[X86][MC] Fix the bug of -output-asm-variant=1 for intel syntax

[skan]

Summary

Before this patch

$ echo "leal    (,%r15), %eax" | llvm-mc --show-encoding --output-asm-variant=1

        lea     eax, [r15]                      # encoding: [0x42,0x8d,0x04,0x3d,0x00,0x00,0x00,0x00]

$ echo "lea     eax, [r15]" | llvm-mc --show-encoding -x86-asm-syntax=intel --output-asm-variant=1

        lea     eax, [r15]                      # encoding: [0x41,0x8d,0x07]

MC printed the register r15 as a base in intel syntax even when it's an index.
Then we got a different encoding by using the assembly from the output of the
first command.

I believe the behavior is too weird to be called a feature.

After this patch, we get

$ echo "leal    (,%r15), %eax" | llvm-mc --show-encoding --output-asm-variant=1

        lea     eax, [1*r15]                    # encoding: [0x42,0x8d,0x04,0x3d,0x00,0x00,0x00,0x00]

[pengfei]

LG.

llvm/test/MC/Disassembler/X86/intel-syntax.txt

176–181

Too many spaces.

[skan]

Address review comments: remove some space

[RKSimon]

LGTM - cheers

[MaskRay]

llvm/test/MC/Disassembler/X86/intel-syntax.txt

177

Shall we add a test with a non-zero displacement like lea eax, [1*r15+4]?

[MaskRay]

I believe the behavior is too weird to be called a feature.

More importantly, the behavior does not match llvm-mc -filetype=obj. The new behavior matches llvm-mc -filetype=obj and as -msyntax=intel -mnaked-reg.

[skan]

Address review comments: add 2 more tests

[skan]

In D144183#4132541, @MaskRay wrote:

I believe the behavior is too weird to be called a feature.

More importantly, the behavior does not match llvm-mc -filetype=obj. The new behavior matches llvm-mc -filetype=obj and as -msyntax=intel -mnaked-reg.

The encoding is right, w/o this patch, we can get still get a correct encoding for "lea eax, [1*r15] " with llvm-mc. The issue here is that the output assembly is incorrect.

llvm/test/MC/Disassembler/X86/intel-syntax.txt

177

Good suggestion. Done.

llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.cpp

void X86IntelInstPrinter::printMemReference(const MCInst *MI, unsigned Op,
   bool NeedPlus = false;
   if (BaseReg.getReg()) {
     printOperand(MI, Op+X86::AddrBaseReg, O);
     NeedPlus = true;
   }
 
   if (IndexReg.getReg()) {
     if (NeedPlus) O << " + ";
-    if (ScaleVal != 1)
+    if (ScaleVal != 1 || !BaseReg.getReg())
       O << ScaleVal << '*';
     printOperand(MI, Op+X86::AddrIndexReg, O);
     NeedPlus = true;
   }
 
   if (!DispSpec.isImm()) {
     if (NeedPlus) O << " + ";
     assert(DispSpec.isExpr() && "non-immediate displacement for LEA?");

llvm/test/MC/Disassembler/X86/intel-syntax.txt

 0x66 0x8d 0x4c 0x24 0x04 
 
 # CHECK: lea  ecx, [rsp + 4]
 0x8d 0x4c 0x24 0x04 
 
 # CHECK: lea  rcx, [rsp + 4]
 0x48 0x8d 0x4c 0x24 0x04 
 
+# CHECK: lea  rcx, [1*rax]
+0x48 0x8d 0x0c 0x05 0x00 0x00 0x00 0x00
 
+# CHECK: lea  rcx, [1*rax + 4]
+0x48 0x8d 0x0c 0x05 0x04 0x00 0x00 0x00
+
+# CHECK: lea  rcx, [2*rax]
+0x48 0x8d 0x0c 0x45 0x00 0x00 0x00 0x00