AMDGPU/MC: Fix decoders for VSrc_v2b32 and VSrc_v2f32 RegisterOperands

[Petar.Avramovic]

Summary

Decoder should make 32 bit value when decoding immediates, not 64 bit.

[dp]

LGTM.

llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp

 
 DECODE_OPERAND_SRC_REG_OR_IMM_9(SReg_64, OPW64, 64)
 DECODE_OPERAND_SRC_REG_OR_IMM_9(SReg_32, OPW32, 32)
 DECODE_OPERAND_SRC_REG_OR_IMM_9(SRegOrLds_32, OPW32, 32)
 DECODE_OPERAND_SRC_REG_OR_IMM_9(VS_32_Lo128, OPW16, 16)
 DECODE_OPERAND_SRC_REG_OR_IMM_9(VS_32, OPW32, 16)
 DECODE_OPERAND_SRC_REG_OR_IMM_9(VS_32, OPW32, 32)
 DECODE_OPERAND_SRC_REG_OR_IMM_9(VS_64, OPW64, 64)
+DECODE_OPERAND_SRC_REG_OR_IMM_9(VS_64, OPW64, 32)
 DECODE_OPERAND_SRC_REG_OR_IMM_9(VReg_64, OPW64, 64)
 DECODE_OPERAND_SRC_REG_OR_IMM_9(VReg_128, OPW128, 32)
 DECODE_OPERAND_SRC_REG_OR_IMM_9(VReg_256, OPW256, 64)
 DECODE_OPERAND_SRC_REG_OR_IMM_9(VReg_512, OPW512, 32)
 DECODE_OPERAND_SRC_REG_OR_IMM_9(VReg_1024, OPW1024, 32)
 
 DECODE_OPERAND_SRC_REG_OR_IMM_A9(AReg_64, OPW64, 64)
 DECODE_OPERAND_SRC_REG_OR_IMM_A9(AReg_128, OPW128, 32)

llvm/lib/Target/AMDGPU/SIRegisterInfo.td

: RegOrImmOperand <RegisterClass, OperandTypePrefix # "_FP64",
                      !subst("_f64", "F64", NAME), "_Imm64">;
 
 class RegOrB64 <string RegisterClass, string OperandTypePrefix>
   : RegOrImmOperand <RegisterClass, OperandTypePrefix # "_INT64",
                      !subst("_b64", "B64", NAME), "_Imm64">;
 
 class RegOrV2F32 <string RegisterClass, string OperandTypePrefix>
   : RegOrImmOperand <RegisterClass, OperandTypePrefix # "_V2FP32",
-                     !subst("_v2f32", "V2FP32", NAME), "_Imm64">;
+                     !subst("_v2f32", "V2FP32", NAME), "_Imm32">;
 
 class RegOrV2B32 <string RegisterClass, string OperandTypePrefix>
   : RegOrImmOperand <RegisterClass, OperandTypePrefix # "_V2INT32",
-                     !subst("_v2b32", "V2INT32", NAME), "_Imm64">;
+                     !subst("_v2b32", "V2INT32", NAME), "_Imm32">;
 
 // For VOP1,2,C True16 instructions. _Lo128 use first 128 32-bit VGPRs only.
 class RegOrB16_Lo128 <string RegisterClass, string OperandTypePrefix>
   : RegOrImmOperand <RegisterClass, OperandTypePrefix # "_INT16",
                      !subst("_b16_Lo128", "B16_Lo128", NAME), "_Imm16">;
 
 class RegOrF16_Lo128 <string RegisterClass, string OperandTypePrefix>
   : RegOrImmOperand <RegisterClass, OperandTypePrefix # "_FP16",

llvm/test/MC/Disassembler/AMDGPU/gfx90a_features.txt

 0x08,0x44,0xb0,0xd3,0x00,0x01,0x10,0x1c
 
 # GFX90A: v_pk_fma_f32 v[8:9], v[0:1], s[0:1], v[4:5] clamp ; encoding: [0x08,0xc0,0xb0,0xd3,0x00,0x01,0x10,0x1c]
 0x08,0xc0,0xb0,0xd3,0x00,0x01,0x10,0x1c
 
 # GFX90A: v_pk_fma_f32 v[0:1], v[4:5], v[8:9], v[16:17] ; encoding: [0x00,0x40,0xb0,0xd3,0x04,0x11,0x42,0x1c]
 0x00,0x40,0xb0,0xd3,0x04,0x11,0x42,0x1c
 
-# GFX90A: v_pk_fma_f32 v[0:1], v[2:3], v[4:5], 0  ; encoding: [0x00,0x40,0xb0,0xd3,0x02,0x09,0x02,0x1a]
+# GFX90A: v_pk_fma_f32 v[0:1], v[2:3], v[4:5], 1.0 ; encoding: [0x00,0x40,0xb0,0xd3,0x02,0x09,0xca,0x1b]
 0x00,0x40,0xb0,0xd3,0x02,0x09,0xca,0x1b
 
 # GFX90A: v_pk_mul_f32 v[254:255], v[8:9], v[16:17] ; encoding: [0xfe,0x40,0xb1,0xd3,0x08,0x21,0x02,0x18]
 0xfe,0x00,0xb1,0xd3,0x08,0x21,0x02,0x18
 
 # GFX90A: v_pk_mul_f32 v[4:5], v[254:255], v[16:17] ; encoding: [0x04,0x40,0xb1,0xd3,0xfe,0x21,0x02,0x18]
 0x04,0x00,0xb1,0xd3,0xfe,0x21,0x02,0x18
 

 0x04,0x02,0xb1,0xd3,0x08,0x21,0x02,0x18
 
 # GFX90A: v_pk_mul_f32 v[4:5], v[8:9], v[16:17] neg_hi:[1,1] ; encoding: [0x04,0x43,0xb1,0xd3,0x08,0x21,0x02,0x18]
 0x04,0x03,0xb1,0xd3,0x08,0x21,0x02,0x18
 
 # GFX90A: v_pk_mul_f32 v[4:5], v[8:9], v[16:17] clamp ; encoding: [0x04,0xc0,0xb1,0xd3,0x08,0x21,0x02,0x18]
 0x04,0x80,0xb1,0xd3,0x08,0x21,0x02,0x18
 
-# GFX90A: v_pk_mul_f32 v[0:1], v[2:3], 0 ; encoding: [0x00,0x40,0xb1,0xd3,0x02,0x01,0x01,0x18]
+# GFX90A: v_pk_mul_f32 v[0:1], v[2:3], 1.0 ; encoding: [0x00,0x40,0xb1,0xd3,0x02,0xe5,0x01,0x18]
 0x00,0x40,0xb1,0xd3,0x02,0xe5,0x01,0x18
 
 # GFX90A: v_pk_add_f32 v[254:255], v[8:9], v[16:17] ; encoding: [0xfe,0x40,0xb2,0xd3,0x08,0x21,0x02,0x18]
 0xfe,0x00,0xb2,0xd3,0x08,0x21,0x02,0x18
 
 # GFX90A: v_pk_add_f32 v[4:5], v[254:255], v[16:17] ; encoding: [0x04,0x40,0xb2,0xd3,0xfe,0x21,0x02,0x18]
 0x04,0x00,0xb2,0xd3,0xfe,0x21,0x02,0x18
 

 0x04,0x02,0xb2,0xd3,0x08,0x21,0x02,0x18
 
 # GFX90A: v_pk_add_f32 v[4:5], v[8:9], v[16:17] neg_hi:[1,1] ; encoding: [0x04,0x43,0xb2,0xd3,0x08,0x21,0x02,0x18]
 0x04,0x03,0xb2,0xd3,0x08,0x21,0x02,0x18
 
 # GFX90A: v_pk_add_f32 v[4:5], v[8:9], v[16:17] clamp ; encoding: [0x04,0xc0,0xb2,0xd3,0x08,0x21,0x02,0x18]
 0x04,0x80,0xb2,0xd3,0x08,0x21,0x02,0x18
 
-# GFX90A: v_pk_add_f32 v[0:1], v[2:3], 0 ; encoding: [0x00,0x40,0xb2,0xd3,0x02,0x01,0x01,0x18]
+# GFX90A: v_pk_add_f32 v[0:1], v[2:3], 1.0 ; encoding: [0x00,0x40,0xb2,0xd3,0x02,0xe5,0x01,0x18]
 0x00,0x40,0xb2,0xd3,0x02,0xe5,0x01,0x18
 
 # GFX90A: v_pk_mov_b32 v[0:1], v[2:3], v[4:5] ; encoding: [0x00,0x40,0xb3,0xd3,0x02,0x09,0x02,0x18]
 0x00,0x00,0xb3,0xd3,0x02,0x09,0x02,0x18
 
 # GFX90A: v_pk_mov_b32 v[0:1], flat_scratch, v[4:5] ; encoding: [0x00,0x40,0xb3,0xd3,0x66,0x08,0x02,0x18]
 0x00,0x00,0xb3,0xd3,0x66,0x08,0x02,0x18
 

 0x00,0x08,0xb3,0xd3,0x02,0x09,0x02,0x18
 
 # GFX90A: v_pk_mov_b32 v[0:1], v[2:3], v[4:5] op_sel:[1,1] ; encoding: [0x00,0x58,0xb3,0xd3,0x02,0x09,0x02,0x18]
 0x00,0x18,0xb3,0xd3,0x02,0x09,0x02,0x18
 
 # GFX90A: v_pk_mov_b32 v[0:1], v[2:3], 4 ; encoding: [0x00,0x40,0xb3,0xd3,0x02,0x09,0x01,0x18]
 0x00,0x40,0xb3,0xd3,0x02,0x09,0x01,0x18
 
-# GFX90A: v_pk_mov_b32 v[0:1], v[2:3], 0 ; encoding: [0x00,0x40,0xb3,0xd3,0x02,0x01,0x01,0x18]
+# GFX90A: v_pk_mov_b32 v[0:1], v[2:3], 2.0 ; encoding: [0x00,0x40,0xb3,0xd3,0x02,0xe9,0x01,0x18]
 0x00,0x40,0xb3,0xd3,0x02,0xe9,0x01,0x18
 
 # GFX90A: buffer_wbl2 ; encoding: [0x00,0x00,0xa0,0xe0,0x00,0x00,0x00,0x00]
 0x00,0x00,0xa0,0xe0,0x00,0x00,0x00,0x00
 
 # GFX90A: buffer_invl2 ; encoding: [0x00,0x00,0xa4,0xe0,0x00,0x00,0x00,0x00]
 0x00,0x00,0xa4,0xe0,0x00,0x00,0x00,0x00