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Differential D143517

[AArch64][GlobalISel] Legalize wide s8/s16 vectors G_ADD/G_MUL/G_OR/...
ClosedPublic

Authored by dzhidzhoev on Feb 7 2023, 10:11 AM.

Details

Reviewers
aemerson
arsenm
t.p.northover
paquette
Commits
rG90c98f8e5516: [AArch64][GlobalISel] Legalize wide s8/s16 vectors G_ADD/G_MUL/G_OR/...
Summary

Clamp the max number of elements of s8/s16 vectors when legalizing G_ADD,
G_SUB, G_MUL, G_AND, G_OR, G_XOR, in order to support some wide vectors.

Fixes https://github.com/llvm/llvm-project/issues/58156.

Diff Detail

Event Timeline

dzhidzhoev created this revision.Feb 7 2023, 10:11 AM
Herald added a project: Restricted Project. · View Herald TranscriptFeb 7 2023, 10:11 AM
Herald added subscribers: hiraditya, kristof.beyls. · View Herald Transcript
dzhidzhoev requested review of this revision.Feb 7 2023, 10:11 AM
Herald added a project: Restricted Project. · View Herald TranscriptFeb 7 2023, 10:11 AM
Herald added subscribers: llvm-commits, wdng. · View Herald Transcript
aemerson accepted this revision.Feb 7 2023, 10:26 AM

LGTM, thanks!

This revision is now accepted and ready to land.Feb 7 2023, 10:26 AM
Harbormaster completed remote builds in B212430: Diff 495584.Feb 7 2023, 12:30 PM
Closed by commit rG90c98f8e5516: [AArch64][GlobalISel] Legalize wide s8/s16 vectors G_ADD/G_MUL/G_OR/... (authored by dzhidzhoev). · Explain WhyFeb 7 2023, 12:34 PM
This revision was automatically updated to reflect the committed changes.
dzhidzhoev added a commit: rG90c98f8e5516: [AArch64][GlobalISel] Legalize wide s8/s16 vectors G_ADD/G_MUL/G_OR/....

Revision Contents

PathSize
llvm/
lib/
Target/
AArch64/
GISel/
2 lines
test/
CodeGen/
AArch64/
GlobalISel/
40 lines
40 lines
40 lines
40 lines
40 lines
40 lines

Diff 495584

llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp

Show First 20 Lines • Show All 120 Lines • ▼ Show 20 Lines getActionDefinitionsBuilder({G_ADD, G_SUB, G_MUL, G_AND, G_OR, G_XOR})
.scalarizeIf( .scalarizeIf(
[=](const LegalityQuery &Query) { [=](const LegalityQuery &Query) {
return Query.Opcode == G_MUL && Query.Types[0] == v2s64; return Query.Opcode == G_MUL && Query.Types[0] == v2s64;
}, },
0) 0)
.legalFor({v2s64}) .legalFor({v2s64})
.widenScalarToNextPow2(0) .widenScalarToNextPow2(0)
.clampScalar(0, s32, s64) .clampScalar(0, s32, s64)
.clampMaxNumElements(0, s8, 16)
.clampMaxNumElements(0, s16, 8)
.clampNumElements(0, v2s32, v4s32) .clampNumElements(0, v2s32, v4s32)
.clampNumElements(0, v2s64, v2s64) .clampNumElements(0, v2s64, v2s64)
.minScalarOrEltIf( .minScalarOrEltIf(
[=](const LegalityQuery &Query) { [=](const LegalityQuery &Query) {
return Query.Types[0].getNumElements() <= 2; return Query.Types[0].getNumElements() <= 2;
}, },
0, s32) 0, s32)
.minScalarOrEltIf( .minScalarOrEltIf(
▲ Show 20 Lines • Show All 1,495 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/GlobalISel/legalize-add.mir

Show First 20 Lines • Show All 159 Lines • ▼ Show 20 Lines bb.0.entry:
%5:_(<4 x s64>) = G_CONCAT_VECTORS %2, %3 %5:_(<4 x s64>) = G_CONCAT_VECTORS %2, %3
%6:_(<4 x s64>) = G_ADD %4, %5 %6:_(<4 x s64>) = G_ADD %4, %5
%7:_(<2 x s64>), %8:_(<2 x s64>) = G_UNMERGE_VALUES %6(<4 x s64>) %7:_(<2 x s64>), %8:_(<2 x s64>) = G_UNMERGE_VALUES %6(<4 x s64>)
$q0 = COPY %7(<2 x s64>) $q0 = COPY %7(<2 x s64>)
$q1 = COPY %8(<2 x s64>) $q1 = COPY %8(<2 x s64>)
... ...
--- ---
name: test_vector_add_v16s16
body: |
bb.0.entry:
; CHECK-LABEL: name: test_vector_add_v16s16
; CHECK: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $q1
; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<8 x s16>) = G_ADD [[COPY]], [[COPY]]
; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(<8 x s16>) = G_ADD [[COPY1]], [[COPY1]]
; CHECK-NEXT: $q0 = COPY [[ADD]](<8 x s16>)
; CHECK-NEXT: $q1 = COPY [[ADD1]](<8 x s16>)
%1:_(<8 x s16>) = COPY $q0
%2:_(<8 x s16>) = COPY $q1
%0:_(<16 x s16>) = G_CONCAT_VECTORS %1(<8 x s16>), %2(<8 x s16>)
%3:_(<16 x s16>) = G_ADD %0, %0
%4:_(<8 x s16>), %5:_(<8 x s16>) = G_UNMERGE_VALUES %3(<16 x s16>)
$q0 = COPY %4(<8 x s16>)
$q1 = COPY %5(<8 x s16>)
...
---
name: test_vector_add_v32s8
body: |
bb.0.entry:
; CHECK-LABEL: name: test_vector_add_v32s8
; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1
; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<16 x s8>) = G_ADD [[COPY]], [[COPY]]
; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(<16 x s8>) = G_ADD [[COPY1]], [[COPY1]]
; CHECK-NEXT: $q0 = COPY [[ADD]](<16 x s8>)
; CHECK-NEXT: $q1 = COPY [[ADD1]](<16 x s8>)
%0:_(<16 x s8>) = COPY $q0
%1:_(<16 x s8>) = COPY $q1
%2:_(<32 x s8>) = G_CONCAT_VECTORS %0, %1
%3:_(<32 x s8>) = G_ADD %2, %2
%7:_(<16 x s8>), %8:_(<16 x s8>) = G_UNMERGE_VALUES %3(<32 x s8>)
$q0 = COPY %7(<16 x s8>)
$q1 = COPY %8(<16 x s8>)
...
---
name: test_vector_add_nonpow2 name: test_vector_add_nonpow2
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK-LABEL: name: test_vector_add_nonpow2 ; CHECK-LABEL: name: test_vector_add_nonpow2
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0 ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s64>) = COPY $q2 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s64>) = COPY $q2
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<2 x s64>) = COPY $q3 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<2 x s64>) = COPY $q3
▲ Show 20 Lines • Show All 265 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/GlobalISel/legalize-and.mir

Show First 20 Lines • Show All 155 Lines • ▼ Show 20 Lines bb.0:
%b:_(s318) = G_IMPLICIT_DEF %b:_(s318) = G_IMPLICIT_DEF
%ptr:_(p0) = COPY $x0 %ptr:_(p0) = COPY $x0
%and:_(s318) = G_AND %a, %b %and:_(s318) = G_AND %a, %b
G_STORE %and(s318), %ptr(p0) :: (store (s318)) G_STORE %and(s318), %ptr(p0) :: (store (s318))
RET_ReallyLR implicit $x0 RET_ReallyLR implicit $x0
... ...
--- ---
name: test_vector_and_v16s16
body: |
bb.0.entry:
; CHECK-LABEL: name: test_vector_and_v16s16
; CHECK: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $q1
; CHECK-NEXT: [[AND:%[0-9]+]]:_(<8 x s16>) = G_AND [[COPY]], [[COPY]]
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<8 x s16>) = G_AND [[COPY1]], [[COPY1]]
; CHECK-NEXT: $q0 = COPY [[AND]](<8 x s16>)
; CHECK-NEXT: $q1 = COPY [[AND1]](<8 x s16>)
%1:_(<8 x s16>) = COPY $q0
%2:_(<8 x s16>) = COPY $q1
%0:_(<16 x s16>) = G_CONCAT_VECTORS %1(<8 x s16>), %2(<8 x s16>)
%3:_(<16 x s16>) = G_AND %0, %0
%4:_(<8 x s16>), %5:_(<8 x s16>) = G_UNMERGE_VALUES %3(<16 x s16>)
$q0 = COPY %4(<8 x s16>)
$q1 = COPY %5(<8 x s16>)
...
---
name: test_vector_and_v32s8
body: |
bb.0.entry:
; CHECK-LABEL: name: test_vector_and_v32s8
; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1
; CHECK-NEXT: [[AND:%[0-9]+]]:_(<16 x s8>) = G_AND [[COPY]], [[COPY]]
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<16 x s8>) = G_AND [[COPY1]], [[COPY1]]
; CHECK-NEXT: $q0 = COPY [[AND]](<16 x s8>)
; CHECK-NEXT: $q1 = COPY [[AND1]](<16 x s8>)
%0:_(<16 x s8>) = COPY $q0
%1:_(<16 x s8>) = COPY $q1
%2:_(<32 x s8>) = G_CONCAT_VECTORS %0, %1
%3:_(<32 x s8>) = G_AND %2, %2
%7:_(<16 x s8>), %8:_(<16 x s8>) = G_UNMERGE_VALUES %3(<32 x s8>)
$q0 = COPY %7(<16 x s8>)
$q1 = COPY %8(<16 x s8>)
...
---
name: and_v2s1 name: and_v2s1
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.1: bb.1:
liveins: $d0, $d1, $d2, $d3 liveins: $d0, $d1, $d2, $d3
; CHECK-LABEL: name: and_v2s1 ; CHECK-LABEL: name: and_v2s1
; CHECK: liveins: $d0, $d1, $d2, $d3 ; CHECK: liveins: $d0, $d1, $d2, $d3
▲ Show 20 Lines • Show All 145 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir

Show First 20 Lines • Show All 452 Lines • ▼ Show 20 Lines bb.1:
%0:_(<4 x s32>) = COPY $q0 %0:_(<4 x s32>) = COPY $q0
%1:_(<4 x s32>) = COPY $q1 %1:_(<4 x s32>) = COPY $q1
%mul:_(<4 x s32>) = G_SMULH %0, %1 %mul:_(<4 x s32>) = G_SMULH %0, %1
$q0 = COPY %mul(<4 x s32>) $q0 = COPY %mul(<4 x s32>)
RET_ReallyLR implicit $q0 RET_ReallyLR implicit $q0
... ...
--- ---
name: test_vector_mul_v16s16
body: |
bb.0.entry:
; CHECK-LABEL: name: test_vector_mul_v16s16
; CHECK: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $q1
; CHECK-NEXT: [[MUL:%[0-9]+]]:_(<8 x s16>) = G_MUL [[COPY]], [[COPY]]
; CHECK-NEXT: [[MUL1:%[0-9]+]]:_(<8 x s16>) = G_MUL [[COPY1]], [[COPY1]]
; CHECK-NEXT: $q0 = COPY [[MUL]](<8 x s16>)
; CHECK-NEXT: $q1 = COPY [[MUL1]](<8 x s16>)
%1:_(<8 x s16>) = COPY $q0
%2:_(<8 x s16>) = COPY $q1
%0:_(<16 x s16>) = G_CONCAT_VECTORS %1(<8 x s16>), %2(<8 x s16>)
%3:_(<16 x s16>) = G_MUL %0, %0
%4:_(<8 x s16>), %5:_(<8 x s16>) = G_UNMERGE_VALUES %3(<16 x s16>)
$q0 = COPY %4(<8 x s16>)
$q1 = COPY %5(<8 x s16>)
...
---
name: test_vector_mul_v32s8
body: |
bb.0.entry:
; CHECK-LABEL: name: test_vector_mul_v32s8
; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1
; CHECK-NEXT: [[MUL:%[0-9]+]]:_(<16 x s8>) = G_MUL [[COPY]], [[COPY]]
; CHECK-NEXT: [[MUL1:%[0-9]+]]:_(<16 x s8>) = G_MUL [[COPY1]], [[COPY1]]
; CHECK-NEXT: $q0 = COPY [[MUL]](<16 x s8>)
; CHECK-NEXT: $q1 = COPY [[MUL1]](<16 x s8>)
%0:_(<16 x s8>) = COPY $q0
%1:_(<16 x s8>) = COPY $q1
%2:_(<32 x s8>) = G_CONCAT_VECTORS %0, %1
%3:_(<32 x s8>) = G_MUL %2, %2
%7:_(<16 x s8>), %8:_(<16 x s8>) = G_UNMERGE_VALUES %3(<32 x s8>)
$q0 = COPY %7(<16 x s8>)
$q1 = COPY %8(<16 x s8>)
...
---
name: mul_v2s1 name: mul_v2s1
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.1: bb.1:
liveins: $d0, $d1, $d2, $d3 liveins: $d0, $d1, $d2, $d3
; CHECK-LABEL: name: mul_v2s1 ; CHECK-LABEL: name: mul_v2s1
; CHECK: liveins: $d0, $d1, $d2, $d3 ; CHECK: liveins: $d0, $d1, $d2, $d3
▲ Show 20 Lines • Show All 145 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/GlobalISel/legalize-or.mir

Show First 20 Lines • Show All 95 Lines • ▼ Show 20 Lines bb.0:
%b:_(s318) = G_IMPLICIT_DEF %b:_(s318) = G_IMPLICIT_DEF
%ptr:_(p0) = COPY $x0 %ptr:_(p0) = COPY $x0
%or:_(s318) = G_OR %a, %b %or:_(s318) = G_OR %a, %b
G_STORE %or(s318), %ptr(p0) :: (store (s318)) G_STORE %or(s318), %ptr(p0) :: (store (s318))
RET_ReallyLR implicit $x0 RET_ReallyLR implicit $x0
... ...
--- ---
name: test_vector_or_v16s16
body: |
bb.0.entry:
; CHECK-LABEL: name: test_vector_or_v16s16
; CHECK: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $q1
; CHECK-NEXT: [[OR:%[0-9]+]]:_(<8 x s16>) = G_OR [[COPY]], [[COPY]]
; CHECK-NEXT: [[OR1:%[0-9]+]]:_(<8 x s16>) = G_OR [[COPY1]], [[COPY1]]
; CHECK-NEXT: $q0 = COPY [[OR]](<8 x s16>)
; CHECK-NEXT: $q1 = COPY [[OR1]](<8 x s16>)
%1:_(<8 x s16>) = COPY $q0
%2:_(<8 x s16>) = COPY $q1
%0:_(<16 x s16>) = G_CONCAT_VECTORS %1(<8 x s16>), %2(<8 x s16>)
%3:_(<16 x s16>) = G_OR %0, %0
%4:_(<8 x s16>), %5:_(<8 x s16>) = G_UNMERGE_VALUES %3(<16 x s16>)
$q0 = COPY %4(<8 x s16>)
$q1 = COPY %5(<8 x s16>)
...
---
name: test_vector_or_v32s8
body: |
bb.0.entry:
; CHECK-LABEL: name: test_vector_or_v32s8
; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1
; CHECK-NEXT: [[OR:%[0-9]+]]:_(<16 x s8>) = G_OR [[COPY]], [[COPY]]
; CHECK-NEXT: [[OR1:%[0-9]+]]:_(<16 x s8>) = G_OR [[COPY1]], [[COPY1]]
; CHECK-NEXT: $q0 = COPY [[OR]](<16 x s8>)
; CHECK-NEXT: $q1 = COPY [[OR1]](<16 x s8>)
%0:_(<16 x s8>) = COPY $q0
%1:_(<16 x s8>) = COPY $q1
%2:_(<32 x s8>) = G_CONCAT_VECTORS %0, %1
%3:_(<32 x s8>) = G_OR %2, %2
%7:_(<16 x s8>), %8:_(<16 x s8>) = G_UNMERGE_VALUES %3(<32 x s8>)
$q0 = COPY %7(<16 x s8>)
$q1 = COPY %8(<16 x s8>)
...
---
name: or_v2s1 name: or_v2s1
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.1: bb.1:
liveins: $d0, $d1, $d2, $d3 liveins: $d0, $d1, $d2, $d3
; CHECK-LABEL: name: or_v2s1 ; CHECK-LABEL: name: or_v2s1
; CHECK: liveins: $d0, $d1, $d2, $d3 ; CHECK: liveins: $d0, $d1, $d2, $d3
▲ Show 20 Lines • Show All 149 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir

Show First 20 Lines • Show All 75 Lines • ▼ Show 20 Lines bb.0.entry:
%2:_(s8) = G_TRUNC %0(s64) %2:_(s8) = G_TRUNC %0(s64)
%3:_(s8) = G_TRUNC %1(s64) %3:_(s8) = G_TRUNC %1(s64)
%4:_(s8) = G_SUB %2, %3 %4:_(s8) = G_SUB %2, %3
%5:_(s64) = G_ANYEXT %4(s8) %5:_(s64) = G_ANYEXT %4(s8)
$x0 = COPY %5(s64) $x0 = COPY %5(s64)
... ...
--- ---
name: test_vector_sub_v16s16
body: |
bb.0.entry:
; CHECK-LABEL: name: test_vector_sub_v16s16
; CHECK: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $q1
; CHECK-NEXT: [[SUB:%[0-9]+]]:_(<8 x s16>) = G_SUB [[COPY]], [[COPY]]
; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(<8 x s16>) = G_SUB [[COPY1]], [[COPY1]]
; CHECK-NEXT: $q0 = COPY [[SUB]](<8 x s16>)
; CHECK-NEXT: $q1 = COPY [[SUB1]](<8 x s16>)
%1:_(<8 x s16>) = COPY $q0
%2:_(<8 x s16>) = COPY $q1
%0:_(<16 x s16>) = G_CONCAT_VECTORS %1(<8 x s16>), %2(<8 x s16>)
%3:_(<16 x s16>) = G_SUB %0, %0
%4:_(<8 x s16>), %5:_(<8 x s16>) = G_UNMERGE_VALUES %3(<16 x s16>)
$q0 = COPY %4(<8 x s16>)
$q1 = COPY %5(<8 x s16>)
...
---
name: test_vector_sub_v32s8
body: |
bb.0.entry:
; CHECK-LABEL: name: test_vector_sub_v32s8
; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1
; CHECK-NEXT: [[SUB:%[0-9]+]]:_(<16 x s8>) = G_SUB [[COPY]], [[COPY]]
; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(<16 x s8>) = G_SUB [[COPY1]], [[COPY1]]
; CHECK-NEXT: $q0 = COPY [[SUB]](<16 x s8>)
; CHECK-NEXT: $q1 = COPY [[SUB1]](<16 x s8>)
%0:_(<16 x s8>) = COPY $q0
%1:_(<16 x s8>) = COPY $q1
%2:_(<32 x s8>) = G_CONCAT_VECTORS %0, %1
%3:_(<32 x s8>) = G_SUB %2, %2
%7:_(<16 x s8>), %8:_(<16 x s8>) = G_UNMERGE_VALUES %3(<32 x s8>)
$q0 = COPY %7(<16 x s8>)
$q1 = COPY %8(<16 x s8>)
...
---
name: sub_v2s1 name: sub_v2s1
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.1: bb.1:
liveins: $d0, $d1, $d2, $d3 liveins: $d0, $d1, $d2, $d3
; CHECK-LABEL: name: sub_v2s1 ; CHECK-LABEL: name: sub_v2s1
; CHECK: liveins: $d0, $d1, $d2, $d3 ; CHECK: liveins: $d0, $d1, $d2, $d3
▲ Show 20 Lines • Show All 145 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir

Show First 20 Lines • Show All 142 Lines • ▼ Show 20 Lines bb.0:
%b:_(s158) = G_IMPLICIT_DEF %b:_(s158) = G_IMPLICIT_DEF
%ptr:_(p0) = COPY $x0 %ptr:_(p0) = COPY $x0
%xor:_(s158) = G_XOR %a, %b %xor:_(s158) = G_XOR %a, %b
G_STORE %xor(s158), %ptr(p0) :: (store (s158)) G_STORE %xor(s158), %ptr(p0) :: (store (s158))
RET_ReallyLR implicit $x0 RET_ReallyLR implicit $x0
... ...
--- ---
name: test_vector_xor_v16s16
body: |
bb.0.entry:
; CHECK-LABEL: name: test_vector_xor_v16s16
; CHECK: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $q1
; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<8 x s16>) = G_XOR [[COPY]], [[COPY]]
; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(<8 x s16>) = G_XOR [[COPY1]], [[COPY1]]
; CHECK-NEXT: $q0 = COPY [[XOR]](<8 x s16>)
; CHECK-NEXT: $q1 = COPY [[XOR1]](<8 x s16>)
%1:_(<8 x s16>) = COPY $q0
%2:_(<8 x s16>) = COPY $q1
%0:_(<16 x s16>) = G_CONCAT_VECTORS %1(<8 x s16>), %2(<8 x s16>)
%3:_(<16 x s16>) = G_XOR %0, %0
%4:_(<8 x s16>), %5:_(<8 x s16>) = G_UNMERGE_VALUES %3(<16 x s16>)
$q0 = COPY %4(<8 x s16>)
$q1 = COPY %5(<8 x s16>)
...
---
name: test_vector_xor_v32s8
body: |
bb.0.entry:
; CHECK-LABEL: name: test_vector_xor_v32s8
; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1
; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<16 x s8>) = G_XOR [[COPY]], [[COPY]]
; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(<16 x s8>) = G_XOR [[COPY1]], [[COPY1]]
; CHECK-NEXT: $q0 = COPY [[XOR]](<16 x s8>)
; CHECK-NEXT: $q1 = COPY [[XOR1]](<16 x s8>)
%0:_(<16 x s8>) = COPY $q0
%1:_(<16 x s8>) = COPY $q1
%2:_(<32 x s8>) = G_CONCAT_VECTORS %0, %1
%3:_(<32 x s8>) = G_XOR %2, %2
%7:_(<16 x s8>), %8:_(<16 x s8>) = G_UNMERGE_VALUES %3(<32 x s8>)
$q0 = COPY %7(<16 x s8>)
$q1 = COPY %8(<16 x s8>)
...
---
name: xor_v2s1 name: xor_v2s1
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.1: bb.1:
liveins: $d0, $d1, $d2, $d3 liveins: $d0, $d1, $d2, $d3
; CHECK-LABEL: name: xor_v2s1 ; CHECK-LABEL: name: xor_v2s1
; CHECK: liveins: $d0, $d1, $d2, $d3 ; CHECK: liveins: $d0, $d1, $d2, $d3
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