This is an archive of the discontinued LLVM Phabricator instance.

[ARM] Perform lane interleaving from reductions.
ClosedPublic

Authored by dmgreen on Feb 6 2023, 6:58 AM.

Details

Summary

We have a pass for MVE to perform lane interleaving to make use of top/bottom instructions, that adds shuffles before extends and after truncates. This extends it to also start from add reductions, where the order of lanes does not matter so the shuffle is not needed. We need to be careful about not breaking the form of existing reductions, but otherwise can save some instructions and awkward extends.

Diff Detail

Event Timeline

dmgreen created this revision.Feb 6 2023, 6:58 AM
Herald added a project: Restricted Project. · View Herald TranscriptFeb 6 2023, 6:58 AM
dmgreen requested review of this revision.Feb 6 2023, 6:58 AM
Herald added a project: Restricted Project. · View Herald TranscriptFeb 6 2023, 6:58 AM
samtebbs accepted this revision.Feb 6 2023, 8:51 AM

Looks great, thank you.

llvm/lib/Target/ARM/MVELaneInterleavingPass.cpp
294–302

nit: add reductions to the assertion message.

396

It might be good to add a comment or change the function name to explain that it's checking if the instruction is a reduction for which the lane ordering doesn't matter, just to make the purpose more clear.

This revision is now accepted and ready to land.Feb 6 2023, 8:51 AM
This revision was landed with ongoing or failed builds.Feb 7 2023, 6:13 AM
This revision was automatically updated to reflect the committed changes.