[LLDB][RISCV] Add RVV register infos

[Emmmer]

Summary

RVV stands for "RISC-V V Extension", which adds 32 vector registers, and seven unprivileged CSRs (vstart, vxsat, vxrm, vcsr, vtype, vl, vlenb) to a base scalar RISC-V ISA.

The base vector extension is intended to provide general support for data-parallel execution within the 32-bit instruction encoding space, with later vector extensions supporting richer functionality for certain domains.

This patch adds the definitions of RVV registers in RegisterInfos_riscv64.h, whose purpose is to provide support (such as reading, writing, and calculating the offsets) for future register-related functions.

[luismarques]

lldb/source/Plugins/Process/Utility/RegisterInfos_riscv64.h

70

What's the plan to support scalable vectors? How is that handled in LLDB for SVE?

[Emmmer]

lldb/source/Plugins/Process/Utility/RegisterInfos_riscv64.h

70

I just figured out how to support variable byte offsets in RegisterInfos (thanks to the arm implementation). The version that supports SVE will be updated later.

[DavidSpickett]

@kito-cheng any objections? I know nothing about RISCV-V.

lldb wise this is fine, we can debate the crossover with sve support code in later patches if needed.

[kito-cheng]

If so, it’s LGTM

lldb/source/Plugins/Process/Utility/RegisterInfos_riscv64.h

70

My understanding is further support will be added in follow up patches?

[Emmmer]

lldb/source/Plugins/Process/Utility/RegisterInfos_riscv64.h

70

Yes, that's correct! The current implementation with variable byte offsets is a step in the right direction.

[DavidSpickett]

In the time since this was written and landed, I added an extra field to register information. Fixed that here: https://github.com/llvm/llvm-project/commit/ee9a646192db1cc5d1df57d69232fdd2a5c89fc5

lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_riscv64.h

struct GPR {
     uint64_t gpr[32];
   };
 
   struct FPR {
     uint64_t fpr[32];
     uint32_t fcsr;
   };
 
+  struct VPR {
+    // The size should be VLEN*32 in bits, but we don't have VLEN here.
+    void *vpr;
+  };
+
   RegisterInfoPOSIX_riscv64(const lldb_private::ArchSpec &target_arch,
                             lldb_private::Flags flags);
 
   size_t GetGPRSize() const override;
 
   size_t GetFPRSize() const override;
 
   const lldb_private::RegisterInfo *GetRegisterInfo() const override;

lldb/source/Plugins/Process/Utility/RegisterInfos_riscv64.h

#define KIND_HELPER(reg, generic_kind)                                         \
   }
 
 // Generates register kinds array for vector registers
 #define GPR64_KIND(reg, generic_kind) KIND_HELPER(reg, generic_kind)
 
 // FPR register kinds array for vector registers
 #define FPR64_KIND(reg, generic_kind) KIND_HELPER(reg, generic_kind)
 
+// VPR register kinds array for vector registers
+#define VPR_KIND(reg, generic_kind) KIND_HELPER(reg, generic_kind)
+
 // Defines a 64-bit general purpose register
 #define DEFINE_GPR64(reg, generic_kind) DEFINE_GPR64_ALT(reg, reg, generic_kind)
 
 // Defines a 64-bit general purpose register
 #define DEFINE_GPR64_ALT(reg, alt, generic_kind)                               \
   {                                                                            \
     #reg, #alt, 8, GPR_OFFSET(gpr_##reg##_riscv - gpr_first_riscv),            \
     lldb::eEncodingUint, lldb::eFormatHex,                                     \
     GPR64_KIND(gpr_##reg, generic_kind), nullptr, nullptr, nullptr,            \
   }
 
 #define DEFINE_FPR64(reg, generic_kind) DEFINE_FPR64_ALT(reg, reg, generic_kind)
 
 #define DEFINE_FPR64_ALT(reg, alt, generic_kind) DEFINE_FPR_ALT(reg, alt, 8, generic_kind)
 
 #define DEFINE_FPR_ALT(reg, alt, size, generic_kind)                           \
   {                                                                            \
     #reg, #alt, size, FPR_OFFSET(fpr_##reg##_riscv - fpr_first_riscv),         \
     lldb::eEncodingUint, lldb::eFormatHex,                                     \
     FPR64_KIND(fpr_##reg, generic_kind), nullptr, nullptr, nullptr,           \
   }
 
+#define DEFINE_VPR(reg, generic_kind) DEFINE_VPR_ALT(reg, reg, generic_kind)
+
+// Defines a scalable vector register, with default size 128 bits
+// The byte offset 0 is a placeholder, which should be corrected at runtime.
+#define DEFINE_VPR_ALT(reg, alt, generic_kind)                                 \
+  {                                                                            \
+    #reg, #alt, 16, 0, lldb::eEncodingVector, lldb::eFormatVectorOfUInt8,      \
+    VPR_KIND(vpr_##reg, generic_kind), nullptr, nullptr                        \
+  }
+
 // clang-format on
 
 static lldb_private::RegisterInfo g_register_infos_riscv64_le[] = {
     // DEFINE_GPR64(name, GENERIC KIND)
     DEFINE_GPR64(pc, LLDB_REGNUM_GENERIC_PC),
     DEFINE_GPR64_ALT(ra, x1, LLDB_REGNUM_GENERIC_RA),
     DEFINE_GPR64_ALT(sp, x2, LLDB_REGNUM_GENERIC_SP),
     DEFINE_GPR64_ALT(gp, x3, LLDB_INVALID_REGNUM),
static lldb_private::RegisterInfo g_register_infos_riscv64_le[] = {
     DEFINE_FPR64_ALT(fs9, f25, LLDB_INVALID_REGNUM),
     DEFINE_FPR64_ALT(fs10, f26, LLDB_INVALID_REGNUM),
     DEFINE_FPR64_ALT(fs11, f27, LLDB_INVALID_REGNUM),
     DEFINE_FPR64_ALT(ft8, f28, LLDB_INVALID_REGNUM),
     DEFINE_FPR64_ALT(ft9, f29, LLDB_INVALID_REGNUM),
     DEFINE_FPR64_ALT(ft10, f30, LLDB_INVALID_REGNUM),
     DEFINE_FPR64_ALT(ft11, f31, LLDB_INVALID_REGNUM),
     DEFINE_FPR_ALT(fcsr, nullptr, 4, LLDB_INVALID_REGNUM),
+
+    DEFINE_VPR(v0, LLDB_INVALID_REGNUM),
+    DEFINE_VPR(v1, LLDB_INVALID_REGNUM),
+    DEFINE_VPR(v2, LLDB_INVALID_REGNUM),
+    DEFINE_VPR(v3, LLDB_INVALID_REGNUM),
+    DEFINE_VPR(v4, LLDB_INVALID_REGNUM),
+    DEFINE_VPR(v5, LLDB_INVALID_REGNUM),
+    DEFINE_VPR(v6, LLDB_INVALID_REGNUM),
+    DEFINE_VPR(v7, LLDB_INVALID_REGNUM),
+    DEFINE_VPR(v8, LLDB_INVALID_REGNUM),
+    DEFINE_VPR(v9, LLDB_INVALID_REGNUM),
+    DEFINE_VPR(v10, LLDB_INVALID_REGNUM),
+    DEFINE_VPR(v11, LLDB_INVALID_REGNUM),
+    DEFINE_VPR(v12, LLDB_INVALID_REGNUM),
+    DEFINE_VPR(v13, LLDB_INVALID_REGNUM),
+    DEFINE_VPR(v14, LLDB_INVALID_REGNUM),
+    DEFINE_VPR(v15, LLDB_INVALID_REGNUM),
+    DEFINE_VPR(v16, LLDB_INVALID_REGNUM),
+    DEFINE_VPR(v17, LLDB_INVALID_REGNUM),
+    DEFINE_VPR(v18, LLDB_INVALID_REGNUM),
+    DEFINE_VPR(v19, LLDB_INVALID_REGNUM),
+    DEFINE_VPR(v20, LLDB_INVALID_REGNUM),
+    DEFINE_VPR(v21, LLDB_INVALID_REGNUM),
+    DEFINE_VPR(v22, LLDB_INVALID_REGNUM),
+    DEFINE_VPR(v23, LLDB_INVALID_REGNUM),
+    DEFINE_VPR(v24, LLDB_INVALID_REGNUM),
+    DEFINE_VPR(v25, LLDB_INVALID_REGNUM),
+    DEFINE_VPR(v26, LLDB_INVALID_REGNUM),
+    DEFINE_VPR(v27, LLDB_INVALID_REGNUM),
+    DEFINE_VPR(v28, LLDB_INVALID_REGNUM),
+    DEFINE_VPR(v29, LLDB_INVALID_REGNUM),
+    DEFINE_VPR(v30, LLDB_INVALID_REGNUM),
+    DEFINE_VPR(v31, LLDB_INVALID_REGNUM),
 };
 
 #endif // DECLARE_REGISTER_INFOS_RISCV64_STRUCT