[InstCombine][NFC] Update generated variable names in signed-truncation-check.ll

[jmciver]

Summary

Update signed-truncation-check.ll using latest version of update_test_checks.py.

[jmciver]

Rebase onto latest main.

[RKSimon]

LGTM

[jmciver]

@RKSimon Thanks for taking the time to review!

Can you please land on my behalf?

Name: John McIver
Email: [e-mail]

llvm/test/Transforms/InstCombine/signed-truncation-check.ll

 
 ; I'm sure there is a bunch more patterns possible :/
 
 ; This used to trigger an assert, because the icmp's are not direct
 ; operands of the and.
 define i1 @positive_with_extra_and(i32 %arg, i1 %z) {
 ; CHECK-LABEL: @positive_with_extra_and(
 ; CHECK-NEXT:    [[T5_SIMPLIFIED:%.*]] = icmp ult i32 [[ARG:%.*]], 128
-; CHECK-NEXT:    [[TMP1:%.*]] = and i1 [[T5_SIMPLIFIED]], [[Z:%.*]]
-; CHECK-NEXT:    ret i1 [[TMP1]]
+; CHECK-NEXT:    [[T5:%.*]] = and i1 [[T5_SIMPLIFIED]], [[Z:%.*]]
+; CHECK-NEXT:    ret i1 [[T5]]
 ;
   %t1 = icmp sgt i32 %arg, -1
   %t2 = add i32 %arg, 128
   %t3 = icmp ult i32 %t2, 256
   %t4 = and i1 %t1, %z
   %t5 = and i1 %t3, %t4
   ret i1 %t5
 }
;
   %t2 = add i32 %arg, 256 ; should be less than 256
   %t3 = icmp ult i32 %t2, 256
   %t4 = select i1 %t1, i1 %t3, i1 false
   ret i1 %t4
 }
 
 define i1 @negative_not_power_of_two(i32 %arg) {
 ; CHECK-LABEL: @negative_not_power_of_two(
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp eq i32 [[ARG:%.*]], 0
-; CHECK-NEXT:    ret i1 [[TMP1]]
+; CHECK-NEXT:    [[T4:%.*]] = icmp eq i32 [[ARG:%.*]], 0
+; CHECK-NEXT:    ret i1 [[T4]]
 ;
   %t1 = icmp sgt i32 %arg, -1
   %t2 = add i32 %arg, 255 ; should be power of two
   %t3 = icmp ult i32 %t2, 256
   %t4 = and i1 %t1, %t3
   ret i1 %t4
 }
 
 define i1 @negative_not_power_of_two_logical(i32 %arg) {
 ; CHECK-LABEL: @negative_not_power_of_two_logical(
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp eq i32 [[ARG:%.*]], 0
-; CHECK-NEXT:    ret i1 [[TMP1]]
+; CHECK-NEXT:    [[T4:%.*]] = icmp eq i32 [[ARG:%.*]], 0
+; CHECK-NEXT:    ret i1 [[T4]]
 ;
   %t1 = icmp sgt i32 %arg, -1
   %t2 = add i32 %arg, 255 ; should be power of two
   %t3 = icmp ult i32 %t2, 256
   %t4 = select i1 %t1, i1 %t3, i1 false
   ret i1 %t4
 }
 
 define i1 @negative_not_next_power_of_two(i32 %arg) {
 ; CHECK-LABEL: @negative_not_next_power_of_two(
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp ult i32 [[ARG:%.*]], 192
-; CHECK-NEXT:    ret i1 [[TMP1]]
+; CHECK-NEXT:    [[T4:%.*]] = icmp ult i32 [[ARG:%.*]], 192
+; CHECK-NEXT:    ret i1 [[T4]]
 ;
   %t1 = icmp sgt i32 %arg, -1
   %t2 = add i32 %arg, 64 ; should be 256 >> 1
   %t3 = icmp ult i32 %t2, 256
   %t4 = and i1 %t1, %t3
   ret i1 %t4
 }
 
 define i1 @negative_not_next_power_of_two_logical(i32 %arg) {
 ; CHECK-LABEL: @negative_not_next_power_of_two_logical(
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp ult i32 [[ARG:%.*]], 192
-; CHECK-NEXT:    ret i1 [[TMP1]]
+; CHECK-NEXT:    [[T4:%.*]] = icmp ult i32 [[ARG:%.*]], 192
+; CHECK-NEXT:    ret i1 [[T4]]
 ;
   %t1 = icmp sgt i32 %arg, -1
   %t2 = add i32 %arg, 64 ; should be 256 >> 1
   %t3 = icmp ult i32 %t2, 256
   %t4 = select i1 %t1, i1 %t3, i1 false
   ret i1 %t4
 }
 
 define i1 @two_signed_truncation_checks(i32 %arg) {
 ; CHECK-LABEL: @two_signed_truncation_checks(
 ; CHECK-NEXT:    [[TMP1:%.*]] = add i32 [[ARG:%.*]], 128
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp ult i32 [[TMP1]], 256
-; CHECK-NEXT:    ret i1 [[TMP2]]
+; CHECK-NEXT:    [[T5:%.*]] = icmp ult i32 [[TMP1]], 256
+; CHECK-NEXT:    ret i1 [[T5]]
 ;
   %t1 = add i32 %arg, 512
   %t2 = icmp ult i32 %t1, 1024
   %t3 = add i32 %arg, 128
   %t4 = icmp ult i32 %t3, 256
   %t5 = and i1 %t2, %t4
   ret i1 %t5
 }
 
 define i1 @two_signed_truncation_checks_logical(i32 %arg) {
 ; CHECK-LABEL: @two_signed_truncation_checks_logical(
 ; CHECK-NEXT:    [[TMP1:%.*]] = add i32 [[ARG:%.*]], 128
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp ult i32 [[TMP1]], 256
-; CHECK-NEXT:    ret i1 [[TMP2]]
+; CHECK-NEXT:    [[T5:%.*]] = icmp ult i32 [[TMP1]], 256
+; CHECK-NEXT:    ret i1 [[T5]]
 ;
   %t1 = add i32 %arg, 512
   %t2 = icmp ult i32 %t1, 1024
   %t3 = add i32 %arg, 128
   %t4 = icmp ult i32 %t3, 256
   %t5 = select i1 %t2, i1 %t4, i1 false
   ret i1 %t5
 }