[Thumb2] Upgrade intrinsic upgrading code

[barannikov88]

Summary

Enabling opaque pointers has changed the mangled names of these two ARM
intrinsics:

arm.mve.vldr.gather.offset.predicated.v2i64.p0i64.v2i64.v4i1
arm.mve.vstr.scatter.offset.predicated.p0i64.v2i64.v2i64.v4i1

They are now spelled as:

arm.mve.vldr.gather.offset.predicated.v2i64.p0.v2i64.v4i1
arm.mve.vstr.scatter.offset.predicated.p0.v2i64.v2i64.v4i1

Upgrade intrinsic upgrading code to account for the change in names.

[dmgreen]

Thanks for this.

Do you know what happens with old IR and bitcode from a previous release? Will it see the old @llvm.mve.vldr.gather.offset.predicated.v2i64.p0i64.v2i64.v4i1 names when auto-upgrading? Or will that have been converted to @llvm.arm.mve.vstr.scatter.offset.predicated.p0.v2i64.v2i64.v4i1 by an earlier stage?

[nikic]

In D142900#4091015, @dmgreen wrote:

Thanks for this.

Do you know what happens with old IR and bitcode from a previous release? Will it see the old @llvm.mve.vldr.gather.offset.predicated.v2i64.p0i64.v2i64.v4i1 names when auto-upgrading? Or will that have been converted to @llvm.arm.mve.vstr.scatter.offset.predicated.p0.v2i64.v2i64.v4i1 by an earlier stage?

I think it will see the old p0i64 name. That will get remangle-upgraded to the p0 name, but after that the custom auto-upgrade won't be rerun.

So I think the right thing to do here would be to either just add both variants to the list, or modify the test to keep p0i64 in the original input. (I'd personally favor the former, as that should work no matter how the upgrade process works.)

[dmgreen]

That sounds good to me. Thanks for the input.

[barannikov88]

Keep both spellings

[dmgreen]

Thanks. LGTM

llvm/lib/IR/AutoUpgrade.cpp

if (Name == "arm.mve.vctp64" &&
       rename(F);
       return true;
     }
     // These too are changed to accept a v2i1 insteead of the old v4i1.
     if (Name == "arm.mve.mull.int.predicated.v2i64.v4i32.v4i1" ||
         Name == "arm.mve.vqdmull.predicated.v2i64.v4i32.v4i1" ||
         Name == "arm.mve.vldr.gather.base.predicated.v2i64.v2i64.v4i1" ||
         Name == "arm.mve.vldr.gather.base.wb.predicated.v2i64.v2i64.v4i1" ||
-        Name == "arm.mve.vldr.gather.offset.predicated.v2i64.p0i64.v2i64.v4i1" ||
+        Name ==
+            "arm.mve.vldr.gather.offset.predicated.v2i64.p0i64.v2i64.v4i1" ||
+        Name == "arm.mve.vldr.gather.offset.predicated.v2i64.p0.v2i64.v4i1" ||
         Name == "arm.mve.vstr.scatter.base.predicated.v2i64.v2i64.v4i1" ||
         Name == "arm.mve.vstr.scatter.base.wb.predicated.v2i64.v2i64.v4i1" ||
-        Name == "arm.mve.vstr.scatter.offset.predicated.p0i64.v2i64.v2i64.v4i1" ||
+        Name ==
+            "arm.mve.vstr.scatter.offset.predicated.p0i64.v2i64.v2i64.v4i1" ||
+        Name == "arm.mve.vstr.scatter.offset.predicated.p0.v2i64.v2i64.v4i1" ||
         Name == "arm.cde.vcx1q.predicated.v2i64.v4i1" ||
         Name == "arm.cde.vcx1qa.predicated.v2i64.v4i1" ||
         Name == "arm.cde.vcx2q.predicated.v2i64.v4i1" ||
         Name == "arm.cde.vcx2qa.predicated.v2i64.v4i1" ||
         Name == "arm.cde.vcx3q.predicated.v2i64.v4i1" ||
         Name == "arm.cde.vcx3qa.predicated.v2i64.v4i1")
       return true;
 
return Builder.CreateCall(
         Intrinsic::getDeclaration(
             F->getParent(), Intrinsic::arm_mve_pred_i2v,
             {VectorType::get(Builder.getInt1Ty(), 4, false)}),
         C1);
   } else if (Name == "mve.mull.int.predicated.v2i64.v4i32.v4i1" ||
              Name == "mve.vqdmull.predicated.v2i64.v4i32.v4i1" ||
              Name == "mve.vldr.gather.base.predicated.v2i64.v2i64.v4i1" ||
              Name == "mve.vldr.gather.base.wb.predicated.v2i64.v2i64.v4i1" ||
-             Name == "mve.vldr.gather.offset.predicated.v2i64.p0i64.v2i64.v4i1" ||
+             Name ==
+                 "mve.vldr.gather.offset.predicated.v2i64.p0i64.v2i64.v4i1" ||
+             Name == "mve.vldr.gather.offset.predicated.v2i64.p0.v2i64.v4i1" ||
              Name == "mve.vstr.scatter.base.predicated.v2i64.v2i64.v4i1" ||
              Name == "mve.vstr.scatter.base.wb.predicated.v2i64.v2i64.v4i1" ||
-             Name == "mve.vstr.scatter.offset.predicated.p0i64.v2i64.v2i64.v4i1" ||
+             Name ==
+                 "mve.vstr.scatter.offset.predicated.p0i64.v2i64.v2i64.v4i1" ||
+             Name == "mve.vstr.scatter.offset.predicated.p0.v2i64.v2i64.v4i1" ||
              Name == "cde.vcx1q.predicated.v2i64.v4i1" ||
              Name == "cde.vcx1qa.predicated.v2i64.v4i1" ||
              Name == "cde.vcx2q.predicated.v2i64.v4i1" ||
              Name == "cde.vcx2qa.predicated.v2i64.v4i1" ||
              Name == "cde.vcx3q.predicated.v2i64.v4i1" ||
              Name == "cde.vcx3qa.predicated.v2i64.v4i1") {
     std::vector<Type *> Tys;
     unsigned ID = CI->getIntrinsicID();

llvm/test/CodeGen/Thumb2/mve-intrinsics/v2i1-upgrade.ll

entry:
   ret <2 x i64> %5
 }
 
 define arm_aapcs_vfpcc <2 x i64> @test_vldrdq_gather_offset_z_s64(ptr %base, <2 x i64> %offset, i16 zeroext %p) {
 ; CHECK-LABEL: @test_vldrdq_gather_offset_z_s64(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
 ; CHECK-NEXT:    [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
-; CHECK-NEXT:    [[TMP2:%.*]] = call <2 x i64> @llvm.arm.mve.vldr.gather.offset.predicated.v2i64.p0.v2i64.v4i1(ptr [[BASE:%.*]], <2 x i64> [[OFFSET:%.*]], i32 64, i32 0, i32 0, <4 x i1> [[TMP1]])
-; CHECK-NEXT:    ret <2 x i64> [[TMP2]]
+; CHECK-NEXT:    [[TMP2:%.*]] = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> [[TMP1]])
+; CHECK-NEXT:    [[TMP3:%.*]] = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 [[TMP2]])
+; CHECK-NEXT:    [[TMP4:%.*]] = call <2 x i64> @llvm.arm.mve.vldr.gather.offset.predicated.v2i64.p0.v2i64.v2i1(ptr [[BASE:%.*]], <2 x i64> [[OFFSET:%.*]], i32 64, i32 0, i32 0, <2 x i1> [[TMP3]])
+; CHECK-NEXT:    ret <2 x i64> [[TMP4]]
 ;
 entry:
   %0 = zext i16 %p to i32
   %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
   %2 = call <2 x i64> @llvm.arm.mve.vldr.gather.offset.predicated.v2i64.p0.v2i64.v4i1(ptr %base, <2 x i64> %offset, i32 64, i32 0, i32 0, <4 x i1> %1)
   ret <2 x i64> %2
 }
 
entry:
   ret void
 }
 
 define arm_aapcs_vfpcc void @test_vstrdq_scatter_offset_p_s64(ptr %base, <2 x i64> %offset, <2 x i64> %value, i16 zeroext %p) {
 ; CHECK-LABEL: @test_vstrdq_scatter_offset_p_s64(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
 ; CHECK-NEXT:    [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
-; CHECK-NEXT:    call void @llvm.arm.mve.vstr.scatter.offset.predicated.p0.v2i64.v2i64.v4i1(ptr [[BASE:%.*]], <2 x i64> [[OFFSET:%.*]], <2 x i64> [[VALUE:%.*]], i32 64, i32 0, <4 x i1> [[TMP1]])
+; CHECK-NEXT:    [[TMP2:%.*]] = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> [[TMP1]])
+; CHECK-NEXT:    [[TMP3:%.*]] = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 [[TMP2]])
+; CHECK-NEXT:    call void @llvm.arm.mve.vstr.scatter.offset.predicated.p0.v2i64.v2i64.v2i1(ptr [[BASE:%.*]], <2 x i64> [[OFFSET:%.*]], <2 x i64> [[VALUE:%.*]], i32 64, i32 0, <2 x i1> [[TMP3]])
 ; CHECK-NEXT:    ret void
 ;
 entry:
   %0 = zext i16 %p to i32
   %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
   call void @llvm.arm.mve.vstr.scatter.offset.predicated.p0.v2i64.v2i64.v4i1(ptr %base, <2 x i64> %offset, <2 x i64> %value, i32 64, i32 0, <4 x i1> %1)
   ret void
 }