AMDGPU: Put un-initiaized enumerators together in an enum definition.

[cfang]

Summary

For any enumerator whose definition does not have an initializer, the associated value is the value of the previous enumerator plus one.
In order to avoid the possibility that two unrelated enumerators to have the same value, we should try to cluster the uninitialized enumerators together.

[arsenm]

Missing test

[foad]

LGTM even if it is currently NFC.

[cfang]

Add a test.

[arsenm]

llvm/test/CodeGen/AMDGPU/permlane-op-sel.ll

3

Should also add a direct to asm line with -show-mc-encoding to be sure

7

Should check the encoding comments

[cfang]

update test

[Joe_Nash]

1. There is a bug in permlane16 selection I am working on and will put up a patch for soon
2. I'm curious how AMDGPU/permlane-op-sel.ll test passes. When I run the runline "llc -march=amdgcn -mcpu=gfx1030 -show-mc-encoding" using ToT and check the output I get "v_permlane16_b32 v0, v0, s7, s0 op_sel:[1,0] ; encoding: [0x00,0x49,0x77,0xd7,0x00,0x0f,0x00,0x20]" not what is in the check line.

[foad]

llvm/test/CodeGen/AMDGPU/permlane-op-sel.ll

10

This line doesn't do anything because ASM-CHRCK is not a check prefix

[Joe_Nash]

llvm/test/CodeGen/AMDGPU/permlane-op-sel.ll

10

https://reviews.llvm.org/D144519

[foad]

This was closed by 3bde23c5e0b2e7b16aa3a514f8c87a55207ec8c0

llvm/lib/Target/AMDGPU/SIDefines.h

   OPERAND_REG_INLINE_AC_FP16,
   OPERAND_REG_INLINE_AC_FP32,
   OPERAND_REG_INLINE_AC_FP64,
   OPERAND_REG_INLINE_AC_V2INT16,
   OPERAND_REG_INLINE_AC_V2FP16,
   OPERAND_REG_INLINE_AC_V2INT32,
   OPERAND_REG_INLINE_AC_V2FP32,
 
+  // Operand for source modifiers for VOP instructions
+  OPERAND_INPUT_MODS,
+
+  // Operand for SDWA instructions
+  OPERAND_SDWA_VOPC_DST,
+
   OPERAND_REG_IMM_FIRST = OPERAND_REG_IMM_INT32,
   OPERAND_REG_IMM_LAST = OPERAND_REG_IMM_V2FP32,
 
   OPERAND_REG_INLINE_C_FIRST = OPERAND_REG_INLINE_C_INT16,
   OPERAND_REG_INLINE_C_LAST = OPERAND_REG_INLINE_AC_V2FP32,
 
   OPERAND_REG_INLINE_AC_FIRST = OPERAND_REG_INLINE_AC_INT16,
   OPERAND_REG_INLINE_AC_LAST = OPERAND_REG_INLINE_AC_V2FP32,
 
   OPERAND_SRC_FIRST = OPERAND_REG_IMM_INT32,
   OPERAND_SRC_LAST = OPERAND_REG_INLINE_C_LAST,
 
   OPERAND_KIMM_FIRST = OPERAND_KIMM32,
-  OPERAND_KIMM_LAST = OPERAND_KIMM16,
-
-  // Operand for source modifiers for VOP instructions
-  OPERAND_INPUT_MODS,
-
-  // Operand for SDWA instructions
-  OPERAND_SDWA_VOPC_DST
+  OPERAND_KIMM_LAST = OPERAND_KIMM16
 
 };
 }
 
 // Input operand modifiers bit-masks
 // NEG and SEXT share same bit-mask because they can't be set simultaneously.
 namespace SISrcMods {
   enum : unsigned {

llvm/test/CodeGen/AMDGPU/permlane-op-sel.ll

+; RUN: llc -march=amdgcn -mcpu=gfx1030 -filetype=obj < %s | llvm-objdump --triple=amdgcn--amdhsa --mcpu=gfx1030 -d - | FileCheck -check-prefix=OBJ %s
+; RUN: llc -march=amdgcn -mcpu=gfx1030 -show-mc-encoding < %s | FileCheck -check-prefix=ASM %s
+
+declare i32 @llvm.amdgcn.permlane16(i32, i32, i32, i32, i1, i1)
+
+; OBJ-LABEL: <permlane_op_sel>:
+; OBJ: v_permlane16_b32 v0, v0, s7, s0 op_sel:[1,0]
+
+; ASM-LABEL: permlane_op_sel:
+; ASM-CHRCK: v_permlane16_b32 v0, v0, s7, s0 op_sel:[1,0] ; encoding: [0x00,0x00,0x77,0xd7,0x00,0x0f,0x00,0x20]
+define amdgpu_kernel void @permlane_op_sel(ptr addrspace(1) %out, i32 %src0, i32 %src1, i32 %src2) {
+  %v = call i32 @llvm.amdgcn.permlane16(i32 %src0, i32 %src0, i32 %src1, i32 %src2, i1 1, i1 0)
+  store i32 %v, ptr addrspace(1) %out
+  ret void
+}