[AArch64][SME2] MOVA tile-to-vector and vector-to-tile should not accept VG suffix

[MattDevereau]

llvm/lib/Target/AArch64/SMEInstrFormats.td

3472

Given that vgx2 has been removed from this class is it not misleading to still have vg2 in the class and multiclass name? Same goes for the vgx4 variants.

[sdesmalen]

llvm/lib/Target/AArch64/SMEInstrFormats.td

3472

That's probably best done in a separate NFC patch, because it makes this change quite big. It would also mean changing the naming scheme for lots of other instructions (e.g. defm ZIP_VG2_2ZZZ : sme2_zip_vector_vg2<"zip", 0b0>;) which also uses vg2 to mean "two vectors".

[MattDevereau]

llvm/lib/Target/AArch64/SMEInstrFormats.td

3472

Fair enough, I can see these classes and multiclasses are used in quite a lot of places which wouldn't make sense to touch for a small patch like this.

[CarolineConcatto]

Hey Sander,
I am not sure if this class is always used by movaz. In my search it looks it is used by them too.
I also looked at the sme2_mova_tile_or_array_to_vec_aliases, but it looks that one is fine and we don't need to change.

llvm/lib/Target/AArch64/SMEInstrFormats.td

2998

Can you check if this class is also used my movaz?
Because if so, then should movaz also not use vgx?

[MattDevereau]

On second thought the changes do also affect MOVAZ which seems correct as the tile-to-vector variant doesn't accept the vg suffix, but some tests alongside MOV and MOVA are missing here. Thanks @CarolineConcatto

[sdesmalen]

Rebased on top of D142198 and added test-cases for movaz

llvm/lib/Target/AArch64/SMEInstrFormats.td

 // SME2 MOV
 class sme2_mova_vec_to_tile_vg2_multi_base<bits<2> sz, bit v,
                                            RegisterOperand tile_ty,
                                            Operand index_ty,
                                            RegisterOperand vector_ty,
                                            string mnemonic>
    : I<(outs tile_ty:$ZAd),
        (ins tile_ty:$_ZAd, MatrixIndexGPR32Op12_15:$Rs, index_ty:$imm, vector_ty:$Zn),
-       mnemonic, "\t$ZAd[$Rs, $imm, vgx2], $Zn",
+       mnemonic, "\t$ZAd[$Rs, $imm], $Zn",
        "", []>, Sched<[]> {
   bits<2> Rs;
   bits<4> Zn;
   let Inst{31-24} = 0b11000000;
   let Inst{23-22} = sz;
   let Inst{21-16} = 0b000100;
   let Inst{15}    = v;
   let Inst{14-13} = Rs;
class sme2_mova_vec_to_tile_vg4_multi_base<bits<2> sz, bit v, bits<3> op,
                                            RegisterOperand tile_ty,
                                            Operand index_ty,
                                            RegisterOperand vector_ty,
                                            string mnemonic>
    : I<(outs tile_ty:$ZAd),
        (ins tile_ty:$_ZAd, MatrixIndexGPR32Op12_15:$Rs, index_ty:$imm,
             vector_ty:$Zn),
        mnemonic,
-       "\t$ZAd[$Rs, $imm, vgx4], $Zn",
+       "\t$ZAd[$Rs, $imm], $Zn",
        "", []>, Sched<[]> {
   bits<2> Rs;
   bits<3> Zn;
   let Inst{31-24} = 0b11000000;
   let Inst{23-22} = sz;
   let Inst{21-16} = 0b000100;
   let Inst{15}    = v;
   let Inst{14-13} = Rs;
multiclass sme2_mova_vec_to_array_vg4_multi<string mnemonic> {
   defm : sme2_mova_vec_to_tile_or_array_aliases<1, !cast<Instruction>(NAME),
                                                 MatrixOp64,
                                                 MatrixIndexGPR32Op8_11,
                                                 sme_elm_idx0_7, ZZZZ_d_mul_r,
                                                 "mov", "vgx4">;
 
 }
 
 class sme2_mova_tile_to_vec_vg2_multi_base<bits<2> sz, bit v, bits<3> op,
                                            RegisterOperand vector_ty,
                                            RegisterOperand tile_ty,
                                            Operand index_ty,
                                            string mnemonic>
    : I<!if(op{1}, (outs vector_ty:$Zd, tile_ty:$_ZAn), (outs vector_ty:$Zd)),
        (ins tile_ty:$ZAn, MatrixIndexGPR32Op12_15:$Rs, index_ty:$imm),
        mnemonic,
-       "\t$Zd, $ZAn[$Rs, $imm, vgx2]",
+       "\t$Zd, $ZAn[$Rs, $imm]",
        "", []>, Sched<[]> {
   bits<4> Zd;
   bits<2> Rs;
   let Inst{31-24} = 0b11000000;
   let Inst{23-22} = sz;
   let Inst{21-16} = 0b000110;
   let Inst{15}    = v;
   let Inst{14-13} = Rs;

 class sme2_mova_tile_to_vec_vg4_multi_base<bits<2> sz, bit v, bits<6> op,
                                            RegisterOperand vector_ty,
                                            RegisterOperand tile_ty,
                                            Operand index_ty,
                                            string mnemonic>
    : I<!if(op{4}, (outs vector_ty:$Zd, tile_ty:$_ZAn), (outs vector_ty:$Zd)),
        (ins tile_ty:$ZAn, MatrixIndexGPR32Op12_15:$Rs, index_ty:$imm),
        mnemonic,
-       "\t$Zd, $ZAn[$Rs, $imm, vgx4]",
+       "\t$Zd, $ZAn[$Rs, $imm]",
        "", []>, Sched<[]> {
   bits<3> Zd;
   bits<2> Rs;
   let Inst{31-24} = 0b11000000;
   let Inst{23-22} = sz;
   let Inst{21-16} = 0b000110;
   let Inst{15}    = v;
   let Inst{14-13} = Rs;

llvm/test/MC/AArch64/SME2/mova-diagnostics.s

 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected suffix .s
 // CHECK-NEXT: mova {z0.s-z3.s}, za.b[w8, 0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 mov {z0.h-z3.h}, za.d[w8, 0]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected suffix .h
 // CHECK-NEXT: mov {z0.h-z3.h}, za.d[w8, 0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Tile-to-vector and vector-to-tile should not accept the VG suffix
+
+mov za0h.b[w12, 0:1, vgx2], { z0.b, z1.b }
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: mov za0h.b[w12, 0:1, vgx2], { z0.b, z1.b }
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+mov { z0.b, z1.b }, za0h.b[w12, 0:1, vgx2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: mov { z0.b, z1.b }, za0h.b[w12, 0:1, vgx2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+mov za0h.b[w12, 0:3, vgx4], { z0.b - z3.b }
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: mov za0h.b[w12, 0:3, vgx4], { z0.b - z3.b }
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+mov { z0.b - z3.b }, za0h.b[w12, 0:3, vgx4]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: mov { z0.b - z3.b }, za0h.b[w12, 0:3, vgx4]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+mova za0h.b[w12, 0:1, vgx2], { z0.b, z1.b }
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: mova za0h.b[w12, 0:1, vgx2], { z0.b, z1.b }
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+mova { z0.b, z1.b }, za0h.b[w12, 0:1, vgx2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: mova { z0.b, z1.b }, za0h.b[w12, 0:1, vgx2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+mova za0h.b[w12, 0:3, vgx4], { z0.b - z3.b }
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: mova za0h.b[w12, 0:3, vgx4], { z0.b - z3.b }
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+mova { z0.b - z3.b }, za0h.b[w12, 0:3, vgx4]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: mova { z0.b - z3.b }, za0h.b[w12, 0:3, vgx4]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SME2p1/movaz-diagnostics.s

 
 // --------------------------------------------------------------------------//
 // Invalid matrix operand
 
 movaz z31.s, za1h.d[w15, -1]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za[0-3]h.s or za[0-3]v.s
 // CHECK-NEXT: movaz z31.s, za1h.d[w15, -1]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Tile-to-vector should not accept the VG suffix
+
+movaz { z0.b, z1.b }, za0h.b[w12, 0:1, vgx2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: movaz { z0.b, z1.b }, za0h.b[w12, 0:1, vgx2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+movaz { z0.b - z3.b }, za0h.b[w12, 0:3, vgx4]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: movaz { z0.b - z3.b }, za0h.b[w12, 0:3, vgx4]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: