AMDGPU: Remove IsSourceOfDivergence check

[ruiling]

Summary

This bit is not set/reserved in td file. Let's remove it for now,
we can always add it back if we need it.

llvm/lib/Target/AMDGPU/SIDefines.h

enum : uint64_t {
   // Atomic without return.
   IsAtomicNoRet = UINT64_C(1) << 57,
 
   // Atomic with return.
   IsAtomicRet = UINT64_C(1) << 58,
 
   // Is a WMMA instruction.
   IsWMMA = UINT64_C(1) << 59,
-
-  // Is source of divergence.
-  //
-  // Note: There is no corresponding SIInstrInfo::IsSourceOfDivergence method
-  // by design, since this flag only covers opcodes that are _always_ divergent.
-  // Use SIInstrInfo::getInstructionUniformity for a more complete analysis.
-  IsSourceOfDivergence = UINT64_C(1) << 60
 };
 
 // v_cmp_class_* etc. use a 10-bit mask for what operation is checked.
 // The result is true if any of these tests are true.
 enum ClassFlags : unsigned {
   S_NAN = 1 << 0,        // Signaling NaN
   Q_NAN = 1 << 1,        // Quiet NaN
   N_INFINITY = 1 << 2,   // Negative infinity

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

if (SIInstrInfo::isGenericAtomicRMWOpcode(opcode) ||
       opcode == AMDGPU::G_ATOMIC_CMPXCHG_WITH_SUCCESS) {
     return InstructionUniformity::NeverUniform;
   }
   return InstructionUniformity::Default;
 }
 
 InstructionUniformity
 SIInstrInfo::getInstructionUniformity(const MachineInstr &MI) const {
-  if (MI.getDesc().TSFlags & SIInstrFlags::IsSourceOfDivergence)
-    return InstructionUniformity::NeverUniform;
-
   // Atomics are divergent because they are executed sequentially: when an
   // atomic operation refers to the same address in each thread, then each
   // thread after the first sees the value written by the previous thread as
   // original value.
 
   if (isAtomic(MI))
     return InstructionUniformity::NeverUniform;