[VE] Fix useDeprecatedPositionallyEncodedOperands errors.

[jyknight]

Summary

This is a follow-on to https://reviews.llvm.org/D134073.

Behavior is unchanged by this cleanup, except that previously the
'CVTRDm' pattern was accidentally getting the top bit of 'sz' from the
'sx' input, instead of setting it to 0.

[kaz7]

Thank you very much for updating VEInstInfo.td and fixing CVTRDm problem. I have only one comment.

llvm/lib/Target/VE/VEInstrInfo.td

854

Is it possible to not convert "cond" to "cf" please? We use "cond" as condition flag several times in VEInstrInfo.td, so I'd like to make them consitent, either "cond" or "cf". Thanks.

[jyknight]

Rename 'cf' field to 'cond' per review request.

[kaz7]

I didn't realize that we use "cf" in VEInstrFormats.td. Thank you so much. Modified llc works fine, so LGTM.

llvm/lib/Target/VE/VE.td

 //===----------------------------------------------------------------------===//
 // Register File, Calling Conv, Instruction Descriptions
 //===----------------------------------------------------------------------===//
 
 include "VERegisterInfo.td"
 include "VECallingConv.td"
 include "VEInstrInfo.td"
 
-def VEInstrInfo : InstrInfo {
-  let useDeprecatedPositionallyEncodedOperands = 1;
-}
+def VEInstrInfo : InstrInfo {}
 
 def VEAsmParser : AsmParser {
   // Use both VE register name matcher to accept "S0~S63" register names
   // and default register matcher to accept other registeres.
   let AllowDuplicateRegisterNames = 1;
   let ShouldEmitMatchRegisterAltName = 1;
 }
 

llvm/lib/Target/VE/VEInstrInfo.td

 //   e.g. CVTWDSX, CVTWDZX, CVTWSSX, and etc.
 // sz{3-0} = rounding mode
 let cz = 0, hasSideEffects = 0 in
 multiclass CVTRDm<string opcStr, bits<8> opc, RegisterClass RCo,
                   RegisterClass RCi> {
   def r : RR<opc, (outs RCo:$sx), (ins RDOp:$rd, RCi:$sy),
              !strconcat(opcStr, "${rd} $sx, $sy")> {
     bits<4> rd;
-    let sz{5-4} = 0;
+    let sz{6-4} = 0;
     let sz{3-0} = rd;
   }
   let cy = 0 in
   def i : RR<opc, (outs RCo:$sx), (ins RDOp:$rd, simm7:$sy),
              !strconcat(opcStr, "${rd} $sx, $sy")> {
     bits<4> rd;
-    let sz{5-4} = 0;
+    let sz{6-4} = 0;
     let sz{3-0} = rd;
   }
 }
 
 // Multiclass for floating point conversion instructions.
 //   e.g. CVTDW, CVTSW, CVTDL, and etc.
 let cz = 0, sz = 0, hasSideEffects = 0 in
 multiclass CVTm<string opcStr, bits<8> opc, RegisterClass RCo, ValueType Tyo,
                 RegisterClass RCi, ValueType Tyi,
                 SDPatternOperator OpNode = null_frag> {
   def r : RR<opc, (outs RCo:$sx), (ins RCi:$sy),
              !strconcat(opcStr, " $sx, $sy"),
              [(set Tyo:$sx, (OpNode Tyi:$sy))]>;
   let cy = 0 in
   def i : RR<opc, (outs RCo:$sx), (ins simm7:$sy),
              !strconcat(opcStr, " $sx, $sy")>;
 }
 
 // Multiclass for PFCH instructions.
 //   e.g. PFCH
 let sx = 0, hasSideEffects = 0 in
 multiclass PFCHm<string opcStr, bits<8>opc> {
-  def rri : RM<opc, (outs), (ins MEMrri:$addr), !strconcat(opcStr, " $addr"),
+  def rri : RM<opc, (outs), (ins (MEMrri $sz, $sy, $imm32):$addr), !strconcat(opcStr, " $addr"),
                [(prefetch ADDRrri:$addr, imm, imm, (i32 1))]>;
   let cy = 0 in
-  def rii : RM<opc, (outs), (ins MEMrii:$addr), !strconcat(opcStr, " $addr"),
+  def rii : RM<opc, (outs), (ins (MEMrii $sz, $sy, $imm32):$addr), !strconcat(opcStr, " $addr"),
                [(prefetch ADDRrii:$addr, imm, imm, (i32 1))]>;
   let cz = 0 in
-  def zri : RM<opc, (outs), (ins MEMzri:$addr), !strconcat(opcStr, " $addr"),
+  def zri : RM<opc, (outs), (ins (MEMzri $sz, $sy, $imm32):$addr), !strconcat(opcStr, " $addr"),
                [(prefetch ADDRzri:$addr, imm, imm, (i32 1))]>;
   let cy = 0, cz = 0 in
-  def zii : RM<opc, (outs), (ins MEMzii:$addr), !strconcat(opcStr, " $addr"),
+  def zii : RM<opc, (outs), (ins (MEMzii $sz, $sy, $imm32):$addr), !strconcat(opcStr, " $addr"),
                [(prefetch ADDRzii:$addr, imm, imm, (i32 1))]>;
 }
 
 // Multiclass for CAS instructions.
 //   e.g. TS1AML, TS1AMW, TS2AM, and etc.
-let Constraints = "$dest = $sd", DisableEncoding = "$sd",
+let Constraints = "$sx = $sd", DisableEncoding = "$sd",
     mayStore=1, mayLoad = 1, hasSideEffects = 0 in
 multiclass RRCAStgm<string opcStr, bits<8>opc, RegisterClass RC, ValueType Ty,
                     Operand immOp, Operand MEM, ComplexPattern ADDR,
                     SDPatternOperator OpNode = null_frag> {
-  def r : RRM<opc, (outs RC:$dest), (ins MEM:$addr, RC:$sy, RC:$sd),
-              !strconcat(opcStr, " $dest, $addr, $sy"),
-              [(set Ty:$dest, (OpNode ADDR:$addr, Ty:$sy, Ty:$sd))]>;
+  def r : RRM<opc, (outs RC:$sx), (ins (MEM $sz, $imm32):$addr, RC:$sy, RC:$sd),
+              !strconcat(opcStr, " $sx, $addr, $sy"),
+              [(set Ty:$sx, (OpNode ADDR:$addr, Ty:$sy, Ty:$sd))]>;
   let cy = 0 in
-  def i : RRM<opc, (outs RC:$dest), (ins MEM:$addr, immOp:$sy, RC:$sd),
-              !strconcat(opcStr, " $dest, $addr, $sy"),
-              [(set Ty:$dest, (OpNode ADDR:$addr, (Ty immOp:$sy), Ty:$sd))]>;
+  def i : RRM<opc, (outs RC:$sx), (ins (MEM $sz, $imm32):$addr, immOp:$sy, RC:$sd),
+              !strconcat(opcStr, " $sx, $addr, $sy"),
+              [(set Ty:$sx, (OpNode ADDR:$addr, (Ty immOp:$sy), Ty:$sd))]>;
 }
 multiclass RRCASm<string opcStr, bits<8>opc, RegisterClass RC, ValueType Ty,
                   Operand immOp, SDPatternOperator OpNode = null_frag> {
   defm ri : RRCAStgm<opcStr, opc, RC, Ty, immOp, MEMriRRM, ADDRri, OpNode>;
   let cz = 0 in
   defm zi : RRCAStgm<opcStr, opc, RC, Ty, immOp, MEMziRRM, ADDRzi, OpNode>;
 }
 
 // Multiclass for branch instructions
 //   e.g. BCFL, BCFW, BCFD, and etc.
 let isBranch = 1, isTerminator = 1, isIndirectBranch = 1, hasSideEffects = 0 in
 multiclass BCbpfm<string opcStr, string cmpStr, bits<8> opc, dag cond,
                   Operand ADDR> {
   let bpf = 0 /* NONE */ in
-  def "" : CF<opc, (outs), !con(cond, (ins ADDR:$addr)),
+  def "" : CF<opc, (outs), !con(cond, (ins (ADDR $sz, $imm32):$addr)),
               !strconcat(opcStr, " ", cmpStr, "$addr")>;
   let bpf = 2 /* NOT TAKEN */ in
-  def _nt : CF<opc, (outs), !con(cond, (ins ADDR:$addr)),
+  def _nt : CF<opc, (outs), !con(cond, (ins (ADDR $sz, $imm32):$addr)),
                !strconcat(opcStr, ".nt ", cmpStr, "$addr")>;
   let bpf = 3 /* TAKEN */ in
-  def _t : CF<opc, (outs), !con(cond, (ins ADDR:$addr)),
+  def _t : CF<opc, (outs), !con(cond, (ins (ADDR $sz, $imm32):$addr)),
               !strconcat(opcStr, ".t ", cmpStr, "$addr")>;
 }
 multiclass BCtgm<string opcStr, string cmpStr, bits<8> opc, dag cond> {
   defm ri : BCbpfm<opcStr, cmpStr, opc, cond, MEMriASX>;
   let cz = 0 in defm zi : BCbpfm<opcStr, cmpStr, opc, cond, MEMziASX>;
 }
 multiclass BCm<string opcStr, string opcStrAt, string opcStrAf, bits<8> opc,
                RegisterClass RC, Operand immOp> {
   let DecoderMethod = "DecodeBranchCondition" in
-  defm r : BCtgm<opcStr, "$comp, ", opc, (ins CCOp:$cond, RC:$comp)>;
+  defm r : BCtgm<opcStr, "$sy, ", opc, (ins CCOp:$cf, RC:$sy)>;
   let DecoderMethod = "DecodeBranchCondition", cy = 0 in
-  defm i : BCtgm<opcStr, "$comp, ", opc, (ins CCOp:$cond, immOp:$comp)>;
+  defm i : BCtgm<opcStr, "$sy, ", opc, (ins CCOp:$cf, immOp:$sy)>;
   let DecoderMethod = "DecodeBranchConditionAlways", cy = 0, sy = 0,
       cf = 15 /* AT */, isBarrier = 1 in
   defm a : BCtgm<opcStrAt, "", opc, (ins)>;
   let DecoderMethod = "DecodeBranchConditionAlways", cy = 0, sy = 0,
       cf = 0 /* AF */ in
   defm na : BCtgm<opcStrAf, "", opc, (ins)>;
 }
 
def ri : RR<opc, (outs RC:$sx), (ins RC:$sy, uimm3:$sz),
               !strconcat(opcStr, " $sx, $sy, $sz")>;
   let cy = 0 in def ii : RR<opc, (outs RC:$sx), (ins simm7:$sy, uimm3:$sz),
                             !strconcat(opcStr, " $sx, $sy, $sz")>;
 }
 
 // Multiclass for LHM instruction.
 let mayLoad = 1, hasSideEffects = 0 in
 multiclass LHMm<string opcStr, bits<8> opc, RegisterClass RC> {
-  def ri : RRMHM<opc, (outs RC:$dest), (ins MEMriHM:$addr),
-                 !strconcat(opcStr, " $dest, $addr")>;
+  def ri : RRMHM<opc, (outs RC:$sx), (ins (MEMriHM $sz, $imm32):$addr),
+                 !strconcat(opcStr, " $sx, $addr")>;
   let cz = 0 in
-  def zi : RRMHM<opc, (outs RC:$dest), (ins MEMziHM:$addr),
-                 !strconcat(opcStr, " $dest, $addr")>;
+  def zi : RRMHM<opc, (outs RC:$sx), (ins (MEMziHM $sz, $imm32):$addr),
+                 !strconcat(opcStr, " $sx, $addr")>;
 }
 
 // Multiclass for SHM instruction.
 let mayStore = 1, hasSideEffects = 0 in
 multiclass SHMm<string opcStr, bits<8> opc, RegisterClass RC> {
-  def ri : RRMHM<opc, (outs), (ins MEMriHM:$addr, RC:$sx),
+  def ri : RRMHM<opc, (outs), (ins (MEMriHM $sz, $imm32):$addr, RC:$sx),
                  !strconcat(opcStr, " $sx, $addr")>;
   let cz = 0 in
-  def zi : RRMHM<opc, (outs), (ins MEMziHM:$addr, RC:$sx),
+  def zi : RRMHM<opc, (outs), (ins (MEMziHM $sz, $imm32):$addr, RC:$sx),
                  !strconcat(opcStr, " $sx, $addr")>;
 }
 
 //===----------------------------------------------------------------------===//
 // Instructions
 //
 // Define all scalar instructions defined in SX-Aurora TSUBASA Architecture
 // Guide here.  As those mnemonics, we use mnemonics defined in Vector Engine
 // Assembly Language Reference Manual.
 //===----------------------------------------------------------------------===//
 
 //-----------------------------------------------------------------------------
 // Section 8.2 - Load/Store instructions
 //-----------------------------------------------------------------------------
 
 // Multiclass for generic RM instructions
 multiclass RMm<string opcStr, bits<8>opc, RegisterClass RC, bit MoveImm = 0> {
-  def rri : RM<opc, (outs RC:$dest), (ins MEMrri:$addr),
-               !strconcat(opcStr, " $dest, $addr"), []>;
+  def rri : RM<opc, (outs RC:$sx), (ins (MEMrri $sz, $sy, $imm32):$addr),
+               !strconcat(opcStr, " $sx, $addr"), []>;
   let cy = 0 in
-  def rii : RM<opc, (outs RC:$dest), (ins MEMrii:$addr),
-               !strconcat(opcStr, " $dest, $addr"), []>;
+  def rii : RM<opc, (outs RC:$sx), (ins (MEMrii $sz, $sy, $imm32):$addr),
+               !strconcat(opcStr, " $sx, $addr"), []>;
   let cz = 0 in
-  def zri : RM<opc, (outs RC:$dest), (ins MEMzri:$addr),
-               !strconcat(opcStr, " $dest, $addr"), []>;
+  def zri : RM<opc, (outs RC:$sx), (ins (MEMzri $sz, $sy, $imm32):$addr),
+               !strconcat(opcStr, " $sx, $addr"), []>;
   let cy = 0, cz = 0 in
-  def zii : RM<opc, (outs RC:$dest), (ins MEMzii:$addr),
-               !strconcat(opcStr, " $dest, $addr"), []> {
+  def zii : RM<opc, (outs RC:$sx), (ins (MEMzii $sz, $sy, $imm32):$addr),
+               !strconcat(opcStr, " $sx, $addr"), []> {
     // VE uses LEAzii and LEASLzii as a move immediate instruction, so declare
     // it here.  An instruction declared as MoveImm will be optimized in
     // FoldImmediate later.
     let isMoveImm = MoveImm;
   }
 }
 
 // Section 8.2.1 - LEA

 def : Pat<(iPTR ADDRrii:$addr), (LEArii MEMrii:$addr)>;
 def : Pat<(add I64:$base, simm32:$disp), (LEArii $base, 0, (LO32 $disp))>;
 def : Pat<(add I64:$base, lozero:$disp), (LEASLrii $base, 0, (HI32 $disp))>;
 
 // Multiclass for load instructions.
 let mayLoad = 1, hasSideEffects = 0 in
 multiclass LOADm<string opcStr, bits<8> opc, RegisterClass RC, ValueType Ty,
                  SDPatternOperator OpNode = null_frag> {
-  def rri : RM<opc, (outs RC:$dest), (ins MEMrri:$addr),
-               !strconcat(opcStr, " $dest, $addr"),
-               [(set Ty:$dest, (OpNode ADDRrri:$addr))]>;
+  def rri : RM<opc, (outs RC:$sx), (ins (MEMrri $sz, $sy, $imm32):$addr),
+               !strconcat(opcStr, " $sx, $addr"),
+               [(set Ty:$sx, (OpNode ADDRrri:$addr))]>;
   let cy = 0 in
-  def rii : RM<opc, (outs RC:$dest), (ins MEMrii:$addr),
-               !strconcat(opcStr, " $dest, $addr"),
-               [(set Ty:$dest, (OpNode ADDRrii:$addr))]>;
+  def rii : RM<opc, (outs RC:$sx), (ins (MEMrii $sz, $sy, $imm32):$addr),
+               !strconcat(opcStr, " $sx, $addr"),
+               [(set Ty:$sx, (OpNode ADDRrii:$addr))]>;
   let cz = 0 in
-  def zri : RM<opc, (outs RC:$dest), (ins MEMzri:$addr),
-               !strconcat(opcStr, " $dest, $addr"),
-               [(set Ty:$dest, (OpNode ADDRzri:$addr))]>;
+  def zri : RM<opc, (outs RC:$sx), (ins (MEMzri $sz, $sy, $imm32):$addr),
+               !strconcat(opcStr, " $sx, $addr"),
+               [(set Ty:$sx, (OpNode ADDRzri:$addr))]>;
   let cy = 0, cz = 0 in
-  def zii : RM<opc, (outs RC:$dest), (ins MEMzii:$addr),
-               !strconcat(opcStr, " $dest, $addr"),
-               [(set Ty:$dest, (OpNode ADDRzii:$addr))]>;
+  def zii : RM<opc, (outs RC:$sx), (ins (MEMzii $sz, $sy, $imm32):$addr),
+               !strconcat(opcStr, " $sx, $addr"),
+               [(set Ty:$sx, (OpNode ADDRzii:$addr))]>;
 }
 
 // Section 8.2.2 - LDS
 let DecoderMethod = "DecodeLoadI64" in
 defm LD : LOADm<"ld", 0x01, I64, i64, load>;
 def : Pat<(f64 (load ADDRrri:$addr)), (LDrri MEMrri:$addr)>;
 def : Pat<(f64 (load ADDRrii:$addr)), (LDrii MEMrii:$addr)>;
 def : Pat<(f64 (load ADDRzri:$addr)), (LDzri MEMzri:$addr)>;
def LDQrii : Pseudo<(outs F128:$dest), (ins MEMrii:$addr),
                       "# pseudo ldq $dest, $addr",
                       [(set f128:$dest, (load ADDRrii:$addr))]>;
 }
 
 // Multiclass for store instructions.
 let mayStore = 1 in
 multiclass STOREm<string opcStr, bits<8> opc, RegisterClass RC, ValueType Ty,
                   SDPatternOperator OpNode = null_frag> {
-  def rri : RM<opc, (outs), (ins MEMrri:$addr, RC:$sx),
+  def rri : RM<opc, (outs), (ins (MEMrri $sz, $sy, $imm32):$addr, RC:$sx),
                !strconcat(opcStr, " $sx, $addr"),
                [(OpNode Ty:$sx, ADDRrri:$addr)]>;
   let cy = 0 in
-  def rii : RM<opc, (outs), (ins MEMrii:$addr, RC:$sx),
+  def rii : RM<opc, (outs), (ins (MEMrii $sz, $sy, $imm32):$addr, RC:$sx),
                !strconcat(opcStr, " $sx, $addr"),
                [(OpNode Ty:$sx, ADDRrii:$addr)]>;
   let cz = 0 in
-  def zri : RM<opc, (outs), (ins MEMzri:$addr, RC:$sx),
+  def zri : RM<opc, (outs), (ins (MEMzri $sz, $sy, $imm32):$addr, RC:$sx),
                !strconcat(opcStr, " $sx, $addr"),
                [(OpNode Ty:$sx, ADDRzri:$addr)]>;
   let cy = 0, cz = 0 in
-  def zii : RM<opc, (outs), (ins MEMzii:$addr, RC:$sx),
+  def zii : RM<opc, (outs), (ins (MEMzii $sz, $sy, $imm32):$addr, RC:$sx),
                !strconcat(opcStr, " $sx, $addr"),
                [(OpNode Ty:$sx, ADDRzii:$addr)]>;
 }
 
 // Section 8.2.7 - STS
 let DecoderMethod = "DecodeStoreI64" in
 defm ST : STOREm<"st", 0x11, I64, i64, store>;
 def : Pat<(store f64:$src, ADDRrri:$addr), (STrri MEMrri:$addr, $src)>;

 let cx = 1 in
 defm CVTQS : CVTm<"cvt.q.s", 0x2D, F128, f128, F32, f32, fpextend>;
 
 //-----------------------------------------------------------------------------
 // Section 8.8 - Branch instructions
 //-----------------------------------------------------------------------------
 
 // Section 8.8.1 - BC (Branch on Codition)
-defm BCFL : BCm<"b${cond}.l", "b.l", "baf.l", 0x19, I64, simm7>;
+defm BCFL : BCm<"b${cf}.l", "b.l", "baf.l", 0x19, I64, simm7>;
 
 // Indirect branch aliases
 def : Pat<(brind I64:$reg), (BCFLari_t $reg, 0)>;
 def : Pat<(brind tblockaddress:$imm), (BCFLazi_t 0, $imm)>;
 
 // Return instruction is a special case of jump.
 let Uses = [SX10], bpf = 3 /* TAKEN */, cf = 15 /* AT */, cy = 0, sy = 0,
     sz = 10 /* SX10 */, imm32 = 0, isReturn = 1, isTerminator = 1,
     isBarrier = 1, isCodeGenOnly = 1, hasSideEffects = 0 in
 def RET : CF<0x19, (outs), (ins), "b.l.t (, %s10)", [(retflag)]>;
 
 // Section 8.8.2 - BCS (Branch on Condition Single)
-defm BCFW : BCm<"b${cond}.w", "b.w", "baf.w", 0x1B, I32, simm7>;
+defm BCFW : BCm<"b${cf}.w", "b.w", "baf.w", 0x1B, I32, simm7>;
 
 // Section 8.8.3 - BCF (Branch on Condition Floating Point)
-defm BCFD : BCm<"b${cond}.d", "b.d", "baf.d", 0x1C, I64, simm7fp>;
+defm BCFD : BCm<"b${cf}.d", "b.d", "baf.d", 0x1C, I64, simm7fp>;
 let cx = 1 in
-defm BCFS : BCm<"b${cond}.s", "b.s", "baf.s", 0x1C, F32, simm7fp>;
+defm BCFS : BCm<"b${cf}.s", "b.s", "baf.s", 0x1C, F32, simm7fp>;
 
 // Section 8.8.4 - BCR (Branch on Condition Relative)
 let cx = 0, cx2 = 0 in
 defm BRCFL : BCRm<"br${cf}.l", "br.l", "braf.l", 0x18, I64, simm7, zero>;
 let cx = 1, cx2 = 0 in
 defm BRCFW : BCRm<"br${cf}.w", "br.w", "braf.w", 0x18, I32, simm7, zero>;
 let cx = 0, cx2 = 1 in
 defm BRCFD : BCRm<"br${cf}.d", "br.d", "braf.d", 0x18, I64, simm7fp, zerofp>;