[mlir][spirv] Add StreamingInterfaceINTEL to mlir SPIRVBase.td

[mmendell]

Summary

StreamingInterfaceINTEL has been recently added to the SPIR-V headers. Add it to SPRIVBase.td

[mmendell]

I am unable to commit this. Can someone please do so?

[antiagainst]

In D140476#4013091, @mmendell wrote:

I am unable to commit this. Can someone please do so?

Happy to. What's the git commit author and email to use?

[mmendell]

In D140476#4013468, @antiagainst wrote:

In D140476#4013091, @mmendell wrote:

I am unable to commit this. Can someone please do so?

Happy to. What's the git commit author and email to use?

Mark Mendell
[e-mail]

Should this be set somewhere in Phabricator?

[antiagainst]

Should this be set somewhere in Phabricator?

I'm not familiar with that actually. Normally arc patch would directly fill the proper name and email; but not this case. I'd assume it would help to fill out some name and email configurations in settings?

[mmendell]

I used the web interface only, since I couldn't install arc easily :-)

mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td

list<Availability> availability = [
     Capability<[SPIRV_C_FPGAKernelAttributesINTEL]>
   ];
 }
 def SPIRV_EM_SchedulerTargetFmaxMhzINTEL      : I32EnumAttrCase<"SchedulerTargetFmaxMhzINTEL", 5903> {
   list<Availability> availability = [
     Capability<[SPIRV_C_FPGAKernelAttributesINTEL]>
   ];
 }
+def SPIRV_EM_StreamingInterfaceINTEL          : I32EnumAttrCase<"StreamingInterfaceINTEL", 6154> {
+  list<Availability> availability = [
+    Capability<[SPIRV_C_FPGAKernelAttributesINTEL]>
+  ];
+}
 def SPIRV_EM_NamedBarrierCountINTEL           : I32EnumAttrCase<"NamedBarrierCountINTEL", 6417> {
   list<Availability> availability = [
     Capability<[SPIRV_C_VectorComputeINTEL]>
   ];
 }
 
 def SPIRV_ExecutionModeAttr :
     SPIRV_I32EnumAttr<"ExecutionMode", "valid SPIR-V ExecutionMode", "execution_mode", [
SPIRV_I32EnumAttr<"ExecutionMode", "valid SPIR-V ExecutionMode", "execution_mode", [
       SPIRV_EM_OutputTrianglesNV, SPIRV_EM_PixelInterlockOrderedEXT,
       SPIRV_EM_PixelInterlockUnorderedEXT, SPIRV_EM_SampleInterlockOrderedEXT,
       SPIRV_EM_SampleInterlockUnorderedEXT, SPIRV_EM_ShadingRateInterlockOrderedEXT,
       SPIRV_EM_ShadingRateInterlockUnorderedEXT, SPIRV_EM_SharedLocalMemorySizeINTEL,
       SPIRV_EM_RoundingModeRTPINTEL, SPIRV_EM_RoundingModeRTNINTEL,
       SPIRV_EM_FloatingPointModeALTINTEL, SPIRV_EM_FloatingPointModeIEEEINTEL,
       SPIRV_EM_MaxWorkgroupSizeINTEL, SPIRV_EM_MaxWorkDimINTEL,
       SPIRV_EM_NoGlobalOffsetINTEL, SPIRV_EM_NumSIMDWorkitemsINTEL,
-      SPIRV_EM_SchedulerTargetFmaxMhzINTEL, SPIRV_EM_NamedBarrierCountINTEL
+      SPIRV_EM_SchedulerTargetFmaxMhzINTEL, SPIRV_EM_StreamingInterfaceINTEL,
+      SPIRV_EM_NamedBarrierCountINTEL
     ]>;
 
 def SPIRV_EM_Vertex                 : I32EnumAttrCase<"Vertex", 0> {
   list<Availability> availability = [
     Capability<[SPIRV_C_Shader]>
   ];
 }
 def SPIRV_EM_TessellationControl    : I32EnumAttrCase<"TessellationControl", 1> {