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Differential D140469

[mlir][llvm] Cleanup LLVM IR control flow import test (NFC).
ClosedPublic

Authored by gysit on Dec 21 2022, 2:10 AM.

Details

Reviewers
ftynse
dcaballe
Dinistro
Commits
rG7c93fde8d274: [mlir][llvm] Cleanup LLVM IR control flow import test (NFC).
Summary

Use a FileCheck variable to match the switch op argument
instead of hardcoding the argument name.

Diff Detail

Event Timeline

gysit created this revision.Dec 21 2022, 2:10 AM
Herald added a reviewer: ftynse. · View Herald TranscriptDec 21 2022, 2:10 AM
Herald added a project: Restricted Project. · View Herald Transcript
Herald added subscribers: Moerafaat, zero9178, bzcheeseman and 22 others. · View Herald Transcript
gysit requested review of this revision.Dec 21 2022, 2:10 AM
Herald added a reviewer: dcaballe. · View Herald TranscriptDec 21 2022, 2:10 AM
Herald added a project: Restricted Project. · View Herald Transcript
Herald added subscribers: stephenneuendorffer, nicolasvasilache. · View Herald Transcript
gysit added a reviewer: Dinistro.Dec 21 2022, 2:10 AM
Dinistro accepted this revision.Dec 21 2022, 2:17 AM

LGTM!

This revision is now accepted and ready to land.Dec 21 2022, 2:17 AM
Harbormaster completed remote builds in B204343: Diff 484503.Dec 21 2022, 2:31 AM
ftynse accepted this revision.Dec 21 2022, 12:18 PM
Closed by commit rG7c93fde8d274: [mlir][llvm] Cleanup LLVM IR control flow import test (NFC). (authored by gysit). · Explain WhyDec 21 2022, 11:56 PM
This revision was automatically updated to reflect the committed changes.
gysit added a commit: rG7c93fde8d274: [mlir][llvm] Cleanup LLVM IR control flow import test (NFC)..

Revision Contents

PathSize
mlir/
test/
Target/
LLVMIR/
Import/
4 lines

Diff 484746

mlir/test/Target/LLVMIR/Import/control-flow.ll

Show First 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
; CHECK-SAME: %[[ARG1:[a-zA-Z0-9]+]] ; CHECK-SAME: %[[ARG1:[a-zA-Z0-9]+]]
define i32 @simple_switch(i32 %arg1) { define i32 @simple_switch(i32 %arg1) {
; CHECK: %[[VAL1:.+]] = llvm.add ; CHECK: %[[VAL1:.+]] = llvm.add
; CHECK: %[[VAL2:.+]] = llvm.sub ; CHECK: %[[VAL2:.+]] = llvm.sub
; CHECK: %[[VAL3:.+]] = llvm.mul ; CHECK: %[[VAL3:.+]] = llvm.mul
%1 = add i32 %arg1, 42 %1 = add i32 %arg1, 42
%2 = sub i32 %arg1, 42 %2 = sub i32 %arg1, 42
%3 = mul i32 %arg1, 42 %3 = mul i32 %arg1, 42
; CHECK: llvm.switch %arg0 : i32, ^[[BBD:.+]] [ ; CHECK: llvm.switch %[[ARG1]] : i32, ^[[BBD:.+]] [
; CHECK: 0: ^[[BB1:.+]], ; CHECK: 0: ^[[BB1:.+]],
; CHECK: 9: ^[[BB2:.+]] ; CHECK: 9: ^[[BB2:.+]]
; CHECK: ] ; CHECK: ]
switch i32 %arg1, label %bbd [ switch i32 %arg1, label %bbd [
i32 0, label %bb1 i32 0, label %bb1
i32 9, label %bb2 i32 9, label %bb2
] ]
bb1: bb1:
Show All 17 Lines
define i32 @switch_args(i32 %arg1) { define i32 @switch_args(i32 %arg1) {
entry: entry:
; CHECK: %[[VAL1:.+]] = llvm.add ; CHECK: %[[VAL1:.+]] = llvm.add
; CHECK: %[[VAL2:.+]] = llvm.sub ; CHECK: %[[VAL2:.+]] = llvm.sub
; CHECK: %[[VAL3:.+]] = llvm.mul ; CHECK: %[[VAL3:.+]] = llvm.mul
%0 = add i32 %arg1, 42 %0 = add i32 %arg1, 42
%1 = sub i32 %arg1, 42 %1 = sub i32 %arg1, 42
%2 = mul i32 %arg1, 42 %2 = mul i32 %arg1, 42
; CHECK: llvm.switch %arg0 : i32, ^[[BBD:.+]](%[[VAL3]] : i32) [ ; CHECK: llvm.switch %[[ARG1]] : i32, ^[[BBD:.+]](%[[VAL3]] : i32) [
; CHECK: 0: ^[[BB1:.+]](%[[VAL1]], %[[VAL2]] : i32, i32) ; CHECK: 0: ^[[BB1:.+]](%[[VAL1]], %[[VAL2]] : i32, i32)
; CHECK: ] ; CHECK: ]
switch i32 %arg1, label %bbd [ switch i32 %arg1, label %bbd [
i32 0, label %bb1 i32 0, label %bb1
] ]
bb1: bb1:
; CHECK: ^[[BB1]](%[[BA1:.+]]: i32, %[[BA2:.+]]: i32): ; CHECK: ^[[BB1]](%[[BA1:.+]]: i32, %[[BA2:.+]]: i32):
; CHECK: %[[VAL1:.*]] = llvm.add %[[BA1]], %[[BA2]] : i32 ; CHECK: %[[VAL1:.*]] = llvm.add %[[BA1]], %[[BA2]] : i32
Show All 11 Lines