[AMDGPU][GFX11] Correct tied src2 of v_fmac_f16_e64

[dp]

Summary

src2 was incorrectly defined as VSrc_f16 but it is tied to dst which is VGPR_32. As a result, disassembler failed to decode src2. See this bug for more information.

This change affects codegen because v_fmac_f16_e64 are now replaced by v_fma_f16 when src2 is not a VGPR. See https://github.com/llvm/llvm-project/blob/b5c809acd34c26666489679300eb0b8a8b824aeb/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp#L337

[Joe_Nash]

LGTM! Thanks for catching that.

llvm/lib/Target/AMDGPU/VOP2Instructions.td

let InsDPP = (ins Src0ModDPP:$src0_modifiers, Src0DPP:$src0,
                     Src1ModDPP:$src1_modifiers, Src1DPP:$src1,
                     getVregSrcForVT_t16<Src2VT>.ret:$src2, // stub argument
                     dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
                     bank_mask:$bank_mask, bound_ctrl:$bound_ctrl);
   let InsDPP8 = (ins Src0ModDPP:$src0_modifiers, Src0DPP:$src0,
                      Src1ModDPP:$src1_modifiers, Src1DPP:$src1,
                      getVregSrcForVT_t16<Src2VT>.ret:$src2, // stub argument
                      dpp8:$dpp8, FI:$fi);
+  let Src2Mod = FP32InputMods; // dummy unused modifiers
+  let Src2RC64 = VGPRSrc_32;   // stub argument
 }
 def VOP_MAC_F32 : VOP_MAC <f32>;
 let HasExtDPP = 0, HasExt32BitDPP = 0 in
 def VOP_MAC_LEGACY_F32 : VOP_MAC <f32>;
 let HasExtSDWA = 0, HasExt32BitDPP = 0, HasExt64BitDPP = 1 in
 def VOP_MAC_F64 : VOP_MAC <f64>;
 
 class VOP_DOT_ACC<ValueType vt0, ValueType vt1> : VOP_MAC<vt0, vt1> {

llvm/test/CodeGen/AMDGPU/fmul-2-combine-multi-use.ll

 
 ; GCN-LABEL: {{^}}multiple_use_fadd_fmac_f16:
 ; GCN-DAG: v_add_f16_e64 [[MUL2:v[0-9]+]], [[X:s[0-9]+]], s{{[0-9]+}}
 
 ; VI-FLUSH-DAG:     v_mac_f16_e64 [[MAD:v[0-9]+]], [[X]], 2.0
 ; VI-DENORM-DAG:    v_fma_f16 [[MAD:v[0-9]+]], [[X]], 2.0, v{{[0-9]+}}
 ; GFX10-FLUSH-DAG:  v_add_f16_e32 [[MAD:v[0-9]+]], s{{[0-9]+}}, [[MUL2]]
 ; GFX10-DENORM-DAG: v_fma_f16 [[MAD:v[0-9]+]], [[X]], 2.0, s{{[0-9]+}}
-; GFX11-DENORM-DAG: v_fmac_f16_e64 [[MAD:v[0-9]+]], [[X]], 2.0
+; GFX11-DENORM-DAG: v_fma_f16 [[MAD:v[0-9]+]], [[X]], 2.0, s{{[0-9]+}}
 
 ; GCN-DAG: buffer_store_{{short|b16}} [[MUL2]]
 ; GCN-DAG: buffer_store_{{short|b16}} [[MAD]]
 ; GCN: s_endpgm
 define amdgpu_kernel void @multiple_use_fadd_fmac_f16(ptr addrspace(1) %out, i16 zeroext %x.arg, i16 zeroext %y.arg) #0 {
   %x = bitcast i16 %x.arg to half
   %y = bitcast i16 %y.arg to half
   %out.gep.1 = getelementptr half, ptr addrspace(1) %out, i32 1

llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vop2.txt

 0x05,0x00,0x36,0xd5,0xf0,0xfa,0x00,0x48
 
 # GFX11: v_fmac_f16_e64 v5, -src_scc, |vcc_lo| mul:4 ; encoding: [0x05,0x02,0x36,0xd5,0xfd,0xd4,0x00,0x30]
 0x05,0x02,0x36,0xd5,0xfd,0xd4,0x00,0x30
 
 # GFX11: v_fmac_f16_e64 v255, -|0xfe0b|, -|vcc_hi| clamp div:2 ; encoding: [0xff,0x83,0x36,0xd5,0xff,0xd6,0x00,0x78,0x0b,0xfe,0x00,0x00]
 0xff,0x83,0x36,0xd5,0xff,0xd6,0x00,0x78,0x0b,0xfe,0x00,0x00
 
+# GFX11: v_fmac_f16_e64 v250, -|0xfe0b|, -|vcc_hi| clamp div:2 ; encoding: [0xfa,0x83,0x36,0xd5,0xff,0xd6,0x00,0x78,0x0b,0xfe,0x00,0x00]
+0xfa,0x83,0x36,0xd5,0xff,0xd6,0x00,0x78,0x0b,0xfe,0x00,0x00
+
+# GFX11: v_fmac_f16_e64 v255, v1, v2             ; encoding: [0xff,0x00,0x36,0xd5,0x01,0x05,0x02,0x00]
+0xff,0x00,0x36,0xd5,0x01,0x05,0x02,0x00
+
 # GFX11: v_fmac_f32_e64 v5, v1, v2               ; encoding: [0x05,0x00,0x2b,0xd5,0x01,0x05,0x02,0x00]
 0x05,0x00,0x2b,0xd5,0x01,0x05,0x02,0x00
 
 # GFX11: v_fmac_f32_e64 v5, v255, v255           ; encoding: [0x05,0x00,0x2b,0xd5,0xff,0xff,0x03,0x00]
 0x05,0x00,0x2b,0xd5,0xff,0xff,0x03,0x00
 
 # GFX11: v_fmac_f32_e64 v5, s1, s2               ; encoding: [0x05,0x00,0x2b,0xd5,0x01,0x04,0x00,0x00]
 0x05,0x00,0x2b,0xd5,0x01,0x04,0x00,0x00