[TTI][AArch64] getMemoryOpCost for ptr types

[SjoerdMeijer]

Summary

Opaque ptr types have a size in bits of 0. The legalised type is an i64 or vector of i64s, which do have size. Because of this difference in size, target hook getMemoryOpCost modelled stores of ptr types as extending/truncating load/stores. Now we just check for opaque ptr types and return the legalised cost. This makes stores of pointers cheaper, and as a result we now SLP vectorise the changed test case.

[dmgreen]

It could use the datalayout to get a better size, but this sounds OK to me. LGTM

[SjoerdMeijer]

Thanks Dave. I am going to look more into this area (for different cases), so will take that into account.

llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp

if (ST->isMisaligned128StoreSlow() && Opcode == Instruction::Store &&
     // practice on inlined block copy code.
     // We make such stores expensive so that we will only vectorize if there
     // are 6 other instructions getting vectorized.
     const int AmortizationCost = 6;
 
     return LT.first * 2 * AmortizationCost;
   }
 
+  // Opaque ptr or ptr vector types are i64s and can be lowered to STP/LDPs.
+  if (Ty->isPtrOrPtrVectorTy())
+    return LT.first;
+
   // Check truncating stores and extending loads.
   if (useNeonVector(Ty) &&
       Ty->getScalarSizeInBits() != LT.second.getScalarSizeInBits()) {
     // v4i8 types are lowered to scalar a load/store and sshll/xtn.
     if (VT == MVT::v4i8)
       return 2;
     // Otherwise we need to scalarize.
     return cast<FixedVectorType>(Ty)->getNumElements() * 2;

llvm/test/Analysis/CostModel/AArch64/store-ptr.ll

 ; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py
 ; RUN: opt < %s -passes="print<cost-model>" 2>&1 -disable-output -mtriple=aarch64-unknown -opaque-pointers | FileCheck %s
 ; RUN: opt < %s -passes="print<cost-model>" -cost-kind=code-size 2>&1 -disable-output -mtriple=aarch64-unknown -opaque-pointers | FileCheck %s --check-prefix=SIZE
 
 target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-v256:32:256-a0:0:32-n32-S32"
 define void @getMemoryOpCost() {
 ; CHECK-LABEL: 'getMemoryOpCost'
-; CHECK-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: store <2 x ptr> undef, ptr undef, align 4
-; CHECK-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: store <4 x ptr> undef, ptr undef, align 4
-; CHECK-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: store <8 x ptr> undef, ptr undef, align 4
+; CHECK-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: store <2 x ptr> undef, ptr undef, align 4
+; CHECK-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: store <4 x ptr> undef, ptr undef, align 4
+; CHECK-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: store <8 x ptr> undef, ptr undef, align 4
 ; CHECK-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret void
 ;
 ; SIZE-LABEL: 'getMemoryOpCost'
 ; SIZE-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: store <2 x ptr> undef, ptr undef, align 4
 ; SIZE-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: store <4 x ptr> undef, ptr undef, align 4
 ; SIZE-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: store <8 x ptr> undef, ptr undef, align 4
 ; SIZE-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: ret void
 ;
   store <2 x ptr> undef, ptr undef
   store <4 x ptr> undef, ptr undef
   store <8 x ptr> undef, ptr undef
 
   ret void
 }

llvm/test/Transforms/SLPVectorizer/AArch64/store-ptr.ll

 ; CHECK-NEXT:    ret void
 ; CHECK:       for.body:
 ; CHECK-NEXT:    [[INDVARS_IV:%.*]] = phi i64 [ 0, [[FOR_BODY_PREHEADER]] ], [ [[INDVARS_IV_NEXT:%.*]], [[FOR_BODY]] ]
 ; CHECK-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_NODE:%.*]], ptr [[Y:%.*]], i64 [[INDVARS_IV]]
 ; CHECK-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds [[STRUCT_NODE]], ptr [[X:%.*]], i64 [[INDVARS_IV]]
 ; CHECK-NEXT:    [[TMP0:%.*]] = load <2 x i64>, ptr [[ARRAYIDX]], align 8, !tbaa [[TBAA0:![0-9]+]]
 ; CHECK-NEXT:    store <2 x i64> [[TMP0]], ptr [[ARRAYIDX2]], align 8, !tbaa [[TBAA0]]
 ; CHECK-NEXT:    [[C:%.*]] = getelementptr inbounds [[STRUCT_NODE]], ptr [[Y]], i64 [[INDVARS_IV]], i32 2
-; CHECK-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[C]], align 8, !tbaa [[TBAA4:![0-9]+]]
 ; CHECK-NEXT:    [[C13:%.*]] = getelementptr inbounds [[STRUCT_NODE]], ptr [[X]], i64 [[INDVARS_IV]], i32 2
-; CHECK-NEXT:    store ptr [[TMP1]], ptr [[C13]], align 8, !tbaa [[TBAA4]]
-; CHECK-NEXT:    [[D:%.*]] = getelementptr inbounds [[STRUCT_NODE]], ptr [[Y]], i64 [[INDVARS_IV]], i32 3
-; CHECK-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[D]], align 8, !tbaa [[TBAA7:![0-9]+]]
-; CHECK-NEXT:    [[D18:%.*]] = getelementptr inbounds [[STRUCT_NODE]], ptr [[X]], i64 [[INDVARS_IV]], i32 3
-; CHECK-NEXT:    store ptr [[TMP2]], ptr [[D18]], align 8, !tbaa [[TBAA7]]
+; CHECK-NEXT:    [[TMP1:%.*]] = load <2 x ptr>, ptr [[C]], align 8, !tbaa [[TBAA4:![0-9]+]]
+; CHECK-NEXT:    store <2 x ptr> [[TMP1]], ptr [[C13]], align 8, !tbaa [[TBAA4]]
 ; CHECK-NEXT:    [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1
 ; CHECK-NEXT:    [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], [[WIDE_TRIP_COUNT]]
 ; CHECK-NEXT:    br i1 [[EXITCOND_NOT]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY]]
 ;
 entry:
   %cmp34 = icmp sgt i32 %n, 0
   br i1 %cmp34, label %for.body.preheader, label %for.cond.cleanup