sme dialect

[WanderAway]

Mistake with arcanist

mlir/include/mlir/Conversion/Passes.td

let options = [
     Option<"amx", "enable-amx",
            "bool", /*default=*/"false",
            "Enables the use of AMX dialect while lowering the vector "
      "dialect.">,
     Option<"armNeon", "enable-arm-neon",
            "bool", /*default=*/"false",
            "Enables the use of ArmNeon dialect while lowering the vector "
      "dialect.">,
+    Option<"armSME", "enable-arm-sme",
+           "bool", /*default=*/"false",
+           "Enables the use of ArmSME dialect while lowering the vector "
+       "dialect.">,
     Option<"armSVE", "enable-arm-sve",
            "bool", /*default=*/"false",
            "Enables the use of ArmSVE dialect while lowering the vector "
        "dialect.">,
     Option<"x86Vector", "enable-x86vector",
            "bool", /*default=*/"false",
            "Enables the use of X86Vector dialect while lowering the vector "
      "dialect.">

mlir/include/mlir/Conversion/VectorToLLVM/ConvertVectorToLLVM.h

 //===- ConvertVectorToLLVM.h - Utils to convert from the vector dialect ---===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 #ifndef MLIR_CONVERSION_VECTORTOLLVM_CONVERTVECTORTOLLVM_H_
struct LowerVectorToLLVMOptions {
   LowerVectorToLLVMOptions &enableIndexOptimizations(bool b = true) {
     force32BitVectorIndices = b;
     return *this;
   }
   LowerVectorToLLVMOptions &enableArmNeon(bool b = true) {
     armNeon = b;
     return *this;
   }
+  LowerVectorToLLVMOptions &enableArmSME(bool b = true) {
+    armSME = b;
+    return *this;
+  }
   LowerVectorToLLVMOptions &enableArmSVE(bool b = true) {
     armSVE = b;
     return *this;
   }
   LowerVectorToLLVMOptions &enableAMX(bool b = true) {
     amx = b;
     return *this;
   }
   LowerVectorToLLVMOptions &enableX86Vector(bool b = true) {
     x86Vector = b;
     return *this;
   }
 
   bool reassociateFPReductions{false};
   bool force32BitVectorIndices{true};
   bool armNeon{false};
+  bool armSME{false};
   bool armSVE{false};
   bool amx{false};
   bool x86Vector{false};
 };
 
 /// Collect a set of patterns to convert from Vector contractions to LLVM Matrix
 /// Intrinsics. To lower to assembly, the LLVM flag -lower-matrix-intrinsics
 /// will be needed when invoking LLVM.

mlir/include/mlir/Dialect/ArmSME/ArmSME.td

+//===-- ArmSME.td - ArmSME dialect operation definitions ---*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines the basic operations for the ArmSME dialect.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef ARMSME_OPS
+#define ARMSME_OPS
+
+include "mlir/Interfaces/SideEffectInterfaces.td"
+include "mlir/Dialect/LLVMIR/LLVMOpBase.td"
+
+//===----------------------------------------------------------------------===//
+// ArmSME dialect definition
+//===----------------------------------------------------------------------===//
+
+def ArmSME_Dialect : Dialect {
+  let name = "arm_sme";
+  let cppNamespace = "::mlir::arm_sme";
+  let summary = "Basic dialect to target Arm SME architectures";
+  let description = [{
+    This dialect contains the definitions necessary to target specific Arm SME
+    scalable vector operations.
+
+    Source:
+    https://developer.arm.com/documentation/ddi0616/aa
+  }];
+  let dependentDialects = ["arm_sve::ArmSVEDialect"];
+}
+
+//===----------------------------------------------------------------------===//
+// ArmSME Tile enum definitions
+//===----------------------------------------------------------------------===//
+
+def ZA0D : I32EnumAttrCase<"za0d", 1>;
+def ZA1D : I32EnumAttrCase<"za1d", 2>;
+def ZA2D : I32EnumAttrCase<"za2d", 4>;
+def ZA3D : I32EnumAttrCase<"za3d", 8>;
+def ZA4D : I32EnumAttrCase<"za4d", 16>;
+def ZA5D : I32EnumAttrCase<"za5d", 32>;
+def ZA6D : I32EnumAttrCase<"za6d", 64>;
+def ZA7D : I32EnumAttrCase<"za7d", 128>;
+def ZA0S : I32EnumAttrCase<"za0s", 17>;  // = ZA0D | ZA4D
+def ZA1S : I32EnumAttrCase<"za1s", 34>;  // = ZA1D | ZA5D
+def ZA2S : I32EnumAttrCase<"za2s", 68>;  // = ZA2D | ZA6D
+def ZA3S : I32EnumAttrCase<"za3s", 136>; // = ZA3D | ZA7D
+
+def ArmSME_TileAttr : I32EnumAttr<"TileEnum",
+                                  "Enum representation the SME matrix tiles",
+                                  [ZA0D, ZA1D, ZA2D, ZA3D, ZA4D, ZA5D, ZA6D,
+                                   ZA7D, ZA0S, ZA1S, ZA2S, ZA3S]> {
+  let cppNamespace = "::mlir::arm_sme";
+}
+
+//===----------------------------------------------------------------------===//
+// ArmSME op definitions
+//===----------------------------------------------------------------------===//
+
+class ArmSME_Op<string mnemonic, list<Trait> traits = []> :
+  Op<ArmSME_Dialect, mnemonic, traits> {}
+
+def Predicate : ScalableVectorOfLengthAndType<[16, 8, 4, 2], [I1]>;
+def SMEVector : ScalableVectorOfLengthAndType<
+                    [16, 8, 4, 2], [SI8, SI16, UI8, UI16, BF16, F16, F32, F64]>;
+def TileList : TypedArrayAttrBase<ArmSME_TileAttr, "list of SME matrix tiles">;
+
+class MOPOpBase<string mnemonic, bit accumulate>
+    : ArmSME_Op<mnemonic,
+                [AllShapesMatch<["lhs", "lhsPred", "rhs", "rhsPred"]>]> {
+  let arguments = (ins
+          ArmSME_TileAttr:$tile,
+          Predicate:$lhsPred,
+          Predicate:$rhsPred,
+          SMEVector:$lhs,
+          SMEVector:$rhs
+  );
+  let extraClassDeclaration = [{
+    bool isAccumulate() { return }] # accumulate # [{;
+}
+    bool isSubtract() { return }] # !not(accumulate) # [{; }
+    bool isWidening() {
+      auto elTy = this->getLhs().getType().cast<VectorType>().getElementType();
+      if (elTy.isF32() || elTy.isF64())
+        return false;
+      else
+        return true;
+    }
+  }];
+  let assemblyFormat =[{ $tile`,` $lhsPred`,` $rhsPred`,` $lhs`,` $rhs attr-dict
+                         `:` type($lhsPred)`,` type($rhsPred)`,` type($lhs)`,` type($rhs) }];
+  let hasVerifier = 1;
+}
+
+def MopaOp : MOPOpBase<"mopa", /*accumulate=*/true> {
+  let summary = "Vector-vector outer product and accumulate op";
+  let description = [{
+    MOPA: Outer product product accumulate.
+
+    This function maps to the *MOPA instructions, it takes scalable vector
+    operands which will be used to compute the outer product matrix. Two
+    masking predicate operands for each of the floating point operands will also
+    be provided, such that elements marked inactive by the predicate will not
+    update the corresponding row/column in the result matrix tile, specified by
+    the attribute.
+
+    Theere are two variations of MOPA instructions - widening and non-widening.
+
+    Non-widening MOPAs will take a 1D vector of f32 or f64 as input and
+    accumulate into 32b and 64b tiles respectively (za*s and za*d).
+
+    Widening MOPAs will pack two f16/bf16 or four (signed or unsigned) i8
+    elements into a single 32b lane of the vector and accumulate into 32b tiles
+    (za*s); Or it will pack four (signed or unsigned) i16 elements into a 64b
+    lane and accumulate into 64b tiles (za*d). Hence widening MOPAs will take
+    2D scalable vectors as input, i.e. `<[4x2]xf16>, <[2x4]xsi16>, <[4x4]xsi8>`
+
+    Example: Assume `vscale == 2`, `%lhs = %rhs = <1, 2, 3, 4> : <[2]xfp64>`,
+    `%lhsPred = %rhsPred = <true, true, false, true>`, then:
+    ```
+    arm_sme.zero za0d
+    arm_sme.fmopa za0d, %lhsPred, %rhsPred, %lhs, %rhs
+                  : vector<[2]xi1>, vector<[2]xf64>
+    ```
+
+    Would result in za0d containing:
+    ```
+    1  2  0  4
+    2  4  0  8
+    0  0  0  0
+    4  8  0 16
+    ```
+  }];
+}
+
+def MopsOp : MOPOpBase<"mops", /*accumulate=*/false> {
+  let summary = "Vector-vector outer product and subtract op";
+  let description = [{
+    FMOPA: Outer product product accumulate.
+
+    This function maps to the *MOPS instructions, it functions similarily to
+    the *MOPA instructions, but differs in that it subtracts the outer product
+    computed from the input vectors from the existing values within the tile
+    provided.
+  }];
+}
+
+def ZeroOp : ArmSME_Op<"zero"> {
+  let summary = "Zeroes a list of SME matrix tiles";
+  let description = [{
+    ZERO: Sets the contents of specified matrix tiles to zero";
+
+    Source:
+    https: // developer.arm.com/documentation/ddi0616/aa
+  }];
+  let arguments = (ins TileList:$tiles);
+  let assemblyFormat = "custom<TileEnumList>($tiles) attr-dict";
+}
+
+//===----------------------------------------------------------------------===//
+// ArmSME Intrinsic op definitions
+//===----------------------------------------------------------------------===//
+
+class ArmSME_IntrOverloadedOp<string mnemonic, list<int> overloadOperands = []>
+    : LLVM_IntrOpBase<
+          /*Dialect dialect=*/ArmSME_Dialect,
+          /*string opName=*/"intr." #mnemonic,
+          /*string enumName=*/"aarch64_sme_" #!subst(".", "_", mnemonic),
+          /*list<int> overloadedResults=*/[],
+          /*list<int> overloadedOperands=*/overloadOperands,
+          /*list<Trait> traits=*/[],
+          /*int numResults=*/0>;
+
+def ZeroIntrOp : ArmSME_IntrOverloadedOp<"zero">,
+                 Arguments<(ins Arg<I32, "Tile register ID">)>;
+
+class ArmSME_IntrMopOverloadedOp<string mnemonic>
+    : ArmSME_IntrOverloadedOp<mnemonic, [4]>,
+      Arguments<(ins Arg<I32, "Tile register ID">,
+                 Arg<Predicate, "LHS predicate">,
+                 Arg<Predicate, "RHS predicate">,
+                 Arg<AnyScalableVector, "LHS vector operand">,
+                 Arg<AnyScalableVector, "RHS vector operand">)>;
+
+def FmopaIntrOp : ArmSME_IntrMopOverloadedOp<"mopa">;
+def FmopsIntrOp : ArmSME_IntrMopOverloadedOp<"mops">;
+
+def FmopaWidenIntrOp : ArmSME_IntrMopOverloadedOp<"mopa_wide">;
+def FmopsWidenIntrOp : ArmSME_IntrMopOverloadedOp<"mops_wide">;
+
+def SmopaIntrOp : ArmSME_IntrMopOverloadedOp<"smopa_wide">;
+def SmopsIntrOp : ArmSME_IntrMopOverloadedOp<"smops_wide">;
+def UmopaIntrOp : ArmSME_IntrMopOverloadedOp<"umopa_wide">;
+def UmopsIntrOp : ArmSME_IntrMopOverloadedOp<"umops_wide">;
+def SUmopaIntrOp : ArmSME_IntrMopOverloadedOp<"sumopa_wide">;
+def SUmopsIntrOp : ArmSME_IntrMopOverloadedOp<"sumops_wide">;
+def USmopaIntrOp : ArmSME_IntrMopOverloadedOp<"usmopa_wide">;
+def USmopsIntrOp : ArmSME_IntrMopOverloadedOp<"usmops_wide">;
+
+class ArmSME_IntrLoadStoreOverloadedOp<string mnemonic>
+    : ArmSME_IntrOverloadedOp<mnemonic>,
+      Arguments<(ins Arg<Predicate, "Vector predicate">,
+                 Arg<LLVM_AnyPointer, "The location to store to", [MemWrite]>,
+                 Arg<I32, "Tile register ID">, Arg<I32, "Vector number">)>;
+
+// Loads
+def LoadHorizontalBytesIntrOp : ArmSME_IntrLoadStoreOverloadedOp<"ld1b_horiz">;
+def LoadHorizontalHalfsIntrOp : ArmSME_IntrLoadStoreOverloadedOp<"ld1h_horiz">;
+def LoadHorizontalWordsIntrOp : ArmSME_IntrLoadStoreOverloadedOp<"ld1w_horiz">;
+def LoadHorizontalDoublesIntrOp : ArmSME_IntrLoadStoreOverloadedOp<"ld1d_horiz">;
+def LoadHorizontalQuadsIntrOp : ArmSME_IntrLoadStoreOverloadedOp<"ld1q_horiz">;
+
+// Stores
+def StoreVerticalBytesIntrOp : ArmSME_IntrLoadStoreOverloadedOp<"st1b_vert">;
+def StoreVerticalHalfsIntrOp : ArmSME_IntrLoadStoreOverloadedOp<"st1h_vert">;
+def StoreVerticalWordsIntrOp : ArmSME_IntrLoadStoreOverloadedOp<"st1w_vert">;
+def StoreVerticalDoublesIntrOp : ArmSME_IntrLoadStoreOverloadedOp<"st1d_vert">;
+def StoreVerticalQuadsIntrOp : ArmSME_IntrLoadStoreOverloadedOp<"st1q_vert">;
+
+#endif // ARMSME_OPS

mlir/include/mlir/Dialect/ArmSME/ArmSMEDialect.h

+//===- ArmSMEDialect.h - MLIR Dialect for Arm SME ---------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file declares the Target dialect for ArmSME in MLIR.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef MLIR_DIALECT_ARMSME_ARMSMEDIALECT_H
+#define MLIR_DIALECT_ARMSME_ARMSMEDIALECT_H
+
+#include "mlir/IR/BuiltinTypes.h"
+#include "mlir/IR/Dialect.h"
+#include "mlir/IR/OpDefinition.h"
+#include "mlir/Interfaces/SideEffectInterfaces.h"
+
+#include "mlir/Dialect/ArmSME/ArmSMEDialect.h.inc"
+#include "mlir/Dialect/ArmSME/ArmSMEEnums.h.inc"
+
+#define GET_OP_CLASSES
+#include "mlir/Dialect/ArmSME/ArmSME.h.inc"
+
+#endif // MLIR_DIALECT_ARMSME_ARMSMEDIALECT_H

mlir/include/mlir/Dialect/ArmSME/CMakeLists.txt

+add_mlir_dialect(ArmSME arm_sme ArmSME)
+add_mlir_doc(ArmSME ArmSME Dialects/ -gen-dialect-doc -dialect=arm_sme)
+
+set(LLVM_TARGET_DEFINITIONS ArmSME.td)
+mlir_tablegen(ArmSMEEnums.h.inc -gen-enum-decls)
+mlir_tablegen(ArmSMEEnums.cpp.inc -gen-enum-defs)
+mlir_tablegen(ArmSMEConversions.inc -gen-llvmir-conversions)
+add_public_tablegen_target(MLIRArmSMEConversionsIncGen)

mlir/include/mlir/Dialect/ArmSME/Transforms.h

+//===- Transforms.h - ArmSME Dialect Transformation Entrypoints -*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef MLIR_DIALECT_ARMSME_TRANSFORMS_H
+#define MLIR_DIALECT_ARMSME_TRANSFORMS_H
+
+namespace mlir {
+
+class LLVMConversionTarget;
+class LLVMTypeConverter;
+class RewritePatternSet;
+
+/// Collect a set of patterns to lower ArmSME ops to ops that map to LLVM
+/// intrinsics.
+void populateArmSMELegalizeForLLVMExportPatterns(LLVMTypeConverter &converter,
+                                                 RewritePatternSet &patterns);
+
+/// Configure the target to support lowering ArmSME ops to ops that map to LLVM
+/// intrinsics.
+void configureArmSMELegalizeForExportTarget(LLVMConversionTarget &target);
+
+} // namespace mlir
+
+#endif // MLIR_DIALECT_ARMSME_TRANSFORMS_H

mlir/include/mlir/Dialect/CMakeLists.txt

 add_subdirectory(AMDGPU)
 add_subdirectory(AMX)
 add_subdirectory(Affine)
 add_subdirectory(Arith)
 add_subdirectory(ArmNeon)
+add_subdirectory(ArmSME)
 add_subdirectory(ArmSVE)
 add_subdirectory(Async)
 add_subdirectory(Bufferization)
 add_subdirectory(Complex)
 add_subdirectory(ControlFlow)
 add_subdirectory(DLTI)
 add_subdirectory(EmitC)
 add_subdirectory(Func)

mlir/include/mlir/InitAllDialects.h

 //===- InitAllDialects.h - MLIR Dialects Registration -----------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file defines a helper to trigger the registration of all dialects and
 // passes to the system.
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef MLIR_INITALLDIALECTS_H_
 #define MLIR_INITALLDIALECTS_H_
 
 #include "mlir/Dialect/AMDGPU/AMDGPUDialect.h"
 #include "mlir/Dialect/AMX/AMXDialect.h"
 #include "mlir/Dialect/Affine/IR/AffineOps.h"
 #include "mlir/Dialect/Affine/TransformOps/AffineTransformOps.h"
 #include "mlir/Dialect/Arith/IR/Arith.h"
 #include "mlir/Dialect/Arith/Transforms/BufferizableOpInterfaceImpl.h"
 #include "mlir/Dialect/ArmNeon/ArmNeonDialect.h"
+#include "mlir/Dialect/ArmSME/ArmSMEDialect.h"
 #include "mlir/Dialect/ArmSVE/ArmSVEDialect.h"
 #include "mlir/Dialect/Async/IR/Async.h"
 #include "mlir/Dialect/Bufferization/IR/Bufferization.h"
 #include "mlir/Dialect/Bufferization/TransformOps/BufferizationTransformOps.h"
 #include "mlir/Dialect/Bufferization/Transforms/FuncBufferizableOpInterfaceImpl.h"
 #include "mlir/Dialect/Complex/IR/Complex.h"
 #include "mlir/Dialect/ControlFlow/IR/ControlFlow.h"
 #include "mlir/Dialect/DLTI/DLTI.h"
registry.insert<acc::OpenACCDialect,
                   ml_program::MLProgramDialect,
                   nvgpu::NVGPUDialect,
                   scf::SCFDialect,
                   omp::OpenMPDialect,
                   pdl::PDLDialect,
                   pdl_interp::PDLInterpDialect,
                   quant::QuantizationDialect,
                   spirv::SPIRVDialect,
+                  arm_sme::ArmSMEDialect,
                   arm_sve::ArmSVEDialect,
                   vector::VectorDialect,
                   NVVM::NVVMDialect,
                   ROCDL::ROCDLDialect,
                   shape::ShapeDialect,
                   sparse_tensor::SparseTensorDialect,
                   tensor::TensorDialect,
                   transform::TransformDialect,

mlir/include/mlir/Target/LLVMIR/Dialect/All.h

 //===- All.h - MLIR To LLVM IR Translation Registration ---------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file defines a helper to register the translations of all suitable
 // dialects to LLVM IR.
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef MLIR_TARGET_LLVMIR_DIALECT_ALL_H
 #define MLIR_TARGET_LLVMIR_DIALECT_ALL_H
 
 #include "mlir/Target/LLVMIR/Dialect/AMX/AMXToLLVMIRTranslation.h"
 #include "mlir/Target/LLVMIR/Dialect/ArmNeon/ArmNeonToLLVMIRTranslation.h"
+#include "mlir/Target/LLVMIR/Dialect/ArmSME/ArmSMEToLLVMIRTranslation.h"
 #include "mlir/Target/LLVMIR/Dialect/ArmSVE/ArmSVEToLLVMIRTranslation.h"
 #include "mlir/Target/LLVMIR/Dialect/LLVMIR/LLVMToLLVMIRTranslation.h"
 #include "mlir/Target/LLVMIR/Dialect/NVVM/NVVMToLLVMIRTranslation.h"
 #include "mlir/Target/LLVMIR/Dialect/OpenACC/OpenACCToLLVMIRTranslation.h"
 #include "mlir/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.h"
 #include "mlir/Target/LLVMIR/Dialect/ROCDL/ROCDLToLLVMIRTranslation.h"
 #include "mlir/Target/LLVMIR/Dialect/X86Vector/X86VectorToLLVMIRTranslation.h"
 
 namespace mlir {
 class DialectRegistry;
 
 /// Registers all dialects that can be translated to LLVM IR and the
 /// corresponding translation interfaces.
 static inline void registerAllToLLVMIRTranslations(DialectRegistry &registry) {
   registerArmNeonDialectTranslation(registry);
   registerAMXDialectTranslation(registry);
+  registerArmSMEDialectTranslation(registry);
   registerArmSVEDialectTranslation(registry);
   registerLLVMDialectTranslation(registry);
   registerNVVMDialectTranslation(registry);
   registerOpenACCDialectTranslation(registry);
   registerOpenMPDialectTranslation(registry);
   registerROCDLDialectTranslation(registry);
   registerX86VectorDialectTranslation(registry);
 }
 } // namespace mlir
 
 #endif // MLIR_TARGET_LLVMIR_DIALECT_ALL_H

mlir/include/mlir/Target/LLVMIR/Dialect/ArmSME/ArmSMEToLLVMIRTranslation.h

+//=======- ArmSMEToLLVMIRTranslation.h - ArmSME to LLVM IR --*- C++ -*-=======//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This provides registration calls for ArmSME dialect to LLVM IR translation.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef MLIR_TARGET_LLVMIR_DIALECT_ARMSME_ARMSMETOLLVMIRTRANSLATION_H
+#define MLIR_TARGET_LLVMIR_DIALECT_ARMSME_ARMSMETOLLVMIRTRANSLATION_H
+
+namespace mlir {
+
+class DialectRegistry;
+class MLIRContext;
+
+/// Register the ArmSME dialect and the translation from it to the LLVM IR in
+/// the given registry;
+void registerArmSMEDialectTranslation(DialectRegistry &registry);
+
+/// Register the ArmSME dialect and the translation from it in the registry
+/// associated with the given context.
+void registerArmSMEDialectTranslation(MLIRContext &context);
+
+} // namespace mlir
+
+#endif // MLIR_TARGET_LLVMIR_DIALECT_ARMSME_ARMSMETOLLVMIRTRANSLATION_H

mlir/lib/Conversion/VectorToLLVM/CMakeLists.txt

add_mlir_conversion_library(MLIRVectorToLLVM
   intrinsics_gen
 
   LINK_COMPONENTS
   Core
 
   LINK_LIBS PUBLIC
   MLIRArithDialect
   MLIRArmNeonDialect
+  MLIRArmSMEDialect
+  MLIRArmSMETransforms
   MLIRArmSVEDialect
   MLIRArmSVETransforms
   MLIRAMXDialect
   MLIRAMXTransforms
   MLIRLLVMCommonConversion
   MLIRLLVMDialect
   MLIRMemRefDialect
   MLIRTargetLLVMIRExport
   MLIRTransforms
   MLIRVectorDialect
   MLIRVectorTransforms
   MLIRX86VectorDialect
   MLIRX86VectorTransforms
   )

mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVMPass.cpp

 //===- VectorToLLVM.cpp - Conversion from Vector to the LLVM dialect ------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #include "mlir/Conversion/VectorToLLVM/ConvertVectorToLLVM.h"
 
 #include "mlir/Conversion/LLVMCommon/ConversionTarget.h"
 #include "mlir/Conversion/LLVMCommon/TypeConverter.h"
 #include "mlir/Dialect/AMX/AMXDialect.h"
 #include "mlir/Dialect/AMX/Transforms.h"
 #include "mlir/Dialect/Arith/IR/Arith.h"
 #include "mlir/Dialect/ArmNeon/ArmNeonDialect.h"
+#include "mlir/Dialect/ArmSME/ArmSMEDialect.h"
+#include "mlir/Dialect/ArmSME/Transforms.h"
 #include "mlir/Dialect/ArmSVE/ArmSVEDialect.h"
 #include "mlir/Dialect/ArmSVE/Transforms.h"
 #include "mlir/Dialect/Func/IR/FuncOps.h"
 #include "mlir/Dialect/LLVMIR/LLVMDialect.h"
 #include "mlir/Dialect/MemRef/IR/MemRef.h"
 #include "mlir/Dialect/Vector/Transforms/VectorRewritePatterns.h"
 #include "mlir/Dialect/X86Vector/Transforms.h"
 #include "mlir/Dialect/X86Vector/X86VectorDialect.h"

 
 namespace {
 struct LowerVectorToLLVMPass
     : public impl::ConvertVectorToLLVMBase<LowerVectorToLLVMPass> {
   LowerVectorToLLVMPass(const LowerVectorToLLVMOptions &options) {
     this->reassociateFPReductions = options.reassociateFPReductions;
     this->force32BitVectorIndices = options.force32BitVectorIndices;
     this->armNeon = options.armNeon;
+    this->armSME = options.armSME;
     this->armSVE = options.armSVE;
     this->amx = options.amx;
     this->x86Vector = options.x86Vector;
   }
   // Override explicitly to allow conditional dialect dependence.
   void getDependentDialects(DialectRegistry &registry) const override {
     registry.insert<LLVM::LLVMDialect>();
     registry.insert<arith::ArithDialect>();
     registry.insert<memref::MemRefDialect>();
     if (armNeon)
       registry.insert<arm_neon::ArmNeonDialect>();
-    if (armSVE)
+    if (armSME) {
+      registry.insert<arm_sme::ArmSMEDialect>();
+      registry.insert<arm_sve::ArmSVEDialect>();
+    } else if (armSVE)
       registry.insert<arm_sve::ArmSVEDialect>();
     if (amx)
       registry.insert<amx::AMXDialect>();
     if (x86Vector)
       registry.insert<x86vector::X86VectorDialect>();
   }
   void runOnOperation() override;
 };
void LowerVectorToLLVMPass::runOnOperation() {
   target.addLegalDialect<memref::MemRefDialect>();
   target.addLegalOp<UnrealizedConversionCastOp>();
   if (armNeon) {
     // TODO: we may or may not want to include in-dialect lowering to
     // LLVM-compatible operations here. So far, all operations in the dialect
     // can be translated to LLVM IR so there is no conversion necessary.
     target.addLegalDialect<arm_neon::ArmNeonDialect>();
   }
-  if (armSVE) {
+  if (armSME) {
+    configureArmSMELegalizeForExportTarget(target);
+    populateArmSMELegalizeForLLVMExportPatterns(converter, patterns);
+    configureArmSVELegalizeForExportTarget(target);
+    populateArmSVELegalizeForLLVMExportPatterns(converter, patterns);
+  } else if (armSVE) {
     configureArmSVELegalizeForExportTarget(target);
     populateArmSVELegalizeForLLVMExportPatterns(converter, patterns);
   }
   if (amx) {
     configureAMXLegalizeForExportTarget(target);
     populateAMXLegalizeForLLVMExportPatterns(converter, patterns);
   }
   if (x86Vector) {

mlir/lib/Dialect/ArmSME/CMakeLists.txt

+add_subdirectory(IR)
+add_subdirectory(Transforms)

mlir/lib/Dialect/ArmSME/IR/ArmSMEDialect.cpp

+//===- ArmSMEDialect.cpp - MLIR ArmSME dialect implementation -------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements the ArmSME dialect and its operations.
+//
+//===----------------------------------------------------------------------===//
+
+#include "mlir/Dialect/ArmSME/ArmSMEDialect.h"
+#include "mlir/Dialect/ArmSVE/ArmSVEDialect.h"
+#include "mlir/Dialect/LLVMIR/LLVMTypes.h"
+#include "mlir/IR/Builders.h"
+#include "mlir/IR/DialectImplementation.h"
+#include "mlir/IR/OpImplementation.h"
+#include "mlir/IR/TypeUtilities.h"
+#include "llvm/ADT/STLExtras.h"
+#include "llvm/ADT/TypeSwitch.h"
+
+using namespace mlir;
+using namespace mlir::arm_sme;
+
+//===----------------------------------------------------------------------===//
+// Custom printer/parser for list of SME Tile enums
+//===----------------------------------------------------------------------===//
+
+namespace {
+
+void printTileEnumList(OpAsmPrinter &printer, Operation *op, ArrayAttr tiles) {
+  (void)op;
+  llvm::interleaveComma(tiles, printer, [&](Attribute elem) {
+    auto tile = elem.cast<TileEnumAttr>().getValue();
+    printer << stringifyTileEnum(tile);
+  });
+}
+
+ParseResult parseTileEnumList(OpAsmParser &parser, ArrayAttr &tiles) {
+  SmallVector<Attribute> tileStorage;
+  auto parseTileEnumAttr = [&]() -> ParseResult {
+    StringRef keyword;
+    if (parser.parseKeyword(&keyword))
+      return failure();
+    Optional<TileEnum> maybeTile = symbolizeTileEnum(keyword);
+    if (!maybeTile)
+      return parser.emitError(parser.getCurrentLocation(),
+                              "invalid SME tile name");
+    auto tileAttr = TileEnumAttr::get(parser.getContext(), *maybeTile);
+    tileStorage.push_back(tileAttr);
+    return success();
+  };
+  auto loc = parser.getCurrentLocation();
+  if (parser.parseCommaSeparatedList(parseTileEnumAttr))
+    return parser.emitError(loc, "expected list of SME tiles");
+  tiles = ArrayAttr::get(parser.getContext(), tileStorage);
+  return success();
+}
+
+} // namespace
+
+//===----------------------------------------------------------------------===//
+// Tablegen Definitions
+//===----------------------------------------------------------------------===//
+
+#include "mlir/Dialect/ArmSME/ArmSMEDialect.cpp.inc"
+#include "mlir/Dialect/ArmSME/ArmSMEEnums.cpp.inc"
+
+#define GET_OP_CLASSES
+#include "mlir/Dialect/ArmSME/ArmSME.cpp.inc"
+
+#define GET_TYPEDEF_CLASSES
+#include "mlir/Dialect/ArmSME/ArmSMETypes.cpp.inc"
+
+void ArmSMEDialect::initialize() {
+  addOperations<
+#define GET_OP_LIST
+#include "mlir/Dialect/ArmSME/ArmSME.cpp.inc"
+      >();
+}
+
+//===----------------------------------------------------------------------===//
+// Custom Verifier
+//===----------------------------------------------------------------------===//
+
+/// Additional verification of MOP ops
+static LogicalResult verifyMOP(TileEnum tile, Type lhsTy, Type rhsTy,
+                               bool isWidening, Operation *op) {
+  auto lhsVecTy = lhsTy.cast<VectorType>();
+  auto rhsVecTy = lhsTy.cast<VectorType>();
+  if (lhsVecTy.getNumScalableDims() != lhsVecTy.getRank() ||
+      rhsVecTy.getNumScalableDims() != rhsVecTy.getRank())
+    return op->emitOpError("expecting all dimensions to be scalable");
+  Type lhsElTy = lhsVecTy.getElementType();
+  Type rhsElTy = rhsVecTy.getElementType();
+
+  const llvm::DenseSet<TileEnum> b32Tiles(
+      {TileEnum::za0s, TileEnum::za1s, TileEnum::za2s, TileEnum::za3s});
+  const llvm::DenseSet<TileEnum> b64Tiles(
+      {TileEnum::za0d, TileEnum::za1d, TileEnum::za2d, TileEnum::za3d,
+       TileEnum::za4d, TileEnum::za5d, TileEnum::za6d, TileEnum::za7d});
+  // Verify element type width
+  unsigned elWidth = lhsElTy.getIntOrFloatBitWidth();
+  if (elWidth != rhsElTy.getIntOrFloatBitWidth())
+    return op->emitOpError("invalid vector element type");
+
+  // Verify valid vector unit length:
+  constexpr unsigned sveUnitVecWidth = 128;
+  if (elWidth * lhsVecTy.getNumElements() != sveUnitVecWidth)
+    return op->emitOpError(
+        "expected operand vector length to be multiples of 128 bits");
+
+  if (isWidening) {
+    // Check element types - integer types can be either signed or unsigned for
+    // both operands, otherwise the types must match.
+    if (lhsVecTy.getRank() != 2)
+      return op->emitOpError(
+          "expecting widening MOP ops to have 2D vector operands");
+    auto lhsShape = lhsVecTy.getShape();
+    if (lhsElTy.isBF16() || lhsElTy.isF16()) {
+      // widening fmop*/bfmop*
+      if (!b32Tiles.contains(tile))
+        return op->emitOpError(
+            "expecting 16b float types to accumulate into 32b tiles");
+      if (rhsElTy != lhsElTy)
+        return op->emitOpError("mismatching lhs and rhs vector element types");
+      if (lhsShape[0] != 4)
+        return op->emitOpError("invalid vector shape for widening MOP");
+    } else if (lhsElTy.isInteger(8)) {
+      // 8->32-bit smop*/umop*/sumop*/usmop*
+      if (!b32Tiles.contains(tile))
+        return op->emitOpError(
+            "expecting 8b int types to accumulate into 32b tiles");
+      if (!rhsElTy.isInteger(8))
+        return op->emitOpError(
+            "expecting lhs and rhs element types to be of same integer width");
+      if (lhsShape[0] != 4)
+        return op->emitOpError("invalid vector shape for widening MOP");
+    } else if (lhsElTy.isInteger(16)) {
+      // 16->64-bit smop*/umop*/sumop*/usmop*
+      if (!b64Tiles.contains(tile))
+        return op->emitOpError(
+            "expecting 16b int types to accumulate into 64b tiles");
+      if (!rhsElTy.isInteger(16))
+        return op->emitOpError(
+            "expecting lhs and rhs element types to be of same integer width");
+      if (lhsShape[0] != 2)
+        return op->emitOpError("invalid vector shape for widening MOP");
+    }
+    return success();
+  }
+
+  // non-widening fmop*
+  if (lhsVecTy != rhsVecTy)
+    return op->emitOpError("expecting lhs and rhs operands to have the same "
+                           "type for non-widening MOP");
+  if (lhsVecTy.getRank() != 1)
+    return op->emitOpError("expecting 1D vector operands for non-widening MOP");
+  if (lhsVecTy.isF32() && !b32Tiles.contains(tile))
+    return op->emitOpError("expecting f32 MOP to accumulate into 32b tiles");
+  if (lhsVecTy.isF64() && !b64Tiles.contains(tile))
+    return op->emitOpError("expecting f64 MOP to accumulate into 64b tiles");
+
+  return success();
+}
+
+LogicalResult MopaOp::verify() {
+  return verifyMOP(getTile(), getLhs().getType(), getRhs().getType(),
+                   isWidening(), getOperation());
+}
+
+LogicalResult MopsOp::verify() {
+  return verifyMOP(getTile(), getLhs().getType(), getRhs().getType(),
+                   isWidening(), getOperation());
+}

mlir/lib/Dialect/ArmSME/IR/CMakeLists.txt

+add_mlir_dialect_library(MLIRArmSMEDialect
+  ArmSMEDialect.cpp
+
+  ADDITIONAL_HEADER_DIRS
+  ${MLIR_MAIN_INCLUDE_DIR}/mlir/Dialect/ArmSME
+
+  DEPENDS
+  MLIRArmSMEIncGen
+
+  LINK_LIBS PUBLIC
+  MLIRIR
+  MLIRLLVMDialect
+  MLIRSideEffectInterfaces
+  )

mlir/lib/Dialect/ArmSME/Transforms/CMakeLists.txt

+add_mlir_dialect_library(MLIRArmSMETransforms
+  LegalizeForLLVMExport.cpp
+
+  DEPENDS
+  MLIRArmSMEConversionsIncGen
+
+  LINK_LIBS PUBLIC
+  MLIRArmSMEDialect
+  MLIRFuncDialect
+  MLIRIR
+  MLIRLLVMCommonConversion
+  MLIRLLVMDialect
+  )

mlir/lib/Dialect/ArmSME/Transforms/LegalizeForLLVMExport.cpp

+//===- LegalizeForLLVMExport.cpp - Prepare ArmSME for LLVM translation ----===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "mlir/Conversion/LLVMCommon/ConversionTarget.h"
+#include "mlir/Conversion/LLVMCommon/Pattern.h"
+#include "mlir/Dialect/Arith/IR/Arith.h"
+#include "mlir/Dialect/ArmSME/ArmSMEDialect.h"
+#include "mlir/Dialect/ArmSME/Transforms.h"
+#include "mlir/Dialect/Func/IR/FuncOps.h"
+#include "mlir/Dialect/LLVMIR/LLVMDialect.h"
+#include "mlir/Dialect/Vector/IR/VectorOps.h"
+#include "mlir/IR/BuiltinOps.h"
+#include "mlir/IR/PatternMatch.h"
+#include "llvm/ADT/SmallVector.h"
+
+using namespace mlir;
+using namespace mlir::arm_sme;
+
+template <typename MOPTy>
+class MOPLowering : public OpConversionPattern<MOPTy> {
+  using OpConversionPattern<MOPTy>::OpConversionPattern;
+  LogicalResult
+  matchAndRewrite(MOPTy op, typename MOPTy::Adaptor adaptor,
+                  ConversionPatternRewriter &rewriter) const final {
+    (void)adaptor;
+    Location loc = op.getLoc();
+    SmallVector<Value, 5> operands;
+    auto tile = static_cast<uint32_t>(op.getTile());
+    // Operands:
+    // Tile number
+    operands.push_back(
+        rewriter.create<LLVM::ConstantOp>(loc, rewriter.getI32Type(), tile)
+            .getResult());
+    if (op.isWidening()) {
+      return op.emitOpError("lowering of widening SME outer product "
+                            "instructions not yet supported");
+    }
+    // Predicates
+    operands.push_back(op.getLhsPred());
+    operands.push_back(op.getRhsPred());
+    // Input vectors
+    operands.push_back(op.getLhs());
+    operands.push_back(op.getRhs());
+    Type lhsElTy =
+        op.getLhs().getType().template cast<VectorType>().getElementType();
+    Type rhsElTy =
+        op.getRhs().getType().template cast<VectorType>().getElementType();
+    ValueRange operandsRange(operands);
+    switch (op.isAccumulate()) {
+    case true:
+      // MOPA ops
+      if (lhsElTy.isF32() || lhsElTy.isF64())
+        rewriter.create<FmopaIntrOp>(loc, TypeRange{}, operandsRange);
+      else if (lhsElTy.isF16() || lhsElTy.isBF16())
+        rewriter.create<FmopaWidenIntrOp>(loc, TypeRange{}, operandsRange);
+      else if (lhsElTy.isSignedInteger() && rhsElTy.isSignedInteger())
+        rewriter.create<SmopaIntrOp>(loc, TypeRange{}, operandsRange);
+      else if (lhsElTy.isSignedInteger() && rhsElTy.isUnsignedInteger())
+        rewriter.create<SUmopaIntrOp>(loc, TypeRange{}, operandsRange);
+      else if (lhsElTy.isUnsignedInteger() && rhsElTy.isSignedInteger())
+        rewriter.create<USmopaIntrOp>(loc, TypeRange{}, operandsRange);
+      else if (lhsElTy.isUnsignedInteger() && rhsElTy.isUnsignedInteger())
+        rewriter.create<UmopaIntrOp>(loc, TypeRange{}, operandsRange);
+      else
+        return op.emitOpError("unsupported SME vector element type");
+      break;
+    case false:
+      // MOPS ops
+      if (lhsElTy.isF32() || lhsElTy.isF64())
+        rewriter.create<FmopsIntrOp>(loc, TypeRange{}, operandsRange);
+      else if (lhsElTy.isF16() || lhsElTy.isBF16())
+        rewriter.create<FmopsWidenIntrOp>(loc, TypeRange{}, operandsRange);
+      else if (lhsElTy.isSignedInteger() && rhsElTy.isSignedInteger())
+        rewriter.create<SmopsIntrOp>(loc, TypeRange{}, operandsRange);
+      else if (lhsElTy.isSignedInteger() && rhsElTy.isUnsignedInteger())
+        rewriter.create<SUmopsIntrOp>(loc, TypeRange{}, operandsRange);
+      else if (lhsElTy.isUnsignedInteger() && rhsElTy.isSignedInteger())
+        rewriter.create<USmopsIntrOp>(loc, TypeRange{}, operandsRange);
+      else if (lhsElTy.isUnsignedInteger() && rhsElTy.isUnsignedInteger())
+        rewriter.create<UmopsIntrOp>(loc, TypeRange{}, operandsRange);
+      else
+        return op.emitOpError("unsupported SME vector element type");
+    }
+    rewriter.eraseOp(op);
+    return LogicalResult::success();
+  }
+};
+
+class ZeroOpLowering : public OpConversionPattern<ZeroOp> {
+  using OpConversionPattern<ZeroOp>::OpConversionPattern;
+  LogicalResult
+  matchAndRewrite(ZeroOp op, ZeroOpAdaptor adaptor,
+                  ConversionPatternRewriter &rewriter) const final {
+    (void)adaptor;
+    Location loc = op.getLoc();
+    ArrayAttr tiles = op.getTiles();
+    uint32_t tileNum = 0;
+    for (auto tile : tiles) {
+      auto tileEnum = tile.cast<TileEnumAttr>().getValue();
+      tileNum |= static_cast<uint32_t>(tileEnum);
+    }
+    Value tileVal =
+        rewriter.create<LLVM::ConstantOp>(loc, rewriter.getI32Type(), tileNum);
+    rewriter.create<ZeroIntrOp>(loc, tileVal);
+    rewriter.eraseOp(op);
+    return LogicalResult::success();
+  }
+};
+
+/// Populate the given list with patterns that convert from ArmSME to LLVM.
+void mlir::populateArmSMELegalizeForLLVMExportPatterns(
+    LLVMTypeConverter &converter, RewritePatternSet &patterns) {
+  // Populate conversion patterns
+  // clang-format off
+  patterns.add<MOPLowering<MopaOp>,
+               MOPLowering<MopsOp>,
+               ZeroOpLowering>(converter, &converter.getContext());
+  // clang-format on
+}
+
+void mlir::configureArmSMELegalizeForExportTarget(
+    LLVMConversionTarget &target) {
+  // clang-format off
+  target.addLegalOp<ZeroIntrOp,
+                    FmopaIntrOp, FmopsIntrOp,
+                    FmopaWidenIntrOp, FmopsWidenIntrOp,
+                    SmopaIntrOp, SmopsIntrOp,
+                    UmopaIntrOp, UmopsIntrOp,
+                    SUmopaIntrOp, SUmopsIntrOp,
+                    USmopaIntrOp, USmopsIntrOp,
+                    LoadHorizontalBytesIntrOp,
+                    LoadHorizontalHalfsIntrOp,
+                    LoadHorizontalWordsIntrOp,
+                    LoadHorizontalDoublesIntrOp,
+                    LoadHorizontalQuadsIntrOp,
+                    StoreVerticalBytesIntrOp,
+                    StoreVerticalHalfsIntrOp,
+                    StoreVerticalWordsIntrOp,
+                    StoreVerticalDoublesIntrOp,
+                    StoreVerticalQuadsIntrOp>();
+  target.addIllegalOp<MopaOp, MopsOp>();
+  // clang-format on
+}

mlir/lib/Dialect/CMakeLists.txt

 add_subdirectory(Affine)
 add_subdirectory(AMDGPU)
 add_subdirectory(Arith)
 add_subdirectory(ArmNeon)
+add_subdirectory(ArmSME)
 add_subdirectory(ArmSVE)
 add_subdirectory(Async)
 add_subdirectory(AMX)
 add_subdirectory(Bufferization)
 add_subdirectory(Complex)
 add_subdirectory(ControlFlow)
 add_subdirectory(DLTI)
 add_subdirectory(EmitC)

mlir/lib/Target/LLVMIR/CMakeLists.txt

add_mlir_translation_library(MLIRTargetLLVMIRExport
   MLIRTranslateLib
   )
 
 add_mlir_translation_library(MLIRToLLVMIRTranslationRegistration
   ConvertToLLVMIR.cpp
 
   LINK_LIBS PUBLIC
   MLIRArmNeonToLLVMIRTranslation
+  MLIRArmSMEToLLVMIRTranslation
   MLIRArmSVEToLLVMIRTranslation
   MLIRAMXToLLVMIRTranslation
   MLIRX86VectorToLLVMIRTranslation
   MLIRLLVMToLLVMIRTranslation
   MLIRNVVMToLLVMIRTranslation
   MLIROpenACCToLLVMIRTranslation
   MLIROpenMPToLLVMIRTranslation
   MLIRROCDLToLLVMIRTranslation

mlir/lib/Target/LLVMIR/Dialect/ArmSME/ArmSMEToLLVMIRTranslation.cpp

+//======- ArmSMEToLLVMIRTranslation.cpp - Translate ArmSME to LLVM IR -=======//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements a translation between the ArmSME dialect and LLVM IR.
+//
+//===----------------------------------------------------------------------===//
+
+#include "mlir/Target/LLVMIR/Dialect/ArmSME/ArmSMEToLLVMIRTranslation.h"
+#include "mlir/Dialect/ArmSME/ArmSMEDialect.h"
+#include "mlir/IR/Operation.h"
+#include "mlir/Target/LLVMIR/ModuleTranslation.h"
+
+#include "llvm/IR/IRBuilder.h"
+#include "llvm/IR/IntrinsicsAArch64.h"
+
+using namespace mlir;
+using namespace mlir::LLVM;
+
+namespace {
+/// Implementation of the dialect interface that converts operations belonging
+/// to the ArmSME dialect to LLVM IR.
+class ArmSMEDialectLLVMIRTranslationInterface
+    : public LLVMTranslationDialectInterface {
+public:
+  using LLVMTranslationDialectInterface::LLVMTranslationDialectInterface;
+
+  /// Translates the given operation to LLVM IR using the provided IR builder
+  /// and saving the state in `moduleTranslation`.
+  LogicalResult
+  convertOperation(Operation *op, llvm::IRBuilderBase &builder,
+                   LLVM::ModuleTranslation &moduleTranslation) const final {
+    Operation &opInst = *op;
+#include "mlir/Dialect/ArmSME/ArmSMEConversions.inc"
+
+    return failure();
+  }
+};
+} // namespace
+
+void mlir::registerArmSMEDialectTranslation(DialectRegistry &registry) {
+  registry.insert<arm_sme::ArmSMEDialect>();
+  registry.addExtension(+[](MLIRContext *ctx, arm_sme::ArmSMEDialect *dialect) {
+    dialect->addInterfaces<ArmSMEDialectLLVMIRTranslationInterface>();
+  });
+}
+
+void mlir::registerArmSMEDialectTranslation(MLIRContext &context) {
+  DialectRegistry registry;
+  registerArmSMEDialectTranslation(registry);
+  context.appendDialectRegistry(registry);
+}

mlir/lib/Target/LLVMIR/Dialect/ArmSME/CMakeLists.txt

+add_mlir_translation_library(MLIRArmSMEToLLVMIRTranslation
+  ArmSMEToLLVMIRTranslation.cpp
+
+  DEPENDS
+  MLIRArmSMEConversionsIncGen
+
+  LINK_COMPONENTS
+  Core
+
+  LINK_LIBS PUBLIC
+  MLIRIR
+  MLIRArmSMEDialect
+  MLIRLLVMDialect
+  MLIRSupport
+  MLIRTargetLLVMIRExport
+  )

mlir/lib/Target/LLVMIR/Dialect/CMakeLists.txt

 add_subdirectory(ArmNeon)
+add_subdirectory(ArmSME)
 add_subdirectory(ArmSVE)
 add_subdirectory(AMX)
 add_subdirectory(LLVMIR)
 add_subdirectory(NVVM)
 add_subdirectory(OpenACC)
 add_subdirectory(OpenMP)
 add_subdirectory(ROCDL)
 add_subdirectory(X86Vector)

mlir/test/Dialect/ArmSME/lower-llvm.mlir

+// RUN: mlir-opt %s -convert-vector-to-llvm="enable-arm-sme"  -convert-func-to-llvm | mlir-translate --mlir-to-llvmir | FileCheck %s
+func.func @arm_sme_lower(%0 : vector<[2]xf64>, %1 : vector<[4]xf32>) {
+  %c = arith.constant 128 : index
+  %pred.64 = vector.create_mask  %c : vector<[2]xi1>
+  // CHECK: call void @llvm.aarch64.sme.zero(i32 255)
+  arm_sme.zero za0d, za1d, za2d, za3d, za4d, za5d, za6d, za7d, za0s, za1s, za2s, za3s
+  // CHECK: call void @llvm.aarch64.sme.mopa.nxv2f64(i32 1,
+  arm_sme.mopa za0d, %pred.64, %pred.64, %0, %0 : vector<[2]xi1>, vector<[2]xi1>, vector<[2]xf64>, vector<[2]xf64>
+  %pred.32 = vector.create_mask  %c : vector<[4]xi1>
+  // CHECK: call void @llvm.aarch64.sme.mopa.nxv4f32(i32 17,
+  arm_sme.mopa za0s, %pred.32, %pred.32, %1, %1 : vector<[4]xi1>, vector<[4]xi1>, vector<[4]xf32>, vector<[4]xf32>
+  return
+}

mlir/test/Dialect/ArmSME/roundtrip.mlir

+// RUN: mlir-opt %s
+func.func @arm_sme_ops(%0 : vector<[2]xf64>,
+                       %1 : vector<[4]xf32>,
+                       %2 : vector<[4x2]xf16>,
+                       %3 : vector<[2x4]xsi16>) {
+  %c = arith.constant 128 : index
+  %pred.64 = vector.create_mask %c : vector<[2]xi1>
+  arm_sme.zero za0d, za1d, za2d, za3d, za4d, za5d, za6d, za7d, za0s, za1s, za2s, za3s
+  arm_sme.mopa za0d, %pred.64, %pred.64, %0, %0 : vector<[2]xi1>, vector<[2]xi1>, vector<[2]xf64>, vector<[2]xf64>
+  %pred.32 = vector.create_mask %c : vector<[4]xi1>
+  arm_sme.mopa za0s, %pred.32, %pred.32, %1, %1 : vector<[4]xi1>, vector<[4]xi1>, vector<[4]xf32>, vector<[4]xf32>
+  %pred.16 = vector.create_mask %c, %c : vector<[4x2]xi1>
+  arm_sme.mopa za1s, %pred.16, %pred.16, %2, %2 : vector<[4x2]xi1>, vector<[4x2]xi1>, vector<[4x2]xf16>, vector<[4x2]xf16>
+  %pred.i16 = vector.create_mask %c, %c : vector<[2x4]xi1>
+  arm_sme.mopa za1d, %pred.i16, %pred.i16, %3, %3 : vector<[2x4]xi1>, vector<[2x4]xi1>, vector<[2x4]xsi16>, vector<[2x4]xsi16>
+  return
+}

mlir/test/mlir-opt/commandline.mlir

 // RUN: mlir-opt --show-dialects | FileCheck %s
 // CHECK: Available Dialects:
 // CHECK-NEXT: acc
 // CHECK-NEXT: affine
 // CHECK-NEXT: amdgpu
 // CHECK-NEXT: amx
 // CHECK-NEXT: arith
 // CHECK-NEXT: arm_neon
+// CHECK-NEXT: arm_sme
 // CHECK-NEXT: arm_sve
 // CHECK-NEXT: async
 // CHECK-NEXT: bufferization
 // CHECK-NEXT: builtin
 // CHECK-NEXT: cf
 // CHECK-NEXT: complex
 // CHECK-NEXT: dlti
 // CHECK-NEXT: emitc