InstCombine: Match pattern that appears in clang's __builtin_isnormal

[arsenm]

Summary

and (fcmp ord x, 0), (fcmp u* x, inf) -> fcmp o* x, inf
and (fcmp ord x, 0), (fcmp u* fabs(x), inf) -> fcmp o* x, inf

Clang emits this peculiar pattern as an isfinite check in
__builtin_isnormal which can be simplified. We should fix clang to
emit this in the first place, but should also fold it here.

[foad]

Looks reasonable to me. It could be relaxed a bit (e.g. the constants 0 and inf could be any non-nan constant values) but I guess there's no particular use case for that.

[arsenm]

In D139311#3970681, @foad wrote:

Looks reasonable to me. It could be relaxed a bit (e.g. the constants 0 and inf could be any non-nan constant values) but I guess there's no particular use case for that.

I thought about handling non-canonical fcmp ord/uno, but I can't write a test that meaningfully changes for that

[arsenm]

ping

[foad]

llvm/lib/IR/Instructions.cpp

4098 ↗

(On Diff #480061)

This whole function is just return Pred & 7;. See the definition of CmpInst::Predicate. The floating point predicates are carefully numbered to make exactly this kind of thing possible.

[arsenm]

Use & FCMP_ORD

[foad]

llvm/include/llvm/IR/InstrTypes.h

839

Argument name should be capitalized (though the existing functions are inconsistent on this).

llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp

1229

Comment seems wrong - this function doesn't do anything with fabs.

1307

Do you need to worry about IsLogicalSelect here?

[arsenm]

llvm/include/llvm/IR/InstrTypes.h

839

Right this was just copy paste from the others

llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp

1229

It's not wrong, it's just the fabs stripping is applied in the predicate where it's called

1307

I don't really know what IsLogicalSelect means

[arsenm]

llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp

1307

I reproduced a case from a select and alive2 seems to not have an issue with it

[arsenm]

Add test coverage for logical select case. Alive says it's fine

[foad]

llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp

1229

I think the comment on this function should say what this function does. I can't see how this function strips anything. Also what is y in the comment?

[sepavloff]

llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp

1217–1220

As this is fcmp ord, the name matchIsNotNaN would be better.

IR producer (not necessarily clang) may chose any form of NaN check, so the check must test both forms, fcmp ord x, const or fcmp ord x, x.

1232

The function name is not clear enough. Why not matchFiniteTest() or something similar?

[arsenm]

llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp

1217–1220

And that get canonicalized into fcmp ord with a zero already. Clang actually emits a non canonical ordered check in isnormal as it is

[arsenm]

Rename functions, move comments.

Also stop bothering with getFCmpValue because we can't end up with a compare true/false here

[arsenm]

effde7f43e26091678dcd5a8f3eb8f344f1be8a7

llvm/include/llvm/IR/InstrTypes.h

public:
   /// For example, EQ -> NE, UGT -> ULE, SLT -> SGE,
   ///              OEQ -> UNE, UGT -> OLE, OLT -> UGE, etc.
   /// @returns the inverse predicate for the instruction's current predicate.
   /// Return the inverse of the instruction's predicate.
   Predicate getInversePredicate() const {
     return getInversePredicate(getPredicate());
   }
 
+  /// Returns the ordered variant of a floating point compare.
+  ///
+  /// For example, UEQ -> OEQ, ULT -> OLT, OEQ -> OEQ
+  static Predicate getOrderedPredicate(Predicate Pred) {
+    return static_cast<Predicate>(Pred & FCMP_ORD);
+  }
+
+  Predicate getOrderedPredicate() const {
+    return getOrderedPredicate(getPredicate());
+  }
+
   /// For example, EQ -> NE, UGT -> ULE, SLT -> SGE,
   ///              OEQ -> UNE, UGT -> OLE, OLT -> UGE, etc.
   /// @returns the inverse predicate for predicate provided in \p pred.
   /// Return the inverse of a given predicate
   static Predicate getInversePredicate(Predicate pred);
 
   /// For example, EQ->EQ, SLE->SGE, ULT->UGT,
   ///              OEQ->OEQ, ULE->UGE, OLT->OGT, etc.

llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp

Value *InstCombinerImpl::foldAndOrOfICmpsUsingRanges(ICmpInst *ICmp1,
   APInt NewC, Offset;
   CR->getEquivalentICmp(NewPred, NewC, Offset);
 
   if (Offset != 0)
     NewV = Builder.CreateAdd(NewV, ConstantInt::get(Ty, Offset));
   return Builder.CreateICmp(NewPred, NewV, ConstantInt::get(Ty, NewC));
 }
 
+/// Ignore all operations which only change the sign of a value, returning the
+/// underlying magnitude value.
+static Value *stripSignOnlyFPOps(Value *Val) {
+  match(Val, m_FNeg(m_Value(Val)));
+  match(Val, m_FAbs(m_Value(Val)));
+  match(Val, m_CopySign(m_Value(Val), m_Value()));
+  return Val;
+}
+
+/// Matches canonical form of isnan, fcmp ord x, 0
+static bool matchIsNotNaN(FCmpInst::Predicate P, Value *LHS, Value *RHS) {
+  return P == FCmpInst::FCMP_ORD && match(RHS, m_AnyZeroFP());
+}
+
+/// Matches fcmp u__ x, +/-inf
+static bool matchUnorderedInfCompare(FCmpInst::Predicate P, Value *LHS,
+                                     Value *RHS) {
+  return FCmpInst::isUnordered(P) && match(RHS, m_Inf());
+}
+
+/// and (fcmp ord x, 0), (fcmp u* x, inf) -> fcmp o* x, inf
+///
+/// Clang emits this pattern for doing an isfinite check in __builtin_isnormal.
+static Value *matchIsFiniteTest(InstCombiner::BuilderTy &Builder, FCmpInst *LHS,
+                                FCmpInst *RHS) {
+  Value *LHS0 = LHS->getOperand(0), *LHS1 = LHS->getOperand(1);
+  Value *RHS0 = RHS->getOperand(0), *RHS1 = RHS->getOperand(1);
+  FCmpInst::Predicate PredL = LHS->getPredicate(), PredR = RHS->getPredicate();
+
+  if (!matchIsNotNaN(PredL, LHS0, LHS1) ||
+      !matchUnorderedInfCompare(PredR, RHS0, RHS1))
+    return nullptr;
+
+  IRBuilder<>::FastMathFlagGuard FMFG(Builder);
+  FastMathFlags FMF = LHS->getFastMathFlags();
+  FMF &= RHS->getFastMathFlags();
+  Builder.setFastMathFlags(FMF);
+
+  return Builder.CreateFCmp(FCmpInst::getOrderedPredicate(PredR), RHS0, RHS1);
+}
+
 Value *InstCombinerImpl::foldLogicOfFCmps(FCmpInst *LHS, FCmpInst *RHS,
                                           bool IsAnd, bool IsLogicalSelect) {
   Value *LHS0 = LHS->getOperand(0), *LHS1 = LHS->getOperand(1);
   Value *RHS0 = RHS->getOperand(0), *RHS1 = RHS->getOperand(1);
   FCmpInst::Predicate PredL = LHS->getPredicate(), PredR = RHS->getPredicate();
 
   if (LHS0 == RHS1 && RHS0 == LHS1) {
     // Swap RHS operands to match LHS.
if (!IsLogicalSelect &&
     // (fcmp ord/uno X, C) will be transformed to (fcmp X, +0.0).
     if (match(LHS1, m_PosZeroFP()) && match(RHS1, m_PosZeroFP()))
       // Ignore the constants because they are obviously not NANs:
       // (fcmp ord x, 0.0) & (fcmp ord y, 0.0)  -> (fcmp ord x, y)
       // (fcmp uno x, 0.0) | (fcmp uno y, 0.0)  -> (fcmp uno x, y)
       return Builder.CreateFCmp(PredL, LHS0, RHS0);
   }
 
+  if (IsAnd && stripSignOnlyFPOps(LHS0) == stripSignOnlyFPOps(RHS0)) {
+    // and (fcmp ord x, 0), (fcmp u* x, inf) -> fcmp o* x, inf
+    // and (fcmp ord x, 0), (fcmp u* fabs(x), inf) -> fcmp o* x, inf
+    if (Value *Left = matchIsFiniteTest(Builder, LHS, RHS))
+      return Left;
+    if (Value *Right = matchIsFiniteTest(Builder, RHS, LHS))
+      return Right;
+  }
+
   return nullptr;
 }
 
 /// or (is_fpclass x, mask0), (is_fpclass x, mask1)
 ///     -> is_fpclass x, (mask0 | mask1)
 /// and (is_fpclass x, mask0), (is_fpclass x, mask1)
 ///     -> is_fpclass x, (mask0 & mask1)
 /// xor (is_fpclass x, mask0), (is_fpclass x, mask1)

llvm/test/Transforms/InstCombine/and-fcmp.ll

;
   ret i1 %retval
 }
 
 ; Clang used to emit this pattern in __builtin_isnormal
 ; https://alive2.llvm.org/ce/z/8sw9vi
 define i1 @clang_builtin_isnormal_inf_check(half %x) {
 ; CHECK-LABEL: @clang_builtin_isnormal_inf_check(
 ; CHECK-NEXT:    [[FABS_X:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT:    [[ORD:%.*]] = fcmp ord half [[X]], 0xH0000
-; CHECK-NEXT:    [[CMP:%.*]] = fcmp uge half [[FABS_X]], 0xH7C00
-; CHECK-NEXT:    [[AND:%.*]] = and i1 [[ORD]], [[CMP]]
-; CHECK-NEXT:    ret i1 [[AND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = fcmp oge half [[FABS_X]], 0xH7C00
+; CHECK-NEXT:    ret i1 [[TMP1]]
 ;
   %fabs.x = call half @llvm.fabs.f16(half %x)
   %ord = fcmp ord half %fabs.x, 0.0
   %cmp = fcmp uge half %fabs.x, 0xH7C00
   %and = and i1 %ord, %cmp
   ret i1 %and
 }
 
 define <2 x i1> @clang_builtin_isnormal_inf_check_vector(<2 x half> %x) {
 ; CHECK-LABEL: @clang_builtin_isnormal_inf_check_vector(
 ; CHECK-NEXT:    [[FABS_X:%.*]] = call <2 x half> @llvm.fabs.v2f16(<2 x half> [[X:%.*]])
-; CHECK-NEXT:    [[ORD:%.*]] = fcmp ord <2 x half> [[X]], zeroinitializer
-; CHECK-NEXT:    [[CMP:%.*]] = fcmp uge <2 x half> [[FABS_X]], <half 0xH7C00, half 0xH7C00>
-; CHECK-NEXT:    [[AND:%.*]] = and <2 x i1> [[ORD]], [[CMP]]
-; CHECK-NEXT:    ret <2 x i1> [[AND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = fcmp oge <2 x half> [[FABS_X]], <half 0xH7C00, half 0xH7C00>
+; CHECK-NEXT:    ret <2 x i1> [[TMP1]]
 ;
   %fabs.x = call <2 x half> @llvm.fabs.v2f16(<2 x half> %x)
   %ord = fcmp ord <2 x half> %fabs.x, zeroinitializer
   %cmp = fcmp uge <2 x half> %fabs.x, <half 0xH7C00, half 0xH7C00>
   %and = and <2 x i1> %ord, %cmp
   ret <2 x i1> %and
 }
 
 define i1 @clang_builtin_isnormal_inf_check_commute(half %x) {
 ; CHECK-LABEL: @clang_builtin_isnormal_inf_check_commute(
 ; CHECK-NEXT:    [[FABS_X:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT:    [[ORD:%.*]] = fcmp ord half [[X]], 0xH0000
-; CHECK-NEXT:    [[CMP:%.*]] = fcmp uge half [[FABS_X]], 0xH7C00
-; CHECK-NEXT:    [[AND:%.*]] = and i1 [[CMP]], [[ORD]]
-; CHECK-NEXT:    ret i1 [[AND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = fcmp oge half [[FABS_X]], 0xH7C00
+; CHECK-NEXT:    ret i1 [[TMP1]]
 ;
   %fabs.x = call half @llvm.fabs.f16(half %x)
   %ord = fcmp ord half %fabs.x, 0.0
   %cmp = fcmp uge half %fabs.x, 0xH7C00
   %and = and i1 %cmp, %ord
   ret i1 %and
 }
 
 define i1 @clang_builtin_isnormal_inf_check_commute_nsz_rhs(half %x) {
 ; CHECK-LABEL: @clang_builtin_isnormal_inf_check_commute_nsz_rhs(
 ; CHECK-NEXT:    [[FABS_X:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT:    [[ORD:%.*]] = fcmp nsz ord half [[X]], 0xH0000
-; CHECK-NEXT:    [[CMP:%.*]] = fcmp uge half [[FABS_X]], 0xH7C00
-; CHECK-NEXT:    [[AND:%.*]] = and i1 [[CMP]], [[ORD]]
-; CHECK-NEXT:    ret i1 [[AND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = fcmp oge half [[FABS_X]], 0xH7C00
+; CHECK-NEXT:    ret i1 [[TMP1]]
 ;
   %fabs.x = call half @llvm.fabs.f16(half %x)
   %ord = fcmp nsz ord half %fabs.x, 0.0
   %cmp = fcmp uge half %fabs.x, 0xH7C00
   %and = and i1 %cmp, %ord
   ret i1 %and
 }
 
 define i1 @clang_builtin_isnormal_inf_check_commute_nsz_lhs(half %x) {
 ; CHECK-LABEL: @clang_builtin_isnormal_inf_check_commute_nsz_lhs(
 ; CHECK-NEXT:    [[FABS_X:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT:    [[ORD:%.*]] = fcmp ord half [[X]], 0xH0000
-; CHECK-NEXT:    [[CMP:%.*]] = fcmp nsz uge half [[FABS_X]], 0xH7C00
-; CHECK-NEXT:    [[AND:%.*]] = and i1 [[CMP]], [[ORD]]
-; CHECK-NEXT:    ret i1 [[AND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = fcmp oge half [[FABS_X]], 0xH7C00
+; CHECK-NEXT:    ret i1 [[TMP1]]
 ;
   %fabs.x = call half @llvm.fabs.f16(half %x)
   %ord = fcmp ord half %fabs.x, 0.0
   %cmp = fcmp nsz uge half %fabs.x, 0xH7C00
   %and = and i1 %cmp, %ord
   ret i1 %and
 }
 
 define i1 @clang_builtin_isnormal_inf_check_commute_nofabs_ueq(half %x) {
 ; CHECK-LABEL: @clang_builtin_isnormal_inf_check_commute_nofabs_ueq(
-; CHECK-NEXT:    [[ORD:%.*]] = fcmp ord half [[X:%.*]], 0xH0000
-; CHECK-NEXT:    [[CMP:%.*]] = fcmp ueq half [[X]], 0xH7C00
-; CHECK-NEXT:    [[AND:%.*]] = and i1 [[CMP]], [[ORD]]
-; CHECK-NEXT:    ret i1 [[AND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = fcmp oeq half [[X:%.*]], 0xH7C00
+; CHECK-NEXT:    ret i1 [[TMP1]]
 ;
   %ord = fcmp ord half %x, 0.0
   %cmp = fcmp ueq half %x, 0xH7C00
   %and = and i1 %cmp, %ord
   ret i1 %and
 }
 
 define i1 @clang_builtin_isnormal_inf_check_commute_nsz(half %x) {
 ; CHECK-LABEL: @clang_builtin_isnormal_inf_check_commute_nsz(
 ; CHECK-NEXT:    [[FABS_X:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT:    [[ORD:%.*]] = fcmp nsz ord half [[X]], 0xH0000
-; CHECK-NEXT:    [[CMP:%.*]] = fcmp nsz uge half [[FABS_X]], 0xH7C00
-; CHECK-NEXT:    [[AND:%.*]] = and i1 [[CMP]], [[ORD]]
-; CHECK-NEXT:    ret i1 [[AND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = fcmp nsz oge half [[FABS_X]], 0xH7C00
+; CHECK-NEXT:    ret i1 [[TMP1]]
 ;
   %fabs.x = call half @llvm.fabs.f16(half %x)
   %ord = fcmp nsz ord half %fabs.x, 0.0
   %cmp = fcmp nsz uge half %fabs.x, 0xH7C00
   %and = and i1 %cmp, %ord
   ret i1 %and
 }
 
 ; ugt -> ogt
 define i1 @clang_builtin_isnormal_inf_check_ugt(half %x) {
 ; CHECK-LABEL: @clang_builtin_isnormal_inf_check_ugt(
-; CHECK-NEXT:    [[FABS_X:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT:    [[ORD:%.*]] = fcmp ord half [[X]], 0xH0000
-; CHECK-NEXT:    [[CMP:%.*]] = fcmp ugt half [[FABS_X]], 0xH7C00
-; CHECK-NEXT:    [[AND:%.*]] = and i1 [[ORD]], [[CMP]]
-; CHECK-NEXT:    ret i1 [[AND]]
+; CHECK-NEXT:    ret i1 false
 ;
   %fabs.x = call half @llvm.fabs.f16(half %x)
   %ord = fcmp ord half %fabs.x, 0.0
   %cmp = fcmp ugt half %fabs.x, 0xH7C00
   %and = and i1 %ord, %cmp
   ret i1 %and
 }
 
 ; ult -> olt
 define i1 @clang_builtin_isnormal_inf_check_ult(half %x) {
 ; CHECK-LABEL: @clang_builtin_isnormal_inf_check_ult(
 ; CHECK-NEXT:    [[FABS_X:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT:    [[ORD:%.*]] = fcmp ord half [[X]], 0xH0000
-; CHECK-NEXT:    [[CMP:%.*]] = fcmp ult half [[FABS_X]], 0xH7C00
-; CHECK-NEXT:    [[AND:%.*]] = and i1 [[ORD]], [[CMP]]
-; CHECK-NEXT:    ret i1 [[AND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = fcmp olt half [[FABS_X]], 0xH7C00
+; CHECK-NEXT:    ret i1 [[TMP1]]
 ;
   %fabs.x = call half @llvm.fabs.f16(half %x)
   %ord = fcmp ord half %fabs.x, 0.0
   %cmp = fcmp ult half %fabs.x, 0xH7C00
   %and = and i1 %ord, %cmp
   ret i1 %and
 }
 
;
   %and = and i1 %ord, %cmp
   ret i1 %and
 }
 
 ; ueq -> oeq
 define i1 @clang_builtin_isnormal_inf_check_ueq(half %x) {
 ; CHECK-LABEL: @clang_builtin_isnormal_inf_check_ueq(
 ; CHECK-NEXT:    [[FABS_X:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT:    [[ORD:%.*]] = fcmp ord half [[X]], 0xH0000
-; CHECK-NEXT:    [[CMP:%.*]] = fcmp ueq half [[FABS_X]], 0xH7C00
-; CHECK-NEXT:    [[AND:%.*]] = and i1 [[ORD]], [[CMP]]
-; CHECK-NEXT:    ret i1 [[AND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = fcmp oeq half [[FABS_X]], 0xH7C00
+; CHECK-NEXT:    ret i1 [[TMP1]]
 ;
   %fabs.x = call half @llvm.fabs.f16(half %x)
   %ord = fcmp ord half %fabs.x, 0.0
   %cmp = fcmp ueq half %fabs.x, 0xH7C00
   %and = and i1 %ord, %cmp
   ret i1 %and
 }
 
 ; une -> ole
 define i1 @clang_builtin_isnormal_inf_check_une(half %x) {
 ; CHECK-LABEL: @clang_builtin_isnormal_inf_check_une(
 ; CHECK-NEXT:    [[FABS_X:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT:    [[ORD:%.*]] = fcmp ord half [[X]], 0xH0000
-; CHECK-NEXT:    [[CMP:%.*]] = fcmp une half [[FABS_X]], 0xH7C00
-; CHECK-NEXT:    [[AND:%.*]] = and i1 [[ORD]], [[CMP]]
-; CHECK-NEXT:    ret i1 [[AND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = fcmp one half [[FABS_X]], 0xH7C00
+; CHECK-NEXT:    ret i1 [[TMP1]]
 ;
   %fabs.x = call half @llvm.fabs.f16(half %x)
   %ord = fcmp ord half %fabs.x, 0.0
   %cmp = fcmp une half %fabs.x, 0xH7C00
   %and = and i1 %ord, %cmp
   ret i1 %and
 }
 
;
   %cmp = fcmp oeq half %fabs.x, 0xH7C00
   %and = and i1 %ord, %cmp
   ret i1 %and
 }
 
 define i1 @clang_builtin_isnormal_inf_check_unnececcary_fabs(half %x) {
 ; CHECK-LABEL: @clang_builtin_isnormal_inf_check_unnececcary_fabs(
 ; CHECK-NEXT:    [[FABS_X:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT:    [[ORD:%.*]] = fcmp ord half [[X]], 0xH0000
-; CHECK-NEXT:    [[UEQ:%.*]] = fcmp uge half [[FABS_X]], 0xH7C00
-; CHECK-NEXT:    [[AND:%.*]] = and i1 [[ORD]], [[UEQ]]
-; CHECK-NEXT:    ret i1 [[AND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = fcmp oge half [[FABS_X]], 0xH7C00
+; CHECK-NEXT:    ret i1 [[TMP1]]
 ;
   %fabs.x = call half @llvm.fabs.f16(half %x)
   %ord = fcmp ord half %x, 0.0
   %ueq = fcmp uge half %fabs.x, 0xH7C00
   %and = and i1 %ord, %ueq
   ret i1 %and
 }
 
;
   %ord = fcmp uno half %fabs.x, 0.0
   %ueq = fcmp uge half %fabs.x, 0xH7C00
   %and = and i1 %ord, %ueq
   ret i1 %and
 }
 
 define i1 @clang_builtin_isnormal_inf_check_missing_fabs(half %x) {
 ; CHECK-LABEL: @clang_builtin_isnormal_inf_check_missing_fabs(
-; CHECK-NEXT:    [[ORD:%.*]] = fcmp ord half [[X:%.*]], 0xH0000
-; CHECK-NEXT:    [[UEQ:%.*]] = fcmp uge half [[X]], 0xH7C00
-; CHECK-NEXT:    [[AND:%.*]] = and i1 [[ORD]], [[UEQ]]
-; CHECK-NEXT:    ret i1 [[AND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = fcmp oge half [[X:%.*]], 0xH7C00
+; CHECK-NEXT:    ret i1 [[TMP1]]
 ;
   %fabs.x = call half @llvm.fabs.f16(half %x)
   %ord = fcmp ord half %x, 0.0
   %ueq = fcmp uge half %x, 0xH7C00
   %and = and i1 %ord, %ueq
   ret i1 %and
 }
 
;
   %ueq = fcmp uge half %fabs.x, 0xH7BFF
   %and = and i1 %ord, %ueq
   ret i1 %and
 }
 
 define i1 @clang_builtin_isnormal_inf_check_nsz_lhs(half %x) {
 ; CHECK-LABEL: @clang_builtin_isnormal_inf_check_nsz_lhs(
 ; CHECK-NEXT:    [[FABS_X:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT:    [[ORD:%.*]] = fcmp nsz ord half [[X]], 0xH0000
-; CHECK-NEXT:    [[UEQ:%.*]] = fcmp uge half [[FABS_X]], 0xH7C00
-; CHECK-NEXT:    [[AND:%.*]] = and i1 [[ORD]], [[UEQ]]
-; CHECK-NEXT:    ret i1 [[AND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = fcmp oge half [[FABS_X]], 0xH7C00
+; CHECK-NEXT:    ret i1 [[TMP1]]
 ;
   %fabs.x = call half @llvm.fabs.f16(half %x)
   %ord = fcmp nsz ord half %fabs.x, 0.0
   %ueq = fcmp uge half %fabs.x, 0xH7C00
   %and = and i1 %ord, %ueq
   ret i1 %and
 }
 
 define i1 @clang_builtin_isnormal_inf_check_nsz_rhs(half %x) {
 ; CHECK-LABEL: @clang_builtin_isnormal_inf_check_nsz_rhs(
 ; CHECK-NEXT:    [[FABS_X:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT:    [[ORD:%.*]] = fcmp ord half [[X]], 0xH0000
-; CHECK-NEXT:    [[UEQ:%.*]] = fcmp nsz uge half [[FABS_X]], 0xH7C00
-; CHECK-NEXT:    [[AND:%.*]] = and i1 [[ORD]], [[UEQ]]
-; CHECK-NEXT:    ret i1 [[AND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = fcmp oge half [[FABS_X]], 0xH7C00
+; CHECK-NEXT:    ret i1 [[TMP1]]
 ;
   %fabs.x = call half @llvm.fabs.f16(half %x)
   %ord = fcmp ord half %fabs.x, 0.0
   %ueq = fcmp nsz uge half %fabs.x, 0xH7C00
   %and = and i1 %ord, %ueq
   ret i1 %and
 }
 
 define i1 @clang_builtin_isnormal_inf_check_nsz(half %x) {
 ; CHECK-LABEL: @clang_builtin_isnormal_inf_check_nsz(
 ; CHECK-NEXT:    [[FABS_X:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT:    [[ORD:%.*]] = fcmp nsz ord half [[X]], 0xH0000
-; CHECK-NEXT:    [[UEQ:%.*]] = fcmp nsz uge half [[FABS_X]], 0xH7C00
-; CHECK-NEXT:    [[AND:%.*]] = and i1 [[ORD]], [[UEQ]]
-; CHECK-NEXT:    ret i1 [[AND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = fcmp nsz oge half [[FABS_X]], 0xH7C00
+; CHECK-NEXT:    ret i1 [[TMP1]]
 ;
   %fabs.x = call half @llvm.fabs.f16(half %x)
   %ord = fcmp nsz ord half %fabs.x, 0.0
   %ueq = fcmp nsz uge half %fabs.x, 0xH7C00
   %and = and i1 %ord, %ueq
   ret i1 %and
 }
 
 define i1 @clang_builtin_isnormal_inf_check_fneg(half %x) {
 ; CHECK-LABEL: @clang_builtin_isnormal_inf_check_fneg(
-; CHECK-NEXT:    [[ORD:%.*]] = fcmp ord half [[X:%.*]], 0xH0000
-; CHECK-NEXT:    [[CMP:%.*]] = fcmp uge half [[X]], 0xH7C00
-; CHECK-NEXT:    [[AND:%.*]] = and i1 [[ORD]], [[CMP]]
-; CHECK-NEXT:    ret i1 [[AND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = fcmp oge half [[X:%.*]], 0xH7C00
+; CHECK-NEXT:    ret i1 [[TMP1]]
 ;
   %fneg.x = fneg half %x
   %ord = fcmp ord half %fneg.x, 0.0
   %cmp = fcmp uge half %x, 0xH7C00
   %and = and i1 %ord, %cmp
   ret i1 %and
 }
 
 define i1 @clang_builtin_isnormal_inf_check_copysign(half %x, half %y) {
 ; CHECK-LABEL: @clang_builtin_isnormal_inf_check_copysign(
 ; CHECK-NEXT:    [[COPYSIGN_X:%.*]] = call half @llvm.copysign.f16(half [[X:%.*]], half [[Y:%.*]])
-; CHECK-NEXT:    [[ORD:%.*]] = fcmp ord half [[X]], 0xH0000
-; CHECK-NEXT:    [[CMP:%.*]] = fcmp uge half [[COPYSIGN_X]], 0xH7C00
-; CHECK-NEXT:    [[AND:%.*]] = and i1 [[ORD]], [[CMP]]
-; CHECK-NEXT:    ret i1 [[AND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = fcmp oge half [[COPYSIGN_X]], 0xH7C00
+; CHECK-NEXT:    ret i1 [[TMP1]]
 ;
   %copysign.x = call half @llvm.copysign.f16(half %x, half %y)
   %ord = fcmp ord half %x, 0.0
   %cmp = fcmp uge half %copysign.x, 0xH7C00
   %and = and i1 %ord, %cmp
   ret i1 %and
 }
 
 define i1 @isnormal_logical_select_0(half %x) {
 ; CHECK-LABEL: @isnormal_logical_select_0(
 ; CHECK-NEXT:    [[FABS_X:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT:    [[ORD:%.*]] = fcmp ord half [[X]], 0xH0000
-; CHECK-NEXT:    [[CMP_INF:%.*]] = fcmp uge half [[FABS_X]], 0xH7C00
-; CHECK-NEXT:    [[AND:%.*]] = and i1 [[ORD]], [[CMP_INF]]
-; CHECK-NEXT:    ret i1 [[AND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = fcmp oge half [[FABS_X]], 0xH7C00
+; CHECK-NEXT:    ret i1 [[TMP1]]
 ;
   %fabs.x = call half @llvm.fabs.f16(half %x)
   %ord = fcmp ord half %fabs.x, 0.0
   %cmp.inf = fcmp uge half %fabs.x, 0xH7C00
   %and = select i1 %ord, i1 %cmp.inf, i1 false
   ret i1 %and
 }
 
 define i1 @isnormal_logical_select_1(half %x) {
 ; CHECK-LABEL: @isnormal_logical_select_1(
 ; CHECK-NEXT:    [[FABS_X:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT:    [[ORD:%.*]] = fcmp ord half [[X]], 0xH0000
-; CHECK-NEXT:    [[CMP_INF:%.*]] = fcmp uge half [[FABS_X]], 0xH7C00
-; CHECK-NEXT:    [[AND:%.*]] = select i1 [[CMP_INF]], i1 [[ORD]], i1 false
-; CHECK-NEXT:    ret i1 [[AND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = fcmp oge half [[FABS_X]], 0xH7C00
+; CHECK-NEXT:    ret i1 [[TMP1]]
 ;
   %fabs.x = call half @llvm.fabs.f16(half %x)
   %ord = fcmp ord half %fabs.x, 0.0
   %cmp.inf = fcmp uge half %fabs.x, 0xH7C00
   %and = select i1 %cmp.inf, i1 %ord, i1 false
   ret i1 %and
 }
 
 define i1 @isnormal_logical_select_0_fmf0(half %x) {
 ; CHECK-LABEL: @isnormal_logical_select_0_fmf0(
 ; CHECK-NEXT:    [[FABS_X:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT:    [[ORD:%.*]] = fcmp reassoc nsz arcp ord half [[X]], 0xH0000
-; CHECK-NEXT:    [[CMP_INF:%.*]] = fcmp reassoc nsz arcp uge half [[FABS_X]], 0xH7C00
-; CHECK-NEXT:    [[AND:%.*]] = and i1 [[ORD]], [[CMP_INF]]
-; CHECK-NEXT:    ret i1 [[AND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = fcmp reassoc nsz arcp oge half [[FABS_X]], 0xH7C00
+; CHECK-NEXT:    ret i1 [[TMP1]]
 ;
   %fabs.x = call half @llvm.fabs.f16(half %x)
   %ord = fcmp nsz arcp reassoc ord half %fabs.x, 0.0
   %cmp.inf = fcmp nsz arcp reassoc uge half %fabs.x, 0xH7C00
   %and = select i1 %ord, i1 %cmp.inf, i1 false
   ret i1 %and
 }
 
 define i1 @isnormal_logical_select_0_fmf1(half %x) {
 ; CHECK-LABEL: @isnormal_logical_select_0_fmf1(
 ; CHECK-NEXT:    [[FABS_X:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT:    [[ORD:%.*]] = fcmp ord half [[X]], 0xH0000
-; CHECK-NEXT:    [[CMP_INF:%.*]] = fcmp reassoc nsz arcp uge half [[FABS_X]], 0xH7C00
-; CHECK-NEXT:    [[AND:%.*]] = and i1 [[ORD]], [[CMP_INF]]
-; CHECK-NEXT:    ret i1 [[AND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = fcmp oge half [[FABS_X]], 0xH7C00
+; CHECK-NEXT:    ret i1 [[TMP1]]
 ;
   %fabs.x = call half @llvm.fabs.f16(half %x)
   %ord = fcmp ord half %fabs.x, 0.0
   %cmp.inf = fcmp nsz arcp reassoc uge half %fabs.x, 0xH7C00
   %and = select i1 %ord, i1 %cmp.inf, i1 false
   ret i1 %and
 }
 
 declare half @llvm.fabs.f16(half)
 declare <2 x half> @llvm.fabs.v2f16(<2 x half>)
 declare half @llvm.copysign.f16(half, half)

llvm/test/Transforms/InstCombine/create-class-from-logic-fcmp.ll

 
 ; --------------------------------------------------------------------
 ; Test ord/uno
 ; --------------------------------------------------------------------
 
 define i1 @is_finite_and_ord(half %x) {
 ; CHECK-LABEL: @is_finite_and_ord(
 ; CHECK-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT:    [[IS_FINITE:%.*]] = fcmp ueq half [[FABS]], 0xH7C00
-; CHECK-NEXT:    [[ORD:%.*]] = fcmp ord half [[X]], 0xH0000
-; CHECK-NEXT:    [[AND:%.*]] = and i1 [[ORD]], [[IS_FINITE]]
-; CHECK-NEXT:    ret i1 [[AND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = fcmp oeq half [[FABS]], 0xH7C00
+; CHECK-NEXT:    ret i1 [[TMP1]]
 ;
   %fabs = call half @llvm.fabs.f16(half %x)
   %is.finite = fcmp ueq half %fabs, 0xH7C00
   %ord = fcmp ord half %x, %x
   %and = and i1 %ord, %is.finite
   ret i1 %and
 }
 

 
 ; --------------------------------------------------------------------
 ; isnormal(x) || x == 0.0
 ; --------------------------------------------------------------------
 
 define i1 @isnormal_or_zero(half %x) #0 {
 ; CHECK-LABEL: @isnormal_or_zero(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[ISEQ:%.*]] = fcmp ord half [[X:%.*]], 0xH0000
-; CHECK-NEXT:    [[FABS:%.*]] = tail call half @llvm.fabs.f16(half [[X]])
-; CHECK-NEXT:    [[ISINF:%.*]] = fcmp ult half [[FABS]], 0xH7C00
+; CHECK-NEXT:    [[FABS:%.*]] = tail call half @llvm.fabs.f16(half [[X:%.*]])
 ; CHECK-NEXT:    [[ISNORMAL:%.*]] = fcmp uge half [[FABS]], 0xH0400
-; CHECK-NEXT:    [[AND:%.*]] = and i1 [[ISEQ]], [[ISINF]]
-; CHECK-NEXT:    [[AND1:%.*]] = and i1 [[ISNORMAL]], [[AND]]
+; CHECK-NEXT:    [[TMP0:%.*]] = fcmp olt half [[FABS]], 0xH7C00
+; CHECK-NEXT:    [[AND1:%.*]] = and i1 [[ISNORMAL]], [[TMP0]]
 ; CHECK-NEXT:    [[CMP:%.*]] = fcmp oeq half [[X]], 0xH0000
 ; CHECK-NEXT:    [[SPEC_SELECT:%.*]] = or i1 [[CMP]], [[AND1]]
 ; CHECK-NEXT:    ret i1 [[SPEC_SELECT]]
 ;
 entry:
   %iseq = fcmp ord half %x, 0xH0000
   %fabs = tail call half @llvm.fabs.f16(half %x)
   %isinf = fcmp ult half %fabs, 0xH7C00
;
   %uno = fcmp uno half %x, 0xH0000
   %or = or i1 %oge.fabs.inf, %uno
   ret i1 %or
 }
 
 define i1 @ult_fabs_eq_inf_and_ord(half %x) #0 {
 ; CHECK-LABEL: @ult_fabs_eq_inf_and_ord(
 ; CHECK-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT:    [[ULT_FABS_INF:%.*]] = fcmp ult half [[FABS]], 0xH7C00
-; CHECK-NEXT:    [[ORD:%.*]] = fcmp ord half [[X]], 0xH0000
-; CHECK-NEXT:    [[AND:%.*]] = and i1 [[ULT_FABS_INF]], [[ORD]]
-; CHECK-NEXT:    ret i1 [[AND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = fcmp olt half [[FABS]], 0xH7C00
+; CHECK-NEXT:    ret i1 [[TMP1]]
 ;
   %fabs = call half @llvm.fabs.f16(half %x)
   %ult.fabs.inf = fcmp ult half %fabs, 0xH7C00
   %ord = fcmp ord half %x, 0xH0000
   %and = and i1 %ult.fabs.inf, %ord
   ret i1 %and
 }
 
 define i1 @ult_eq_inf_and_ord(half %x) #0 {
 ; CHECK-LABEL: @ult_eq_inf_and_ord(
-; CHECK-NEXT:    [[ULT_FABS_INF:%.*]] = fcmp ult half [[X:%.*]], 0xH7C00
-; CHECK-NEXT:    [[ORD:%.*]] = fcmp ord half [[X]], 0xH0000
-; CHECK-NEXT:    [[AND:%.*]] = and i1 [[ULT_FABS_INF]], [[ORD]]
-; CHECK-NEXT:    ret i1 [[AND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = fcmp olt half [[X:%.*]], 0xH7C00
+; CHECK-NEXT:    ret i1 [[TMP1]]
 ;
   %ult.fabs.inf = fcmp ult half %x, 0xH7C00
   %ord = fcmp ord half %x, 0xH0000
   %and = and i1 %ult.fabs.inf, %ord
   ret i1 %and
 }
 
 define i1 @ult_fabs_eq_inf_or_uno(half %x) #0 {
;
   %ord = fcmp ord half %x, 0.0
   %class = or i1 %une.neg.infinity, %ord
   ret i1 %class
 }
 
 ; -> ~(nan | ninf)
 define i1 @une_neginfinity_and_ord(half %x) #0 {
 ; CHECK-LABEL: @une_neginfinity_and_ord(
-; CHECK-NEXT:    [[UNE_NEG_INFINITY:%.*]] = fcmp une half [[X:%.*]], 0xHFC00
-; CHECK-NEXT:    [[ORD:%.*]] = fcmp ord half [[X]], 0xH0000
-; CHECK-NEXT:    [[CLASS:%.*]] = and i1 [[UNE_NEG_INFINITY]], [[ORD]]
-; CHECK-NEXT:    ret i1 [[CLASS]]
+; CHECK-NEXT:    [[TMP1:%.*]] = fcmp one half [[X:%.*]], 0xHFC00
+; CHECK-NEXT:    ret i1 [[TMP1]]
 ;
   %une.neg.infinity = fcmp une half %x, 0xHFC00
   %ord = fcmp ord half %x, 0.0
   %class = and i1 %une.neg.infinity, %ord
   ret i1 %class
 }
 
 ; -> ord

llvm/test/Transforms/InstCombine/unordered-compare-and-ordered.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt -S -passes=instcombine < %s | FileCheck %s
 
 define i1 @fcmp_ord_and_uno(half %x, half %y) {
 ; CHECK-LABEL: @fcmp_ord_and_uno(
-; CHECK-NEXT:    [[ORD:%.*]] = fcmp ord half [[X:%.*]], 0xH0000
-; CHECK-NEXT:    [[UNO:%.*]] = fcmp uno half [[X]], [[Y:%.*]]
-; CHECK-NEXT:    [[AND:%.*]] = and i1 [[ORD]], [[UNO]]
-; CHECK-NEXT:    ret i1 [[AND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = fcmp ord half [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    ret i1 [[TMP1]]
 ;
   %ord = fcmp ord half %x, 0.0
   %uno = fcmp uno half %x, %y
   %and = and i1 %ord, %uno
   ret i1 %and
 }
 
 define i1 @fcmp_ord_and_ueq(half %x, half %y) {
 ; CHECK-LABEL: @fcmp_ord_and_ueq(
-; CHECK-NEXT:    [[ORD:%.*]] = fcmp ord half [[X:%.*]], 0xH0000
-; CHECK-NEXT:    [[UEQ:%.*]] = fcmp ueq half [[X]], [[Y:%.*]]
-; CHECK-NEXT:    [[AND:%.*]] = and i1 [[ORD]], [[UEQ]]
-; CHECK-NEXT:    ret i1 [[AND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = fcmp oeq half [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    ret i1 [[TMP1]]
 ;
   %ord = fcmp ord half %x, 0.0
   %ueq = fcmp ueq half %x, %y
   %and = and i1 %ord, %ueq
   ret i1 %and
 }
 
 define i1 @fcmp_ord_and_ugt(half %x, half %y) {
 ; CHECK-LABEL: @fcmp_ord_and_ugt(
-; CHECK-NEXT:    [[ORD:%.*]] = fcmp ord half [[X:%.*]], 0xH0000
-; CHECK-NEXT:    [[UGT:%.*]] = fcmp ugt half [[X]], [[Y:%.*]]
-; CHECK-NEXT:    [[AND:%.*]] = and i1 [[ORD]], [[UGT]]
-; CHECK-NEXT:    ret i1 [[AND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = fcmp ogt half [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    ret i1 [[TMP1]]
 ;
   %ord = fcmp ord half %x, 0.0
   %ugt = fcmp ugt half %x, %y
   %and = and i1 %ord, %ugt
   ret i1 %and
 }
 
 define i1 @fcmp_ord_and_uge(half %x, half %y) {
 ; CHECK-LABEL: @fcmp_ord_and_uge(
-; CHECK-NEXT:    [[ORD:%.*]] = fcmp ord half [[X:%.*]], 0xH0000
-; CHECK-NEXT:    [[UGE:%.*]] = fcmp uge half [[X]], [[Y:%.*]]
-; CHECK-NEXT:    [[AND:%.*]] = and i1 [[ORD]], [[UGE]]
-; CHECK-NEXT:    ret i1 [[AND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = fcmp oge half [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    ret i1 [[TMP1]]
 ;
   %ord = fcmp ord half %x, 0.0
   %uge = fcmp uge half %x, %y
   %and = and i1 %ord, %uge
   ret i1 %and
 }
 
 define i1 @fcmp_ord_and_ult(half %x, half %y) {
 ; CHECK-LABEL: @fcmp_ord_and_ult(
-; CHECK-NEXT:    [[ORD:%.*]] = fcmp ord half [[X:%.*]], 0xH0000
-; CHECK-NEXT:    [[ULT:%.*]] = fcmp ult half [[X]], [[Y:%.*]]
-; CHECK-NEXT:    [[AND:%.*]] = and i1 [[ORD]], [[ULT]]
-; CHECK-NEXT:    ret i1 [[AND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = fcmp olt half [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    ret i1 [[TMP1]]
 ;
   %ord = fcmp ord half %x, 0.0
   %ult = fcmp ult half %x, %y
   %and = and i1 %ord, %ult
   ret i1 %and
 }
 
 define i1 @fcmp_ord_and_ule(half %x, half %y) {
 ; CHECK-LABEL: @fcmp_ord_and_ule(
-; CHECK-NEXT:    [[ORD:%.*]] = fcmp ord half [[X:%.*]], 0xH0000
-; CHECK-NEXT:    [[ULE:%.*]] = fcmp ule half [[X]], [[Y:%.*]]
-; CHECK-NEXT:    [[AND:%.*]] = and i1 [[ORD]], [[ULE]]
-; CHECK-NEXT:    ret i1 [[AND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = fcmp ole half [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    ret i1 [[TMP1]]
 ;
   %ord = fcmp ord half %x, 0.0
   %ule = fcmp ule half %x, %y
   %and = and i1 %ord, %ule
   ret i1 %and
 }
 
 define i1 @fcmp_ord_and_une(half %x, half %y) {
 ; CHECK-LABEL: @fcmp_ord_and_une(
-; CHECK-NEXT:    [[ORD:%.*]] = fcmp ord half [[X:%.*]], 0xH0000
-; CHECK-NEXT:    [[UNE:%.*]] = fcmp une half [[X]], [[Y:%.*]]
-; CHECK-NEXT:    [[AND:%.*]] = and i1 [[ORD]], [[UNE]]
-; CHECK-NEXT:    ret i1 [[AND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = fcmp one half [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    ret i1 [[TMP1]]
 ;
   %ord = fcmp ord half %x, 0.0
   %une = fcmp une half %x, %y
   %and = and i1 %ord, %une
   ret i1 %and
 }
 
 define i1 @fcmp_ord_and_true(half %x, half %y) {
 ; CHECK-LABEL: @fcmp_ord_and_true(
 ; CHECK-NEXT:    [[UNE:%.*]] = fcmp une half [[X:%.*]], [[Y:%.*]]
 ; CHECK-NEXT:    ret i1 [[UNE]]
 ;
   %ord = fcmp true half %x, 0.0
   %une = fcmp une half %x, %y
   %and = and i1 %ord, %une
   ret i1 %and
 }
 
 define <2 x i1> @fcmp_ord_and_ueq_vector(<2 x half> %x, <2 x half> %y) {
 ; CHECK-LABEL: @fcmp_ord_and_ueq_vector(
-; CHECK-NEXT:    [[ORD:%.*]] = fcmp ord <2 x half> [[X:%.*]], zeroinitializer
-; CHECK-NEXT:    [[UEQ:%.*]] = fcmp ueq <2 x half> [[X]], [[Y:%.*]]
-; CHECK-NEXT:    [[AND:%.*]] = and <2 x i1> [[ORD]], [[UEQ]]
-; CHECK-NEXT:    ret <2 x i1> [[AND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = fcmp oeq <2 x half> [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    ret <2 x i1> [[TMP1]]
 ;
   %ord = fcmp ord <2 x half> %x, zeroinitializer
   %ueq = fcmp ueq <2 x half> %x, %y
   %and = and <2 x i1> %ord, %ueq
   ret <2 x i1> %and
 }
 
 ; Negative test
;
   %and = and i1 %ueq, %ord
   ret i1 %and
 }
 
 define i1 @fcmp_ord_and_ueq_commute1() {
 ; CHECK-LABEL: @fcmp_ord_and_ueq_commute1(
 ; CHECK-NEXT:    [[X:%.*]] = call half @foo()
 ; CHECK-NEXT:    [[Y:%.*]] = call half @foo()
-; CHECK-NEXT:    [[ORD:%.*]] = fcmp ord half [[X]], 0xH0000
-; CHECK-NEXT:    [[UEQ:%.*]] = fcmp ueq half [[X]], [[Y]]
-; CHECK-NEXT:    [[AND:%.*]] = and i1 [[ORD]], [[UEQ]]
-; CHECK-NEXT:    ret i1 [[AND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = fcmp oeq half [[X]], [[Y]]
+; CHECK-NEXT:    ret i1 [[TMP1]]
 ;
   %x = call half @foo()
   %y = call half @foo()
   %ord = fcmp ord half %x, 0.0
   %ueq = fcmp ueq half %x, %y
   %and = and i1 %ord, %ueq
   ret i1 %and
 }
 
 define i1 @fcmp_oeq_x_x_and_ult(half %x, half %y) {
 ; CHECK-LABEL: @fcmp_oeq_x_x_and_ult(
-; CHECK-NEXT:    [[ORD:%.*]] = fcmp ord half [[X:%.*]], 0xH0000
-; CHECK-NEXT:    [[ULT:%.*]] = fcmp ult half [[X]], [[Y:%.*]]
-; CHECK-NEXT:    [[AND:%.*]] = and i1 [[ORD]], [[ULT]]
-; CHECK-NEXT:    ret i1 [[AND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = fcmp olt half [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    ret i1 [[TMP1]]
 ;
   %ord = fcmp oeq half %x, %x ; noncanonical ordered
   %ult = fcmp ult half %x, %y
   %and = and i1 %ord, %ult
   ret i1 %and
 }
 
 define i1 @fcmp_ord_and_ueq_preserve_flags(half %x, half %y) {
 ; CHECK-LABEL: @fcmp_ord_and_ueq_preserve_flags(
-; CHECK-NEXT:    [[ORD:%.*]] = fcmp nsz ord half [[X:%.*]], 0xH0000
-; CHECK-NEXT:    [[UEQ:%.*]] = fcmp nsz ueq half [[X]], [[Y:%.*]]
-; CHECK-NEXT:    [[AND:%.*]] = and i1 [[ORD]], [[UEQ]]
-; CHECK-NEXT:    ret i1 [[AND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = fcmp nsz oeq half [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    ret i1 [[TMP1]]
 ;
   %ord = fcmp nsz ord half %x, 0.0
   %ueq = fcmp nsz ueq half %x, %y
   %and = and i1 %ord, %ueq
   ret i1 %and
 }
 
 define i1 @fcmp_ord_and_ueq_preserve_subset_flags0(half %x, half %y) {
 ; CHECK-LABEL: @fcmp_ord_and_ueq_preserve_subset_flags0(
-; CHECK-NEXT:    [[ORD:%.*]] = fcmp nsz ord half [[X:%.*]], 0xH0000
-; CHECK-NEXT:    [[UEQ:%.*]] = fcmp ninf nsz ueq half [[X]], [[Y:%.*]]
-; CHECK-NEXT:    [[AND:%.*]] = and i1 [[ORD]], [[UEQ]]
-; CHECK-NEXT:    ret i1 [[AND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = fcmp nsz oeq half [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    ret i1 [[TMP1]]
 ;
   %ord = fcmp nsz ord half %x, 0.0
   %ueq = fcmp ninf nsz ueq half %x, %y
   %and = and i1 %ord, %ueq
   ret i1 %and
 }
 
 define i1 @fcmp_ord_and_ueq_preserve_subset_flags1(half %x, half %y) {
 ; CHECK-LABEL: @fcmp_ord_and_ueq_preserve_subset_flags1(
-; CHECK-NEXT:    [[ORD:%.*]] = fcmp ninf nsz ord half [[X:%.*]], 0xH0000
-; CHECK-NEXT:    [[UEQ:%.*]] = fcmp nsz ueq half [[X]], [[Y:%.*]]
-; CHECK-NEXT:    [[AND:%.*]] = and i1 [[ORD]], [[UEQ]]
-; CHECK-NEXT:    ret i1 [[AND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = fcmp nsz oeq half [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    ret i1 [[TMP1]]
 ;
   %ord = fcmp ninf nsz ord half %x, 0.0
   %ueq = fcmp nsz ueq half %x, %y
   %and = and i1 %ord, %ueq
   ret i1 %and
 }
 
 define i1 @fcmp_ord_and_ueq_flags_lhs(half %x, half %y) {
 ; CHECK-LABEL: @fcmp_ord_and_ueq_flags_lhs(
-; CHECK-NEXT:    [[ORD:%.*]] = fcmp nsz ord half [[X:%.*]], 0xH0000
-; CHECK-NEXT:    [[UEQ:%.*]] = fcmp ueq half [[X]], [[Y:%.*]]
-; CHECK-NEXT:    [[AND:%.*]] = and i1 [[ORD]], [[UEQ]]
-; CHECK-NEXT:    ret i1 [[AND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = fcmp oeq half [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    ret i1 [[TMP1]]
 ;
   %ord = fcmp nsz ord half %x, 0.0
   %ueq = fcmp ueq half %x, %y
   %and = and i1 %ord, %ueq
   ret i1 %and
 }
 
 define i1 @fcmp_ord_and_ueq_flags_rhs(half %x, half %y) {
 ; CHECK-LABEL: @fcmp_ord_and_ueq_flags_rhs(
-; CHECK-NEXT:    [[ORD:%.*]] = fcmp ord half [[X:%.*]], 0xH0000
-; CHECK-NEXT:    [[UEQ:%.*]] = fcmp nsz ueq half [[X]], [[Y:%.*]]
-; CHECK-NEXT:    [[AND:%.*]] = and i1 [[ORD]], [[UEQ]]
-; CHECK-NEXT:    ret i1 [[AND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = fcmp oeq half [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    ret i1 [[TMP1]]
 ;
   %ord = fcmp ord half %x, 0.0
   %ueq = fcmp nsz ueq half %x, %y
   %and = and i1 %ord, %ueq
   ret i1 %and
 }
 
 ; Can ignore fabs and fneg
 define i1 @fcmp_ord_and_fabs_ueq(half %x, half %y) {
 ; CHECK-LABEL: @fcmp_ord_and_fabs_ueq(
 ; CHECK-NEXT:    [[FABS_X:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT:    [[ORD:%.*]] = fcmp ord half [[X]], 0xH0000
-; CHECK-NEXT:    [[UEQ:%.*]] = fcmp ueq half [[FABS_X]], [[Y:%.*]]
-; CHECK-NEXT:    [[AND:%.*]] = and i1 [[ORD]], [[UEQ]]
-; CHECK-NEXT:    ret i1 [[AND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = fcmp oeq half [[FABS_X]], [[Y:%.*]]
+; CHECK-NEXT:    ret i1 [[TMP1]]
 ;
   %fabs.x = call half @llvm.fabs.f16(half %x)
   %ord = fcmp ord half %x, 0.0
   %ueq = fcmp ueq half %fabs.x, %y
   %and = and i1 %ord, %ueq
   ret i1 %and
 }
 
 define i1 @fcmp_ord_fabs_and_ueq(half %x, half %y) {
 ; CHECK-LABEL: @fcmp_ord_fabs_and_ueq(
-; CHECK-NEXT:    [[ORD:%.*]] = fcmp ord half [[X:%.*]], 0xH0000
-; CHECK-NEXT:    [[UEQ:%.*]] = fcmp ueq half [[X]], [[Y:%.*]]
-; CHECK-NEXT:    [[AND:%.*]] = and i1 [[ORD]], [[UEQ]]
-; CHECK-NEXT:    ret i1 [[AND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = fcmp oeq half [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    ret i1 [[TMP1]]
 ;
   %fabs.x = call half @llvm.fabs.f16(half %x)
   %ord = fcmp ord half %fabs.x, 0.0
   %ueq = fcmp ueq half %x, %y
   %and = and i1 %ord, %ueq
   ret i1 %and
 }
 
;
   %ueq = fcmp ueq half %y, %fabs.x
   %and = and i1 %ueq, %ord
   ret i1 %and
 }
 
 define <2 x i1> @fcmp_ord_and_fabs_ueq_vector(<2 x half> %x, <2 x half> %y) {
 ; CHECK-LABEL: @fcmp_ord_and_fabs_ueq_vector(
 ; CHECK-NEXT:    [[FABS_X:%.*]] = call <2 x half> @llvm.fabs.v2f16(<2 x half> [[X:%.*]])
-; CHECK-NEXT:    [[ORD:%.*]] = fcmp ord <2 x half> [[X]], zeroinitializer
-; CHECK-NEXT:    [[UEQ:%.*]] = fcmp ueq <2 x half> [[FABS_X]], [[Y:%.*]]
-; CHECK-NEXT:    [[AND:%.*]] = and <2 x i1> [[ORD]], [[UEQ]]
-; CHECK-NEXT:    ret <2 x i1> [[AND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = fcmp oeq <2 x half> [[FABS_X]], [[Y:%.*]]
+; CHECK-NEXT:    ret <2 x i1> [[TMP1]]
 ;
   %fabs.x = call <2 x half> @llvm.fabs.v2f16(<2 x half> %x)
   %ord = fcmp ord <2 x half> %x, zeroinitializer
   %ueq = fcmp ueq <2 x half> %fabs.x, %y
   %and = and <2 x i1> %ord, %ueq
   ret <2 x i1> %and
 }
 
 define i1 @fcmp_ord_fabs_and_fabs_ueq(half %x, half %y) {
 ; CHECK-LABEL: @fcmp_ord_fabs_and_fabs_ueq(
 ; CHECK-NEXT:    [[FABS_X:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT:    [[ORD:%.*]] = fcmp ord half [[X]], 0xH0000
-; CHECK-NEXT:    [[UEQ:%.*]] = fcmp ueq half [[FABS_X]], [[Y:%.*]]
-; CHECK-NEXT:    [[AND:%.*]] = and i1 [[ORD]], [[UEQ]]
-; CHECK-NEXT:    ret i1 [[AND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = fcmp oeq half [[FABS_X]], [[Y:%.*]]
+; CHECK-NEXT:    ret i1 [[TMP1]]
 ;
   %fabs.x = call half @llvm.fabs.f16(half %x)
   %ord = fcmp ord half %fabs.x, 0.0
   %ueq = fcmp ueq half %fabs.x, %y
   %and = and i1 %ord, %ueq
   ret i1 %and
 }
 
 define i1 @fcmp_ord_and_fneg_ueq(half %x, half %y) {
 ; CHECK-LABEL: @fcmp_ord_and_fneg_ueq(
 ; CHECK-NEXT:    [[FNEG_X:%.*]] = fneg half [[X:%.*]]
-; CHECK-NEXT:    [[ORD:%.*]] = fcmp ord half [[X]], 0xH0000
-; CHECK-NEXT:    [[UEQ:%.*]] = fcmp ueq half [[FNEG_X]], [[Y:%.*]]
-; CHECK-NEXT:    [[AND:%.*]] = and i1 [[ORD]], [[UEQ]]
-; CHECK-NEXT:    ret i1 [[AND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = fcmp oeq half [[FNEG_X]], [[Y:%.*]]
+; CHECK-NEXT:    ret i1 [[TMP1]]
 ;
   %fneg.x = fneg half %x
   %ord = fcmp ord half %x, 0.0
   %ueq = fcmp ueq half %fneg.x, %y
   %and = and i1 %ord, %ueq
   ret i1 %and
 }
 
 define i1 @fcmp_ord_fneg_and_ueq(half %x, half %y) {
 ; CHECK-LABEL: @fcmp_ord_fneg_and_ueq(
-; CHECK-NEXT:    [[ORD:%.*]] = fcmp ord half [[X:%.*]], 0xH0000
-; CHECK-NEXT:    [[UEQ:%.*]] = fcmp ueq half [[X]], [[Y:%.*]]
-; CHECK-NEXT:    [[AND:%.*]] = and i1 [[ORD]], [[UEQ]]
-; CHECK-NEXT:    ret i1 [[AND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = fcmp oeq half [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    ret i1 [[TMP1]]
 ;
   %fneg.x = fneg half %x
   %ord = fcmp ord half %fneg.x, 0.0
   %ueq = fcmp ueq half %x, %y
   %and = and i1 %ord, %ueq
   ret i1 %and
 }
 
 define i1 @fcmp_ord_fneg_and_fneg_ueq(half %x, half %y) {
 ; CHECK-LABEL: @fcmp_ord_fneg_and_fneg_ueq(
 ; CHECK-NEXT:    [[FNEG_X:%.*]] = fneg half [[X:%.*]]
-; CHECK-NEXT:    [[ORD:%.*]] = fcmp ord half [[X]], 0xH0000
-; CHECK-NEXT:    [[UEQ:%.*]] = fcmp ueq half [[FNEG_X]], [[Y:%.*]]
-; CHECK-NEXT:    [[AND:%.*]] = and i1 [[ORD]], [[UEQ]]
-; CHECK-NEXT:    ret i1 [[AND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = fcmp oeq half [[FNEG_X]], [[Y:%.*]]
+; CHECK-NEXT:    ret i1 [[TMP1]]
 ;
   %fneg.x = fneg half %x
   %ord = fcmp ord half %fneg.x, 0.0
   %ueq = fcmp ueq half %fneg.x, %y
   %and = and i1 %ord, %ueq
   ret i1 %and
 }
 
 define i1 @fcmp_ord_and_fneg_fabs_ueq(half %x, half %y) {
 ; CHECK-LABEL: @fcmp_ord_and_fneg_fabs_ueq(
 ; CHECK-NEXT:    [[FABS_X:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
 ; CHECK-NEXT:    [[FNEG_FABS_X:%.*]] = fneg half [[FABS_X]]
-; CHECK-NEXT:    [[ORD:%.*]] = fcmp ord half [[X]], 0xH0000
-; CHECK-NEXT:    [[UEQ:%.*]] = fcmp ueq half [[FNEG_FABS_X]], [[Y:%.*]]
-; CHECK-NEXT:    [[AND:%.*]] = and i1 [[ORD]], [[UEQ]]
-; CHECK-NEXT:    ret i1 [[AND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = fcmp oeq half [[FNEG_FABS_X]], [[Y:%.*]]
+; CHECK-NEXT:    ret i1 [[TMP1]]
 ;
   %fabs.x = call half @llvm.fabs.f16(half %x)
   %fneg.fabs.x = fneg half %fabs.x
   %ord = fcmp ord half %x, 0.0
   %ueq = fcmp ueq half %fneg.fabs.x, %y
   %and = and i1 %ord, %ueq
   ret i1 %and
 }
 
 define i1 @fcmp_ord_and_copysign_ueq(half %x, half %y, half %z) {
 ; CHECK-LABEL: @fcmp_ord_and_copysign_ueq(
 ; CHECK-NEXT:    [[COPYSIGN_X_Y:%.*]] = call half @llvm.copysign.f16(half [[X:%.*]], half [[Z:%.*]])
-; CHECK-NEXT:    [[ORD:%.*]] = fcmp ord half [[X]], 0xH0000
-; CHECK-NEXT:    [[UEQ:%.*]] = fcmp ueq half [[COPYSIGN_X_Y]], [[Y:%.*]]
-; CHECK-NEXT:    [[AND:%.*]] = and i1 [[ORD]], [[UEQ]]
-; CHECK-NEXT:    ret i1 [[AND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = fcmp oeq half [[COPYSIGN_X_Y]], [[Y:%.*]]
+; CHECK-NEXT:    ret i1 [[TMP1]]
 ;
   %copysign.x.y = call half @llvm.copysign.f16(half %x, half %z)
   %ord = fcmp ord half %x, 0.0
   %ueq = fcmp ueq half %copysign.x.y, %y
   %and = and i1 %ord, %ueq
   ret i1 %and
 }
 
 define i1 @fcmp_copysign_ord_and_ueq(half %x, half %y, half %z) {
 ; CHECK-LABEL: @fcmp_copysign_ord_and_ueq(
-; CHECK-NEXT:    [[COPYSIGN_X_Y:%.*]] = call half @llvm.copysign.f16(half [[X:%.*]], half [[Z:%.*]])
-; CHECK-NEXT:    [[ORD:%.*]] = fcmp ord half [[COPYSIGN_X_Y]], 0xH0000
-; CHECK-NEXT:    [[UEQ:%.*]] = fcmp ueq half [[X]], [[Y:%.*]]
-; CHECK-NEXT:    [[AND:%.*]] = and i1 [[ORD]], [[UEQ]]
-; CHECK-NEXT:    ret i1 [[AND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = fcmp oeq half [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    ret i1 [[TMP1]]
 ;
   %copysign.x.y = call half @llvm.copysign.f16(half %x, half %z)
   %ord = fcmp ord half %copysign.x.y, 0.0
   %ueq = fcmp ueq half %x, %y
   %and = and i1 %ord, %ueq
   ret i1 %and
 }
 
 define i1 @fcmp_ord_and_copysign_ueq_commute(half %x, half %y, half %z) {
 ; CHECK-LABEL: @fcmp_ord_and_copysign_ueq_commute(
 ; CHECK-NEXT:    [[COPYSIGN_X_Y:%.*]] = call half @llvm.copysign.f16(half [[X:%.*]], half [[Z:%.*]])
-; CHECK-NEXT:    [[ORD:%.*]] = fcmp ord half [[X]], 0xH0000
-; CHECK-NEXT:    [[UEQ:%.*]] = fcmp ueq half [[COPYSIGN_X_Y]], [[Y:%.*]]
-; CHECK-NEXT:    [[AND:%.*]] = and i1 [[ORD]], [[UEQ]]
-; CHECK-NEXT:    ret i1 [[AND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = fcmp oeq half [[COPYSIGN_X_Y]], [[Y:%.*]]
+; CHECK-NEXT:    ret i1 [[TMP1]]
 ;
   %copysign.x.y = call half @llvm.copysign.f16(half %x, half %z)
   %ord = fcmp ord half %x, 0.0
   %ueq = fcmp ueq half %y, %copysign.x.y
   %and = and i1 %ord, %ueq
   ret i1 %and
 }
 
 define i1 @fcmp_ord_and_copysign_fneg_ueq(half %x, half %y, half %z) {
 ; CHECK-LABEL: @fcmp_ord_and_copysign_fneg_ueq(
 ; CHECK-NEXT:    [[COPYSIGN_X_Y:%.*]] = call half @llvm.copysign.f16(half [[X:%.*]], half [[Z:%.*]])
-; CHECK-NEXT:    [[ORD:%.*]] = fcmp ord half [[X]], 0xH0000
-; CHECK-NEXT:    [[UEQ:%.*]] = fcmp ueq half [[COPYSIGN_X_Y]], [[Y:%.*]]
-; CHECK-NEXT:    [[AND:%.*]] = and i1 [[ORD]], [[UEQ]]
-; CHECK-NEXT:    ret i1 [[AND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = fcmp oeq half [[COPYSIGN_X_Y]], [[Y:%.*]]
+; CHECK-NEXT:    ret i1 [[TMP1]]
 ;
   %x.fneg = fneg half %x
   %copysign.x.y = call half @llvm.copysign.f16(half %x.fneg, half %z)
   %ord = fcmp ord half %x, 0.0
   %ueq = fcmp ueq half %copysign.x.y, %y
   %and = and i1 %ord, %ueq
   ret i1 %and
 }