AMDGPU: Fix creating illegal f16 fp_class

[arsenm]

Summary

We were missing legality checks. The device library build was broken
for targets without f16 support. Technically the first pattern isn't
tested by this patch; it only triggers with the isBeforeLegalize check
in performAndCombine removed. I'm not sure how to trick this into
appearing post-legalization.

[arsenm]

c08d55623d209070883b420e70b070009d447bca

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

SDValue SITargetLowering::performAndCombine(SDNode *N,
   // (and (fcmp ord x, x), (fcmp une (fabs x), inf)) ->
   // fp_class x, ~(s_nan | q_nan | n_infinity | p_infinity)
   if (LHS.getOpcode() == ISD::SETCC && RHS.getOpcode() == ISD::SETCC) {
     ISD::CondCode LCC = cast<CondCodeSDNode>(LHS.getOperand(2))->get();
     ISD::CondCode RCC = cast<CondCodeSDNode>(RHS.getOperand(2))->get();
 
     SDValue X = LHS.getOperand(0);
     SDValue Y = RHS.getOperand(0);
-    if (Y.getOpcode() != ISD::FABS || Y.getOperand(0) != X)
+    if (Y.getOpcode() != ISD::FABS || Y.getOperand(0) != X ||
+        !isTypeLegal(X.getValueType()))
       return SDValue();
 
     if (LCC == ISD::SETO) {
       if (X != LHS.getOperand(1))
         return SDValue();
 
       if (RCC == ISD::SETUNE) {
         const ConstantFPSDNode *C1 = dyn_cast<ConstantFPSDNode>(RHS.getOperand(1));
if ((CC == ISD::SETEQ || CC == ISD::SETNE) &&
         return DAG.getNode(ISD::XOR, SL, MVT::i1, LHS.getOperand(0),
                            DAG.getConstant(-1, SL, MVT::i1));
       if ((CF == CRHSVal && CC == ISD::SETNE) ||
           (CT == CRHSVal && CC == ISD::SETEQ))
         return LHS.getOperand(0);
     }
   }
 
-  if (VT != MVT::f32 && VT != MVT::f64 && (Subtarget->has16BitInsts() &&
-                                           VT != MVT::f16))
+  if (VT != MVT::f32 && VT != MVT::f64 &&
+      (!Subtarget->has16BitInsts() || VT != MVT::f16))
     return SDValue();
 
   // Match isinf/isfinite pattern
   // (fcmp oeq (fabs x), inf) -> (fp_class x, (p_infinity | n_infinity))
   // (fcmp one (fabs x), inf) -> (fp_class x,
   // (p_normal | n_normal | p_subnormal | n_subnormal | p_zero | n_zero)
   if ((CC == ISD::SETOEQ || CC == ISD::SETONE) && LHS.getOpcode() == ISD::FABS) {
     const ConstantFPSDNode *CRHS = dyn_cast<ConstantFPSDNode>(RHS);

llvm/test/CodeGen/AMDGPU/fp-classify.ll

define amdgpu_kernel void @test_not_isfinite_pattern_4_wrong_ord_test(i32 addrspace(1)* nocapture %out, float %x, [8 x i32], float %y) #0 {
   %x.fabs = tail call float @llvm.fabs.f32(float %x) #1
   %ninf = fcmp one float %x.fabs, 0x7FF0000000000000
   %and = and i1 %ord, %ninf
   %ext = zext i1 %and to i32
   store i32 %ext, i32 addrspace(1)* %out, align 4
   ret void
 }
 
+; GCN-LABEL: {{^}}test_isinf_pattern_f16:
+; SI-DAG: s_mov_b32 [[INF:s[0-9]+]], 0x7f800000
+; SI-DAG: v_cvt_f32_f16_e64 [[CVT:v[0-9]+]], |s{{[0-9]+}}|
+; SI: v_cmp_eq_f32_e32 vcc, [[INF]], [[CVT]]
+; SI-NEXT: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1, vcc
+
+; VI: v_mov_b32_e32 [[MASK:v[0-9]+]], 0x204{{$}}
+; VI: v_cmp_class_f16_e32 vcc, s{{[0-9]+}}, [[MASK]]
+; VI-NOT: v_cmp
+
+; GCN: s_endpgm
+define amdgpu_kernel void @test_isinf_pattern_f16(i32 addrspace(1)* nocapture %out, half %x) #0 {
+  %fabs = tail call half @llvm.fabs.f16(half %x) #1
+  %cmp = fcmp oeq half %fabs, 0xH7C00
+  %ext = zext i1 %cmp to i32
+  store i32 %ext, i32 addrspace(1)* %out, align 4
+  ret void
+}
+
+; GCN-LABEL: {{^}}test_isfinite_pattern_0_f16:
+; SI-DAG: s_movk_i32 [[MASK:s[0-9]+]], 0x1f8
+; SI-DAG: v_cvt_f32_f16_e32 [[CVT:v[0-9]+]], s{{[0-9]+}}
+; SI: v_cmp_class_f32_e64 [[CLASS:s\[[0-9]+:[0-9]+\]]], [[CVT]], [[MASK]]
+; SI-NEXT: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1, [[CLASS]]
+
+; VI-NOT: v_cmp
+; VI: v_mov_b32_e32 [[MASK:v[0-9]+]], 0x1f8{{$}}
+; VI: v_cmp_class_f16_e32 vcc, s{{[0-9]+}}, [[MASK]]
+; VI-NOT: v_cmp
+
+; GCN: s_endpgm
+define amdgpu_kernel void @test_isfinite_pattern_0_f16(i32 addrspace(1)* nocapture %out, half %x) #0 {
+  %ord = fcmp ord half %x, 0.0
+  %x.fabs = tail call half @llvm.fabs.f16(half %x) #1
+  %ninf = fcmp une half %x.fabs, 0xH7C00
+  %and = and i1 %ord, %ninf
+  %ext = zext i1 %and to i32
+  store i32 %ext, i32 addrspace(1)* %out, align 4
+  ret void
+}
+
+; GCN-LABEL: {{^}}test_isfinite_pattern_4_f16:
+; SI-DAG: s_movk_i32 [[MASK:s[0-9]+]], 0x1f8
+; SI-DAG: v_cvt_f32_f16_e32 [[CVT:v[0-9]+]], s{{[0-9]+}}
+; SI: v_cmp_class_f32_e64 [[CLASS:s\[[0-9]+:[0-9]+\]]], [[CVT]], [[MASK]]
+; SI-NEXT: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1, [[CLASS]]
+
+; VI-DAG: s_load_dword [[X:s[0-9]+]]
+; VI-DAG: v_mov_b32_e32 [[MASK:v[0-9]+]], 0x1f8
+; VI: v_cmp_class_f16_e32 vcc, [[X]], [[MASK]]
+; VI: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1, vcc
+define amdgpu_kernel void @test_isfinite_pattern_4_f16(i32 addrspace(1)* nocapture %out, half %x) #0 {
+  %ord = fcmp ord half %x, 0.0
+  %x.fabs = tail call half @llvm.fabs.f16(half %x) #1
+  %ninf = fcmp one half %x.fabs, 0xH7C00
+  %and = and i1 %ord, %ninf
+  %ext = zext i1 %and to i32
+  store i32 %ext, i32 addrspace(1)* %out, align 4
+  ret void
+}
+
+declare half @llvm.fabs.f16(half) #1
+
 attributes #0 = { nounwind }
 attributes #1 = { nounwind readnone }