[BOLT][AArch64] Handle adrp+ld64 linker relaxations

[yota9]

Summary

Linker might relax adrp + ldr got address loading to adrp + add for
local non-preemptible symbols (e.g. hidden/protected symbols in
executable). As usually linker doesn't change relocations properly after
relaxation, so we have to handle such cases by ourselves. To do that
during relocations reading we change LD64 reloc to ADD if instruction
mismatch found and introduce FixRelaxationPass that searches for ADRP+ADD
pairs and after performing some checks we're replacing ADRP target symbol
to already fixed ADDs one.

Vladislav Khmelevsky,
Advanced Software Technology Lab, Huawei

[yota9]

Gentle ping @rafaelauler

bolt/lib/Passes/FixRelaxationPass.cpp

60

@rafaelauler To be honest I'm a bit confused, since sometimes I had a problems in the past within parallel execution of other passes. But it seems to be safe here, is it? I should probably make it parallel

[yota9]

2 weeks passed, gentle ping :)

[maksfb]

@yota9, sorry for the delay. Rafael is on vacation. I took a quick peek at aarch64 lld, and it handles more relaxations than just ADRP/LDR, e.g. TLS-specific sequences. Do you plan to support those in the future?

In general, the pass looks fine. Ideally, we should fix such discrepancies as early in the pipeline as possible, i.e. during disassembly so that --print-disasm output looks correct. But this clearly requires scanning forward, which complicates things. Still, you can check if the next relocation doesn't match the instruction when you see a relaxable ADRP candidate. What do you think?

To speed things up with the current approach, you can detect functions with relaxable relocations while reading relocs, mark functions that need fixes, and only run the pass on them.

Please run spellcheck on the summary.

bolt/lib/Passes/FixRelaxationPass.cpp

60

Since you are not modifying MCContext, it should be thread-safe. You can run "valgrind --tool=helgrind ..." or thread sanitizer for extra validation.

bolt/lib/Rewrite/RewriteInstance.cpp

2557–2558

Can we use __BOLT_ prefix for the internally-created symbol?

bolt/test/AArch64/got-ld64-relaxation.test

2

Does it make sense to generate a test case with lld similar to x86 GOTPCRELX test in D126747?

[yota9]

Thank you for review @maksfb and sorry for long response too.
We are now supporting most of them I think, currently every relaxation is handled in skipRelocationProcessAArch64. As for pure TLS ones we don't have to support them since we do not support TLS relocations and don't handle TLS sections in BOLT for now.

Ideally, we should fix such discrepancies as early in the pipeline as possible

I'm absolutely agree with this, but currently I don't see how to do it at relocation-handling stage. We need to handle relocations, get instruction opcode & etc, I expect the code to be very messy if we would do that. Although I don't really like the idea of the separate pass too, but probably it is the only way currently :(

To speed things up with the current approach, you can detect functions with relaxable relocations while reading relocs, mark functions that need fixes, and only run the pass on them.

It is true, but I don't really want to introduce new BF variables here.. Ideally we might make some bit mask values for such purposes, but for now I think it is ok to use it as-is.

bolt/lib/Passes/FixRelaxationPass.cpp

60

It seems to be no problem to run this pass in parallel :)

bolt/lib/Rewrite/RewriteInstance.cpp

2557–2558

Sure :)

bolt/test/AArch64/got-ld64-relaxation.test

2

The thing is that the linker will relax it to the adr + nop due to small size of the final binary. Such a case is already handled in skipRelocationProcessAArch64, but for adrp+add case it is better to use pre-built binary

[yota9]

Address comments

[maksfb]

LGTM

bolt/test/AArch64/got-ld64-relaxation.test

2

You can make the binary artificially bigger with .zero/.skip directives.

[yota9]

bolt/test/AArch64/got-ld64-relaxation.test

2

Well you're right, I was thinking about rept one. Usually I won't use it since it is quite slow and I'm not sure how big binary is OK to use in CI, but in this case it is just 1MB, so it is probably fine to use here.. Also a greater number of bytes really slows down the build. But again I think 1MB is good-enough limit to use in such tests..

[yota9]

Replace test

[yota9]

Add lld relax option

[yota9]

It seems to be that CI prebuilt lld is a bit out of date and does not support --relax option. I may remove this since it is the default, although I think it is probably good to have one. What do you think @Amir ?

[Amir]

In D138097#4007915, @yota9 wrote:

It seems to be that CI prebuilt lld is a bit out of date and does not support --relax option. I may remove this since it is the default, although I think it is probably good to have one. What do you think @Amir ?

Pre-merge checks are managed by Google folks in a separate repo. I can submit a PR to update LLVM version used in pre-merge checks but it'll take me a while (don't have docker-enabled machine readily available to test).

[Amir]

https://github.com/google/llvm-premerge-checks/pull/429

[yota9]

Thanks @Amir ! For now I would probably just remove this option, I don't think it is really necessary to be honest :)

[yota9]

The CI lld does not support this relaxation for now, revert test to prebuilt blob.

bolt/include/bolt/Core/MCPlusBuilder.h

virtual uint64_t matchLinkerVeneer(InstructionIterator Begin,
                                      InstructionIterator End, uint64_t Address,
                                      const MCInst &CurInst,
                                      MCInst *&TargetHiBits,
                                      MCInst *&TargetLowBits,
                                      uint64_t &Target) const {
     llvm_unreachable("not implemented");
   }
 
+  virtual bool matchAdrpAddPair(const MCInst &Adrp, const MCInst &Add) const {
+    llvm_unreachable("not implemented");
+    return false;
+  }
+
   virtual int getShortJmpEncodingSize() const {
     llvm_unreachable("not implemented");
   }
 
   virtual int getUncondBranchEncodingSize() const {
     llvm_unreachable("not implemented");
     return 0;
   }

bolt/include/bolt/Core/Relocation.h

struct Relocation {
   static size_t getSizeForType(uint64_t Type);
 
   /// Return size of this relocation.
   size_t getSize() const { return getSizeForType(Type); }
 
   /// Skip relocations that we don't want to handle in BOLT
   static bool skipRelocationType(uint64_t Type);
 
-  /// Handle special cases when relocation should not be processed by BOLT
-  static bool skipRelocationProcess(uint64_t Type, uint64_t Contents);
+  /// Handle special cases when relocation should not be processed by BOLT or
+  /// change relocation \p Type to proper one before continuing if \p Contents
+  /// and \P Type mismatch occured.
+  static bool skipRelocationProcess(uint64_t &Type, uint64_t Contents);
 
   // Adjust value depending on relocation type (make it PC relative or not)
   static uint64_t adjustValue(uint64_t Type, uint64_t Value,
                               uint64_t PC);
 
   /// Extract current relocated value from binary contents. This is used for
   /// RISC architectures where values are encoded in specific bits depending
   /// on the relocation value. For X86, we limit to sign extending the value

bolt/include/bolt/Passes/FixRelaxationPass.h

+//===- bolt/Passes/ADRRelaxationPass.h --------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file declares the FixRelaxations class, which locates instructions with
+// wrong targets and fixes them. Such problems usually occures when linker
+// relaxes (changes) instructions, but doesn't fix relocations types properly
+// for them.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef BOLT_PASSES_FIXRELAXATIONPASS_H
+#define BOLT_PASSES_FIXRELAXATIONPASS_H
+
+#include "bolt/Passes/BinaryPasses.h"
+
+namespace llvm {
+namespace bolt {
+
+class FixRelaxations : public BinaryFunctionPass {
+  void runOnFunction(BinaryFunction &Function);
+
+public:
+  explicit FixRelaxations(const cl::opt<bool> &PrintPass)
+      : BinaryFunctionPass(PrintPass) {}
+
+  const char *getName() const override { return "fix-relaxations"; }
+
+  /// Pass entry point
+  void runOnFunctions(BinaryContext &BC) override;
+};
+
+} // namespace bolt
+} // namespace llvm
+
+#endif

bolt/include/bolt/Rewrite/RewriteInstance.h

private:
   /// Make .eh_frame section relocatable.
   void relocateEHFrameSection();
 
   /// Analyze relocation \p Rel.
   /// Return true if the relocation was successfully processed, false otherwise.
   /// The \p SymbolName, \p SymbolAddress, \p Addend and \p ExtractedValue
   /// parameters will be set on success. The \p Skip argument indicates
   /// that the relocation was analyzed, but it must not be processed.
-  bool analyzeRelocation(const object::RelocationRef &Rel, uint64_t RType,
+  bool analyzeRelocation(const object::RelocationRef &Rel, uint64_t &RType,
                          std::string &SymbolName, bool &IsSectionRelocation,
                          uint64_t &SymbolAddress, int64_t &Addend,
                          uint64_t &ExtractedValue, bool &Skip) const;
 
   /// Rewrite non-allocatable sections with modifications.
   void rewriteNoteSections();
 
   /// Write .eh_frame_hdr.

bolt/lib/Core/Relocation.cpp

 }
 
 bool skipRelocationTypeX86(uint64_t Type) { return Type == ELF::R_X86_64_NONE; }
 
 bool skipRelocationTypeAArch64(uint64_t Type) {
   return Type == ELF::R_AARCH64_NONE || Type == ELF::R_AARCH64_LD_PREL_LO19;
 }
 
-bool skipRelocationProcessX86(uint64_t Type, uint64_t Contents) {
+bool skipRelocationProcessX86(uint64_t &Type, uint64_t Contents) {
   return false;
 }
 
-bool skipRelocationProcessAArch64(uint64_t Type, uint64_t Contents) {
+bool skipRelocationProcessAArch64(uint64_t &Type, uint64_t Contents) {
   auto IsMov = [](uint64_t Contents) -> bool {
     // The bits 28-23 are 0b100101
     return (Contents & 0x1f800000) == 0x12800000;
   };
 
   auto IsB = [](uint64_t Contents) -> bool {
     // The bits 31-26 are 0b000101
     return (Contents & 0xfc000000) == 0x14000000;
   };
 
   auto IsAdr = [](uint64_t Contents) -> bool {
     // The bits 31-24 are 0b0xx10000
     return (Contents & 0x9f000000) == 0x10000000;
   };
 
+  auto IsAddImm = [](uint64_t Contents) -> bool {
+    // The bits 30-23 are 0b00100010
+    return (Contents & 0x7F800000) == 0x11000000;
+  };
+
   auto IsNop = [](uint64_t Contents) -> bool { return Contents == 0xd503201f; };
 
   // The linker might eliminate the instruction and replace it with NOP, ignore
   if (IsNop(Contents))
     return true;
 
+  // The linker might relax ADRP+LDR instruction sequence for loading symbol
+  // address from GOT table to ADRP+ADD sequence that would point to the
+  // binary-local symbol. Change relocation type in order to process it right.
+  if (Type == ELF::R_AARCH64_LD64_GOT_LO12_NC && IsAddImm(Contents)) {
+    Type = ELF::R_AARCH64_ADD_ABS_LO12_NC;
+    return false;
+  }
+
   // The linker might perform TLS relocations relaxations, such as
   // changed TLS access model (e.g. changed global dynamic model
   // to initial exec), thus changing the instructions. The static
   // relocations might be invalid at this point and we might no
   // need to proccess these relocations anymore.
   // More information could be found by searching
   // elfNN_aarch64_tls_relax in bfd
   switch (Type) {

 }
 
 bool Relocation::skipRelocationType(uint64_t Type) {
   if (Arch == Triple::aarch64)
     return skipRelocationTypeAArch64(Type);
   return skipRelocationTypeX86(Type);
 }
 
-bool Relocation::skipRelocationProcess(uint64_t Type, uint64_t Contents) {
+bool Relocation::skipRelocationProcess(uint64_t &Type, uint64_t Contents) {
   if (Arch == Triple::aarch64)
     return skipRelocationProcessAArch64(Type, Contents);
   return skipRelocationProcessX86(Type, Contents);
 }
 
 uint64_t Relocation::adjustValue(uint64_t Type, uint64_t Value,
                                  uint64_t PC) {
   if (Arch == Triple::aarch64)

bolt/lib/Passes/CMakeLists.txt

 add_llvm_library(LLVMBOLTPasses
   ADRRelaxationPass.cpp
   Aligner.cpp
   AllocCombiner.cpp
   AsmDump.cpp
   BinaryPasses.cpp
   BinaryFunctionCallGraph.cpp
   CMOVConversion.cpp
   CacheMetrics.cpp
   CallGraph.cpp
   CallGraphWalker.cpp
   DataflowAnalysis.cpp
   DataflowInfoManager.cpp
   FrameAnalysis.cpp
   FrameOptimizer.cpp
+  FixRelaxationPass.cpp
   HFSort.cpp
   HFSortPlus.cpp
   Hugify.cpp
   IdenticalCodeFolding.cpp
   IndirectCallPromotion.cpp
   Inliner.cpp
   Instrumentation.cpp
   JTFootprintReduction.cpp

bolt/lib/Passes/FixRelaxationPass.cpp

+#include "bolt/Passes/FixRelaxationPass.h"
+#include "bolt/Core/ParallelUtilities.h"
+
+using namespace llvm;
+
+namespace llvm {
+namespace bolt {
+
+// This function finds ADRP+ADD instruction sequences that originally before
+// linker relaxations were ADRP+LDR. We've modified LDR/ADD relocation properly
+// during relocation reading, so its targeting right symbol. As for ADRP its
+// target is wrong before this pass since we won't be able to recognize and
+// properly change R_AARCH64_ADR_GOT_PAGE relocation to
+// R_AARCH64_ADR_PREL_PG_HI21 during relocation reading. Now we're searching for
+// ADRP+ADD sequences, checking that ADRP points to the GOT-table symbol and the
+// target of ADD is another symbol. When found change ADRP symbol reference to
+// the ADDs one.
+void FixRelaxations::runOnFunction(BinaryFunction &BF) {
+  BinaryContext &BC = BF.getBinaryContext();
+  for (BinaryBasicBlock &BB : BF) {
+    for (auto II = BB.begin(); II != BB.end(); ++II) {
+      MCInst &Adrp = *II;
+      if (BC.MIB->isPseudo(Adrp) || !BC.MIB->isADRP(Adrp))
+        continue;
+
+      const MCSymbol *AdrpSymbol = BC.MIB->getTargetSymbol(Adrp);
+      if (!AdrpSymbol || AdrpSymbol->getName() != "__BOLT_got_zero")
+        continue;
+
+      auto NextII = std::next(II);
+      if (NextII == BB.end())
+        continue;
+
+      const MCInst &Add = *NextII;
+      if (!BC.MIB->matchAdrpAddPair(Adrp, Add))
+        continue;
+
+      const MCSymbol *Symbol = BC.MIB->getTargetSymbol(Add);
+      if (!Symbol || AdrpSymbol == Symbol)
+        continue;
+
+      const int64_t Addend = BC.MIB->getTargetAddend(Add);
+      BC.MIB->setOperandToSymbolRef(Adrp, /*OpNum*/ 1, Symbol, Addend,
+                                    BC.Ctx.get(), ELF::R_AARCH64_NONE);
+    }
+  }
+}
+
+void FixRelaxations::runOnFunctions(BinaryContext &BC) {
+  if (!BC.isAArch64() || !BC.HasRelocations)
+    return;
+
+  ParallelUtilities::WorkFuncTy WorkFun = [&](BinaryFunction &BF) {
+    runOnFunction(BF);
+  };
+
+  ParallelUtilities::runOnEachFunction(
+      BC, ParallelUtilities::SchedulingPolicy::SP_INST_LINEAR, WorkFun, nullptr,
+      "FixRelaxations");
+}
+
+} // namespace bolt
+} // namespace llvm

bolt/lib/Rewrite/BinaryPassManager.cpp

 //===- bolt/Rewrite/BinaryPassManager.cpp - Binary-level pass manager -----===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #include "bolt/Rewrite/BinaryPassManager.h"
 #include "bolt/Passes/ADRRelaxationPass.h"
 #include "bolt/Passes/Aligner.h"
 #include "bolt/Passes/AllocCombiner.h"
 #include "bolt/Passes/AsmDump.h"
 #include "bolt/Passes/CMOVConversion.h"
+#include "bolt/Passes/FixRelaxationPass.h"
 #include "bolt/Passes/FrameOptimizer.h"
 #include "bolt/Passes/Hugify.h"
 #include "bolt/Passes/IdenticalCodeFolding.h"
 #include "bolt/Passes/IndirectCallPromotion.h"
 #include "bolt/Passes/Inliner.h"
 #include "bolt/Passes/Instrumentation.h"
 #include "bolt/Passes/JTFootprintReduction.h"
 #include "bolt/Passes/LongJmp.h"

 static cl::opt<bool>
     PrintSplit("print-split", cl::desc("print functions after code splitting"),
                cl::Hidden, cl::cat(BoltOptCategory));
 
 static cl::opt<bool>
     PrintStoke("print-stoke", cl::desc("print functions after stoke analysis"),
                cl::cat(BoltOptCategory));
 
+static cl::opt<bool>
+    PrintFixRelaxations("print-fix-relaxations",
+                        cl::desc("print functions after fix relaxations pass"),
+                        cl::cat(BoltOptCategory));
+
 static cl::opt<bool> PrintVeneerElimination(
     "print-veneer-elimination",
     cl::desc("print functions after veneer elimination pass"),
     cl::cat(BoltOptCategory));
 
 static cl::opt<bool>
     PrintUCE("print-uce",
              cl::desc("print functions after unreachable code elimination"),
void BinaryFunctionPassManager::runAllPasses(BinaryContext &BC) {
   BinaryFunctionPassManager Manager(BC);
 
   const DynoStats InitialDynoStats =
       getDynoStats(BC.getBinaryFunctions(), BC.isAArch64());
 
   Manager.registerPass(std::make_unique<AsmDumpPass>(),
                        opts::AsmDump.getNumOccurrences());
 
-  if (BC.isAArch64())
+  if (BC.isAArch64()) {
+    Manager.registerPass(std::make_unique<FixRelaxations>(PrintFixRelaxations));
+
     Manager.registerPass(
         std::make_unique<VeneerElimination>(PrintVeneerElimination));
+  }
 
   // Here we manage dependencies/order manually, since passes are run in the
   // order they're registered.
 
   // Run this pass first to use stats for the original functions.
   Manager.registerPass(std::make_unique<PrintProgramStats>(NeverPrint));
 
   if (opts::PrintProfileStats)

bolt/lib/Rewrite/RewriteInstance.cpp

uint32_t getRelocationSymbol(const ELFObjectFileBase *Obj,
   if (auto *ELF32BE = dyn_cast<ELF32BEObjectFile>(Obj))
     return getRelocationSymbol(ELF32BE, Rel);
   auto *ELF64BE = cast<ELF64BEObjectFile>(Obj);
   return getRelocationSymbol(ELF64BE, Rel);
 }
 } // anonymous namespace
 
 bool RewriteInstance::analyzeRelocation(
-    const RelocationRef &Rel, uint64_t RType, std::string &SymbolName,
+    const RelocationRef &Rel, uint64_t &RType, std::string &SymbolName,
     bool &IsSectionRelocation, uint64_t &SymbolAddress, int64_t &Addend,
     uint64_t &ExtractedValue, bool &Skip) const {
   Skip = false;
   if (!Relocation::isSupported(RType))
     return false;
 
   const bool IsAArch64 = BC->isAArch64();
 
if (const BinaryFunction *RogueBF =
                << formatv("function {0} in function {1}\n", *RogueBF,
                           *ContainingBF);
         return;
       }
     }
   }
 
   if (ForceRelocation) {
-    std::string Name = Relocation::isGOT(RType) ? "Zero" : SymbolName;
+    std::string Name =
+        Relocation::isGOT(RType) ? "__BOLT_got_zero" : SymbolName;
     ReferencedSymbol = BC->registerNameAtAddress(Name, 0, 0, 0);
     SymbolAddress = 0;
     if (Relocation::isGOT(RType))
       Addend = Address;
     LLVM_DEBUG(dbgs() << "BOLT-DEBUG: forcing relocation against symbol "
                       << SymbolName << " with addend " << Addend << '\n');
   } else if (ReferencedBF) {
     ReferencedSymbol = ReferencedBF->getSymbol();

bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp

public:
   bool isADRP(const MCInst &Inst) const override {
     return Inst.getOpcode() == AArch64::ADRP;
   }
 
   bool isADR(const MCInst &Inst) const override {
     return Inst.getOpcode() == AArch64::ADR;
   }
 
+  bool isAddXri(const MCInst &Inst) const {
+    return Inst.getOpcode() == AArch64::ADDXri;
+  }
+
   void getADRReg(const MCInst &Inst, MCPhysReg &RegName) const override {
     assert((isADR(Inst) || isADRP(Inst)) && "Not an ADR instruction");
     assert(MCPlus::getNumPrimeOperands(Inst) != 0 &&
            "No operands for ADR instruction");
     assert(Inst.getOperand(0).isReg() &&
            "Unexpected operand in ADR instruction");
     RegName = Inst.getOperand(0).getReg();
   }
public:
   }
 
   bool getSymbolRefOperandNum(const MCInst &Inst, unsigned &OpNum) const {
     if (OpNum >= MCPlus::getNumPrimeOperands(Inst))
       return false;
 
     // Auto-select correct operand number
     if (OpNum == 0) {
-      if (isConditionalBranch(Inst) || isADR(Inst) || isADRP(Inst))
+      if (isConditionalBranch(Inst) || isADR(Inst) || isADRP(Inst) ||
+          isMOVW(Inst))
         OpNum = 1;
-      if (isTB(Inst))
+      if (isTB(Inst) || isAddXri(Inst))
         OpNum = 2;
-      if (isMOVW(Inst))
-        OpNum = 1;
     }
 
     return true;
   }
 
   const MCSymbol *getTargetSymbol(const MCExpr *Expr) const override {
     auto *AArchExpr = dyn_cast<AArch64MCExpr>(Expr);
     if (AArchExpr && AArchExpr->getSubExpr())
if (I->getOpcode() != AArch64::ADRP ||
       return 0;
     TargetHiBits = &*I;
     Addr |= (Address + ((int64_t)I->getOperand(1).getImm() << 12)) &
             0xFFFFFFFFFFFFF000ULL;
     Target = Addr;
     return 3;
   }
 
+  bool matchAdrpAddPair(const MCInst &Adrp, const MCInst &Add) const override {
+    if (!isADRP(Adrp) || !isAddXri(Add))
+      return false;
+
+    assert(Adrp.getOperand(0).isReg() &&
+           "Unexpected operand in ADRP instruction");
+    MCPhysReg AdrpReg = Adrp.getOperand(0).getReg();
+    assert(Add.getOperand(1).isReg() &&
+           "Unexpected operand in ADDXri instruction");
+    MCPhysReg AddReg = Add.getOperand(1).getReg();
+    return AdrpReg == AddReg;
+  }
+
   bool replaceImmWithSymbolRef(MCInst &Inst, const MCSymbol *Symbol,
                                int64_t Addend, MCContext *Ctx, int64_t &Value,
                                uint64_t RelType) const override {
     unsigned ImmOpNo = -1U;
     for (unsigned Index = 0; Index < MCPlus::getNumPrimeOperands(Inst);
          ++Index) {
       if (Inst.getOperand(Index).isImm()) {
         ImmOpNo = Index;

bolt/test/AArch64/Inputs/got-ld64-relaxation.yaml

+--- !ELF
+FileHeader:
+  Class:           ELFCLASS64
+  Data:            ELFDATA2LSB
+  Type:            ET_EXEC
+  Machine:         EM_AARCH64
+  Entry:           0x210648
+ProgramHeaders:
+  - Type:            PT_PHDR
+    Flags:           [ PF_R ]
+    VAddr:           0x200040
+    Align:           0x8
+  - Type:            PT_INTERP
+    Flags:           [ PF_R ]
+    FirstSec:        .interp
+    LastSec:         .interp
+    VAddr:           0x2002A8
+  - Type:            PT_LOAD
+    Flags:           [ PF_R ]
+    FirstSec:        .interp
+    LastSec:         .rodata
+    VAddr:           0x200000
+    Align:           0x10000
+  - Type:            PT_LOAD
+    Flags:           [ PF_X, PF_R ]
+    FirstSec:        .text
+    LastSec:         .plt
+    VAddr:           0x210648
+    Align:           0x10000
+  - Type:            PT_LOAD
+    Flags:           [ PF_W, PF_R ]
+    FirstSec:        .text
+    LastSec:         .got
+    VAddr:           0x322580
+    Align:           0x10000
+  - Type:            PT_LOAD
+    Flags:           [ PF_W, PF_R ]
+    FirstSec:        .data
+    LastSec:         .bss
+    VAddr:           0x332720
+    Align:           0x10000
+  - Type:            PT_DYNAMIC
+    Flags:           [ PF_W, PF_R ]
+    FirstSec:        .dynamic
+    LastSec:         .dynamic
+    VAddr:           0x322590
+    Align:           0x8
+Sections:
+  - Name:            .interp
+    Type:            SHT_PROGBITS
+    Flags:           [ SHF_ALLOC ]
+    Address:         0x2002A8
+    AddressAlign:    0x1
+    Content:         2F6C69622F6C642D6C696E75782D616172636836342E736F2E3100
+  - Name:            .dynsym
+    Type:            SHT_DYNSYM
+    Flags:           [ SHF_ALLOC ]
+    Address:         0x200300
+    Link:            .dynstr
+    AddressAlign:    0x8
+  - Name:            .dynstr
+    Type:            SHT_STRTAB
+    Flags:           [ SHF_ALLOC ]
+    Address:         0x2003F4
+    AddressAlign:    0x1
+  - Name:            .rodata
+    Type:            SHT_PROGBITS
+    Flags:           [ SHF_ALLOC, SHF_MERGE, SHF_STRINGS ]
+    Address:         0x2004E8
+    AddressAlign:    0x8
+    Content:         010002000000000000000000000000000000000000000000486572650A00
+  - Name:            .text
+    Type:            SHT_PROGBITS
+    Flags:           [ SHF_ALLOC, SHF_EXECINSTR ]
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bolt/test/AArch64/got-ld64-relaxation.test

+// This test checks that ADR+LDR instruction sequence relaxed by the linker
+// to the ADR+ADD sequence is properly reconized and handled by bolt
+
+// RUN: yaml2obj %p/Inputs/got-ld64-relaxation.yaml &> %t.exe
+// RUN: llvm-bolt %t.exe -o /dev/null --print-fix-relaxations \
+// RUN:   --print-only=main | FileCheck %s
+
+// CHECK: adrp x0, foo
+// CHECK-NEXT: add x0, x0, :lo12:foo