AMDGPU/GlobalISel: Fix broken expansion of 64-bit vector sext_inreg

[foad]

I'm pretty sure this was correct and you've broken it.

[arsenm]

I'm getting confused by the shift amount being subtracted by the amount to get the sext_inreg encoding

[foad]

I try not to think about shifts at all. The second input operand is just the bit width to extend from.

[arsenm]

In D138051#3928610, @foad wrote:

I try not to think about shifts at all. The second input operand is just the bit width to extend from.

It's hard to not when trying to lift into IR for alive

llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp

case AMDGPU::G_SEXT_INREG: {
 
     int Amt = MI.getOperand(2).getImm();
     if (Amt <= 32) {
       if (Amt == 32) {
         // The low bits are unchanged.
         B.buildCopy(DstRegs[0], SrcRegs[0]);
       } else {
         // Extend in the low bits and propagate the sign bit to the high half.
-        B.buildSExtInReg(DstRegs[0], SrcRegs[0], Amt);
+        B.buildSExtInReg(DstRegs[0], SrcRegs[0], 64 - (32 + Amt));
       }
 
       B.buildAShr(DstRegs[1], DstRegs[0], B.buildConstant(S32, 31));
     } else {
       // The low bits are unchanged, and extend in the high bits.
       B.buildCopy(DstRegs[0], SrcRegs[0]);
       B.buildSExtInReg(DstRegs[1], DstRegs[0], Amt - 32);
     }

llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll

; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = ashr <2 x i64> %value, %amount
   ret <2 x i64> %result
 }
 
 define i65 @v_ashr_i65(i65 %value, i65 %amount) {
 ; GFX6-LABEL: v_ashr_i65:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT:    v_bfe_i32 v4, v2, 0, 1
+; GFX6-NEXT:    v_bfe_i32 v4, v2, 0, 31
 ; GFX6-NEXT:    v_ashrrev_i32_e32 v5, 31, v4
 ; GFX6-NEXT:    v_sub_i32_e32 v8, vcc, 64, v3
 ; GFX6-NEXT:    v_lshr_b64 v[6:7], v[0:1], v3
 ; GFX6-NEXT:    v_lshl_b64 v[8:9], v[4:5], v8
 ; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, 64, v3
 ; GFX6-NEXT:    v_ashr_i64 v[10:11], v[4:5], v3
 ; GFX6-NEXT:    v_or_b32_e32 v6, v6, v8
 ; GFX6-NEXT:    v_ashrrev_i32_e32 v8, 31, v5
 ; GFX6-NEXT:    v_ashr_i64 v[4:5], v[4:5], v2
 ; GFX6-NEXT:    v_or_b32_e32 v7, v7, v9
 ; GFX6-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v3
 ; GFX6-NEXT:    v_cndmask_b32_e32 v2, v4, v6, vcc
 ; GFX6-NEXT:    v_cndmask_b32_e32 v4, v5, v7, vcc
 ; GFX6-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v3
 ; GFX6-NEXT:    v_cndmask_b32_e64 v0, v2, v0, s[4:5]
 ; GFX6-NEXT:    v_cndmask_b32_e64 v1, v4, v1, s[4:5]
 ; GFX6-NEXT:    v_cndmask_b32_e32 v2, v8, v10, vcc
 ; GFX6-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX8-LABEL: v_ashr_i65:
 ; GFX8:       ; %bb.0:
 ; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT:    v_bfe_i32 v4, v2, 0, 1
+; GFX8-NEXT:    v_bfe_i32 v4, v2, 0, 31
 ; GFX8-NEXT:    v_ashrrev_i32_e32 v5, 31, v4
 ; GFX8-NEXT:    v_sub_u32_e32 v8, vcc, 64, v3
 ; GFX8-NEXT:    v_lshrrev_b64 v[6:7], v3, v[0:1]
 ; GFX8-NEXT:    v_lshlrev_b64 v[8:9], v8, v[4:5]
 ; GFX8-NEXT:    v_subrev_u32_e32 v2, vcc, 64, v3
 ; GFX8-NEXT:    v_ashrrev_i64 v[10:11], v3, v[4:5]
 ; GFX8-NEXT:    v_or_b32_e32 v6, v6, v8
 ; GFX8-NEXT:    v_ashrrev_i32_e32 v8, 31, v5
 ; GFX8-NEXT:    v_ashrrev_i64 v[4:5], v2, v[4:5]
 ; GFX8-NEXT:    v_or_b32_e32 v7, v7, v9
 ; GFX8-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v3
 ; GFX8-NEXT:    v_cndmask_b32_e32 v2, v4, v6, vcc
 ; GFX8-NEXT:    v_cndmask_b32_e32 v4, v5, v7, vcc
 ; GFX8-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v3
 ; GFX8-NEXT:    v_cndmask_b32_e64 v0, v2, v0, s[4:5]
 ; GFX8-NEXT:    v_cndmask_b32_e64 v1, v4, v1, s[4:5]
 ; GFX8-NEXT:    v_cndmask_b32_e32 v2, v8, v10, vcc
 ; GFX8-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-LABEL: v_ashr_i65:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:    v_bfe_i32 v4, v2, 0, 1
+; GFX9-NEXT:    v_bfe_i32 v4, v2, 0, 31
 ; GFX9-NEXT:    v_ashrrev_i32_e32 v5, 31, v4
 ; GFX9-NEXT:    v_sub_u32_e32 v8, 64, v3
 ; GFX9-NEXT:    v_lshrrev_b64 v[6:7], v3, v[0:1]
 ; GFX9-NEXT:    v_lshlrev_b64 v[8:9], v8, v[4:5]
 ; GFX9-NEXT:    v_subrev_u32_e32 v2, 64, v3
 ; GFX9-NEXT:    v_ashrrev_i64 v[10:11], v3, v[4:5]
 ; GFX9-NEXT:    v_or_b32_e32 v6, v6, v8
 ; GFX9-NEXT:    v_ashrrev_i32_e32 v8, 31, v5
 ; GFX9-NEXT:    v_ashrrev_i64 v[4:5], v2, v[4:5]
 ; GFX9-NEXT:    v_or_b32_e32 v7, v7, v9
 ; GFX9-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v3
 ; GFX9-NEXT:    v_cndmask_b32_e32 v2, v4, v6, vcc
 ; GFX9-NEXT:    v_cndmask_b32_e32 v4, v5, v7, vcc
 ; GFX9-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v3
 ; GFX9-NEXT:    v_cndmask_b32_e64 v0, v2, v0, s[4:5]
 ; GFX9-NEXT:    v_cndmask_b32_e64 v1, v4, v1, s[4:5]
 ; GFX9-NEXT:    v_cndmask_b32_e32 v2, v8, v10, vcc
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: v_ashr_i65:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_bfe_i32 v4, v2, 0, 1
+; GFX10-NEXT:    v_bfe_i32 v4, v2, 0, 31
 ; GFX10-NEXT:    v_sub_nc_u32_e32 v2, 64, v3
 ; GFX10-NEXT:    v_subrev_nc_u32_e32 v10, 64, v3
 ; GFX10-NEXT:    v_lshrrev_b64 v[6:7], v3, v[0:1]
 ; GFX10-NEXT:    v_cmp_gt_u32_e32 vcc_lo, 64, v3
 ; GFX10-NEXT:    v_ashrrev_i32_e32 v5, 31, v4
 ; GFX10-NEXT:    v_cmp_eq_u32_e64 s4, 0, v3
 ; GFX10-NEXT:    v_lshlrev_b64 v[8:9], v2, v[4:5]
 ; GFX10-NEXT:    v_ashrrev_i64 v[10:11], v10, v[4:5]
 ; GFX10-NEXT:    v_or_b32_e32 v2, v6, v8
 ; GFX10-NEXT:    v_or_b32_e32 v8, v7, v9
 ; GFX10-NEXT:    v_ashrrev_i64 v[6:7], v3, v[4:5]
 ; GFX10-NEXT:    v_ashrrev_i32_e32 v3, 31, v5
 ; GFX10-NEXT:    v_cndmask_b32_e32 v2, v10, v2, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e32 v4, v11, v8, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e64 v0, v2, v0, s4
 ; GFX10-NEXT:    v_cndmask_b32_e64 v1, v4, v1, s4
 ; GFX10-NEXT:    v_cndmask_b32_e32 v2, v3, v6, vcc_lo
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-LABEL: v_ashr_i65:
 ; GFX11:       ; %bb.0:
 ; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT:    v_bfe_i32 v4, v2, 0, 1
+; GFX11-NEXT:    v_bfe_i32 v4, v2, 0, 31
 ; GFX11-NEXT:    v_sub_nc_u32_e32 v2, 64, v3
 ; GFX11-NEXT:    v_subrev_nc_u32_e32 v10, 64, v3
 ; GFX11-NEXT:    v_lshrrev_b64 v[6:7], v3, v[0:1]
 ; GFX11-NEXT:    v_cmp_gt_u32_e32 vcc_lo, 64, v3
 ; GFX11-NEXT:    v_ashrrev_i32_e32 v5, 31, v4
 ; GFX11-NEXT:    v_cmp_eq_u32_e64 s0, 0, v3
 ; GFX11-NEXT:    v_lshlrev_b64 v[8:9], v2, v[4:5]
 ; GFX11-NEXT:    v_ashrrev_i64 v[10:11], v10, v[4:5]
; GFX11-NEXT:    s_setpc_b64 s[30:31]
   ret i65 %result
 }
 
 define i65 @v_ashr_i65_33(i65 %value) {
 ; GFX6-LABEL: v_ashr_i65_33:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v3, v1
-; GFX6-NEXT:    v_bfe_i32 v1, v2, 0, 1
+; GFX6-NEXT:    v_bfe_i32 v1, v2, 0, 31
 ; GFX6-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
 ; GFX6-NEXT:    v_lshl_b64 v[0:1], v[1:2], 31
 ; GFX6-NEXT:    v_lshrrev_b32_e32 v3, 1, v3
 ; GFX6-NEXT:    v_or_b32_e32 v0, v3, v0
 ; GFX6-NEXT:    v_ashrrev_i32_e32 v2, 1, v2
 ; GFX6-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX8-LABEL: v_ashr_i65_33:
 ; GFX8:       ; %bb.0:
 ; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX8-NEXT:    v_mov_b32_e32 v3, v1
-; GFX8-NEXT:    v_bfe_i32 v1, v2, 0, 1
+; GFX8-NEXT:    v_bfe_i32 v1, v2, 0, 31
 ; GFX8-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
 ; GFX8-NEXT:    v_lshlrev_b64 v[0:1], 31, v[1:2]
 ; GFX8-NEXT:    v_lshrrev_b32_e32 v3, 1, v3
 ; GFX8-NEXT:    v_or_b32_e32 v0, v3, v0
 ; GFX8-NEXT:    v_ashrrev_i32_e32 v2, 1, v2
 ; GFX8-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-LABEL: v_ashr_i65_33:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_mov_b32_e32 v3, v1
-; GFX9-NEXT:    v_bfe_i32 v1, v2, 0, 1
+; GFX9-NEXT:    v_bfe_i32 v1, v2, 0, 31
 ; GFX9-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
 ; GFX9-NEXT:    v_lshlrev_b64 v[0:1], 31, v[1:2]
 ; GFX9-NEXT:    v_lshrrev_b32_e32 v3, 1, v3
 ; GFX9-NEXT:    v_or_b32_e32 v0, v3, v0
 ; GFX9-NEXT:    v_ashrrev_i32_e32 v2, 1, v2
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10PLUS-LABEL: v_ashr_i65_33:
 ; GFX10PLUS:       ; %bb.0:
 ; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10PLUS-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX10PLUS-NEXT:    v_mov_b32_e32 v3, v1
-; GFX10PLUS-NEXT:    v_bfe_i32 v1, v2, 0, 1
+; GFX10PLUS-NEXT:    v_bfe_i32 v1, v2, 0, 31
 ; GFX10PLUS-NEXT:    v_lshrrev_b32_e32 v3, 1, v3
 ; GFX10PLUS-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
 ; GFX10PLUS-NEXT:    v_lshlrev_b64 v[0:1], 31, v[1:2]
 ; GFX10PLUS-NEXT:    v_ashrrev_i32_e32 v2, 1, v2
 ; GFX10PLUS-NEXT:    v_or_b32_e32 v0, v3, v0
 ; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
   %result = ashr i65 %value, 33
   ret i65 %result

llvm/test/CodeGen/AMDGPU/GlobalISel/sext_inreg.ll

; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
   %ashr = ashr i64 %shl, 23
   ret i64 %ashr
 }
 
 define i64 @v_sext_inreg_i64_40(i64 %value) {
 ; GCN-LABEL: v_sext_inreg_i64_40:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
+; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 8
 ; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10PLUS-LABEL: v_sext_inreg_i64_40:
 ; GFX10PLUS:       ; %bb.0:
 ; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10PLUS-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10PLUS-NEXT:    v_bfe_i32 v0, v0, 0, 24
+; GFX10PLUS-NEXT:    v_bfe_i32 v0, v0, 0, 8
 ; GFX10PLUS-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
 ; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
   %shl = shl i64 %value, 40
   %ashr = ashr i64 %shl, 40
   ret i64 %ashr
 }
 
 define i64 @v_sext_inreg_i64_63(i64 %value) {
 ; GCN-LABEL: v_sext_inreg_i64_63:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 1
+; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 31
 ; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10PLUS-LABEL: v_sext_inreg_i64_63:
 ; GFX10PLUS:       ; %bb.0:
 ; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10PLUS-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10PLUS-NEXT:    v_bfe_i32 v0, v0, 0, 1
+; GFX10PLUS-NEXT:    v_bfe_i32 v0, v0, 0, 31
 ; GFX10PLUS-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
 ; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
   %shl = shl i64 %value, 63
   %ashr = ashr i64 %shl, 63
   ret i64 %ashr
 }
 
 define i64 @v_sext_inreg_i64_33(i64 %value) {
 ; GCN-LABEL: v_sext_inreg_i64_33:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 31
+; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 1
 ; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10PLUS-LABEL: v_sext_inreg_i64_33:
 ; GFX10PLUS:       ; %bb.0:
 ; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10PLUS-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10PLUS-NEXT:    v_bfe_i32 v0, v0, 0, 31
+; GFX10PLUS-NEXT:    v_bfe_i32 v0, v0, 0, 1
 ; GFX10PLUS-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
 ; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
   %shl = shl i64 %value, 33
   %ashr = ashr i64 %shl, 33
   ret i64 %ashr
 }
 
 define i64 @v_sext_inreg_i64_32(i64 %value) {

 
 define i65 @v_sext_inreg_i65_22(i65 %value) {
 ; GFX6-LABEL: v_sext_inreg_i65_22:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX6-NEXT:    v_lshl_b64 v[2:3], v[2:3], 22
 ; GFX6-NEXT:    v_lshrrev_b32_e32 v3, 10, v1
 ; GFX6-NEXT:    v_or_b32_e32 v2, v2, v3
-; GFX6-NEXT:    v_bfe_i32 v2, v2, 0, 1
+; GFX6-NEXT:    v_bfe_i32 v2, v2, 0, 31
 ; GFX6-NEXT:    v_lshr_b64 v[0:1], v[0:1], 0
 ; GFX6-NEXT:    v_ashrrev_i32_e32 v3, 31, v2
 ; GFX6-NEXT:    v_bfe_u32 v1, v1, 0, 10
 ; GFX6-NEXT:    v_lshlrev_b32_e32 v4, 10, v2
 ; GFX6-NEXT:    v_ashr_i64 v[2:3], v[2:3], 22
 ; GFX6-NEXT:    v_or_b32_e32 v1, v1, v4
 ; GFX6-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX8-LABEL: v_sext_inreg_i65_22:
 ; GFX8:       ; %bb.0:
 ; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX8-NEXT:    v_lshlrev_b64 v[2:3], 22, v[2:3]
 ; GFX8-NEXT:    v_lshrrev_b32_e32 v3, 10, v1
 ; GFX8-NEXT:    v_or_b32_e32 v2, v2, v3
-; GFX8-NEXT:    v_bfe_i32 v2, v2, 0, 1
+; GFX8-NEXT:    v_bfe_i32 v2, v2, 0, 31
 ; GFX8-NEXT:    v_lshrrev_b64 v[0:1], 0, v[0:1]
 ; GFX8-NEXT:    v_ashrrev_i32_e32 v3, 31, v2
 ; GFX8-NEXT:    v_bfe_u32 v1, v1, 0, 10
 ; GFX8-NEXT:    v_lshlrev_b32_e32 v4, 10, v2
 ; GFX8-NEXT:    v_ashrrev_i64 v[2:3], 22, v[2:3]
 ; GFX8-NEXT:    v_or_b32_e32 v1, v1, v4
 ; GFX8-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-LABEL: v_sext_inreg_i65_22:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_lshlrev_b64 v[2:3], 22, v[2:3]
 ; GFX9-NEXT:    v_lshrrev_b32_e32 v3, 10, v1
 ; GFX9-NEXT:    v_or_b32_e32 v2, v2, v3
-; GFX9-NEXT:    v_bfe_i32 v2, v2, 0, 1
+; GFX9-NEXT:    v_bfe_i32 v2, v2, 0, 31
 ; GFX9-NEXT:    v_lshrrev_b64 v[0:1], 0, v[0:1]
 ; GFX9-NEXT:    v_ashrrev_i32_e32 v3, 31, v2
 ; GFX9-NEXT:    v_bfe_u32 v1, v1, 0, 10
 ; GFX9-NEXT:    v_lshlrev_b32_e32 v4, 10, v2
 ; GFX9-NEXT:    v_ashrrev_i64 v[2:3], 22, v[2:3]
 ; GFX9-NEXT:    v_or_b32_e32 v1, v1, v4
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10PLUS-LABEL: v_sext_inreg_i65_22:
 ; GFX10PLUS:       ; %bb.0:
 ; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10PLUS-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX10PLUS-NEXT:    v_lshlrev_b64 v[2:3], 22, v[2:3]
 ; GFX10PLUS-NEXT:    v_lshrrev_b32_e32 v3, 10, v1
 ; GFX10PLUS-NEXT:    v_lshrrev_b64 v[0:1], 0, v[0:1]
 ; GFX10PLUS-NEXT:    v_or_b32_e32 v2, v2, v3
 ; GFX10PLUS-NEXT:    v_bfe_u32 v1, v1, 0, 10
-; GFX10PLUS-NEXT:    v_bfe_i32 v2, v2, 0, 1
+; GFX10PLUS-NEXT:    v_bfe_i32 v2, v2, 0, 31
 ; GFX10PLUS-NEXT:    v_ashrrev_i32_e32 v3, 31, v2
 ; GFX10PLUS-NEXT:    v_lshlrev_b32_e32 v4, 10, v2
 ; GFX10PLUS-NEXT:    v_ashrrev_i64 v[2:3], 22, v[2:3]
 ; GFX10PLUS-NEXT:    v_or_b32_e32 v1, v1, v4
 ; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
   %shl = shl i65 %value, 22
   %ashr = ashr i65 %shl, 22
   ret i65 %ashr
 }
 
 define i65 @v_sext_inreg_i65_33(i65 %value) {
 ; GFX6-LABEL: v_sext_inreg_i65_33:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v3, v1
-; GFX6-NEXT:    v_bfe_i32 v1, v2, 0, 1
+; GFX6-NEXT:    v_bfe_i32 v1, v2, 0, 31
 ; GFX6-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
 ; GFX6-NEXT:    v_lshl_b64 v[0:1], v[1:2], 31
 ; GFX6-NEXT:    v_lshrrev_b32_e32 v3, 1, v3
 ; GFX6-NEXT:    v_or_b32_e32 v0, v3, v0
 ; GFX6-NEXT:    v_ashrrev_i32_e32 v2, 1, v2
 ; GFX6-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX8-LABEL: v_sext_inreg_i65_33:
 ; GFX8:       ; %bb.0:
 ; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX8-NEXT:    v_mov_b32_e32 v3, v1
-; GFX8-NEXT:    v_bfe_i32 v1, v2, 0, 1
+; GFX8-NEXT:    v_bfe_i32 v1, v2, 0, 31
 ; GFX8-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
 ; GFX8-NEXT:    v_lshlrev_b64 v[0:1], 31, v[1:2]
 ; GFX8-NEXT:    v_lshrrev_b32_e32 v3, 1, v3
 ; GFX8-NEXT:    v_or_b32_e32 v0, v3, v0
 ; GFX8-NEXT:    v_ashrrev_i32_e32 v2, 1, v2
 ; GFX8-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-LABEL: v_sext_inreg_i65_33:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_mov_b32_e32 v3, v1
-; GFX9-NEXT:    v_bfe_i32 v1, v2, 0, 1
+; GFX9-NEXT:    v_bfe_i32 v1, v2, 0, 31
 ; GFX9-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
 ; GFX9-NEXT:    v_lshlrev_b64 v[0:1], 31, v[1:2]
 ; GFX9-NEXT:    v_lshrrev_b32_e32 v3, 1, v3
 ; GFX9-NEXT:    v_or_b32_e32 v0, v3, v0
 ; GFX9-NEXT:    v_ashrrev_i32_e32 v2, 1, v2
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10PLUS-LABEL: v_sext_inreg_i65_33:
 ; GFX10PLUS:       ; %bb.0:
 ; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10PLUS-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX10PLUS-NEXT:    v_mov_b32_e32 v3, v1
-; GFX10PLUS-NEXT:    v_bfe_i32 v1, v2, 0, 1
+; GFX10PLUS-NEXT:    v_bfe_i32 v1, v2, 0, 31
 ; GFX10PLUS-NEXT:    v_lshrrev_b32_e32 v3, 1, v3
 ; GFX10PLUS-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
 ; GFX10PLUS-NEXT:    v_lshlrev_b64 v[0:1], 31, v[1:2]
 ; GFX10PLUS-NEXT:    v_ashrrev_i32_e32 v2, 1, v2
 ; GFX10PLUS-NEXT:    v_or_b32_e32 v0, v3, v0
 ; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
   %shl = shl i65 %value, 33
   %ashr = ashr i65 %value, 33