[AMDGPU][MC][GFX11] Correct op_sel handling for permlane*16

[dp]

Summary

Unify handling of GFX10 and GFX11 permlane16 opcodes:

• disable op_sel for bits other than 0 and 1.
• correct disassembly to print op_sel values for first two bits only.

[dp]

Ping.

[Joe_Nash]

LGTM

llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

for (int OpIdx : OpIndices) {
     }
   }
 
   return NumLiterals + NumExprs <= 1;
 }
 
 bool AMDGPUAsmParser::validateOpSel(const MCInst &Inst) {
   const unsigned Opc = Inst.getOpcode();
-  if (Opc == AMDGPU::V_PERMLANE16_B32_gfx10 ||
-      Opc == AMDGPU::V_PERMLANEX16_B32_gfx10) {
+  if (isPermlane16(Opc)) {
     int OpSelIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel);
     unsigned OpSel = Inst.getOperand(OpSelIdx).getImm();
 
     if (OpSel & ~3)
       return false;
   }
 
   uint64_t TSFlags = MII.get(Opc).TSFlags;

llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp

void AMDGPUInstPrinter::printPackedModifier(const MCInst *MI,
 
   O << ']';
 }
 
 void AMDGPUInstPrinter::printOpSel(const MCInst *MI, unsigned,
                                    const MCSubtargetInfo &STI,
                                    raw_ostream &O) {
   unsigned Opc = MI->getOpcode();
-  if (Opc == AMDGPU::V_PERMLANE16_B32_gfx10 ||
-      Opc == AMDGPU::V_PERMLANEX16_B32_gfx10) {
+  if (isPermlane16(Opc)) {
     auto FIN = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers);
     auto BCN = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1_modifiers);
     unsigned FI = !!(MI->getOperand(FIN).getImm() & SISrcMods::OP_SEL_0);
     unsigned BC = !!(MI->getOperand(BCN).getImm() & SISrcMods::OP_SEL_0);
     if (FI || BC)
       O << " op_sel:[" << FI << ',' << BC << ']';
     return;
   }

llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h

 unsigned getVOPDOpcode(unsigned Opc);
 
 LLVM_READONLY
 int getVOPDFull(unsigned OpX, unsigned OpY);
 
 LLVM_READONLY
 bool isVOPD(unsigned Opc);
 
+LLVM_READNONE
+bool isPermlane16(unsigned Opc);
+
 namespace VOPD {
 
 enum Component : unsigned {
   DST = 0,
   SRC0,
   SRC1,
   SRC2,
 

llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp

unsigned getVOPDOpcode(unsigned Opc) {
   const VOPDComponentInfo *Info = getVOPDComponentHelper(Opc);
   return Info ? Info->VOPDOp : ~0u;
 }
 
 bool isVOPD(unsigned Opc) {
   return AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src0X);
 }
 
+bool isPermlane16(unsigned Opc) {
+  return Opc == AMDGPU::V_PERMLANE16_B32_gfx10 ||
+         Opc == AMDGPU::V_PERMLANEX16_B32_gfx10 ||
+         Opc == AMDGPU::V_PERMLANE16_B32_e64_gfx11 ||
+         Opc == AMDGPU::V_PERMLANEX16_B32_e64_gfx11;
+}
+
 bool isTrue16Inst(unsigned Opc) {
   const VOPTrue16Info *Info = getTrue16OpcodeHelper(Opc);
   return Info ? Info->IsTrue16 : false;
 }
 
 unsigned mapWMMA2AddrTo3AddrOpcode(unsigned Opc) {
   const WMMAOpcodeMappingInfo *Info = getWMMAMappingInfoFrom2AddrOpcode(Opc);
   return Info ? Info->Opcode3Addr : ~0u;

llvm/test/MC/AMDGPU/gfx11_asm_vop3_err.s

+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX11 --implicit-check-not=error %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX11 --implicit-check-not=error %s
+
+v_permlane16_b32 v5, v1, s2, s3 op_sel:[0, 0, 0, 1]
+// GFX11: error: invalid op_sel operand
+
+v_permlanex16_b32 v5, v1, s2, s3 op_sel:[0, 0, 1, 0]
+// GFX11: error: invalid op_sel operand

llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3.txt

 0x05,0x00,0x5b,0xd6,0x01,0xfb,0x05,0x03
 
 # GFX11: v_permlane16_b32 v255, v255, 0xaf123456, null ; encoding: [0xff,0x00,0x5b,0xd6,0xff,0xff,0xf1,0x01,0x56,0x34,0x12,0xaf]
 0xff,0x00,0x5b,0xd6,0xff,0xff,0xf1,0x01,0x56,0x34,0x12,0xaf
 
 # GFX11: v_permlanex16_b32 v5, v1, s2, s3        ; encoding: [0x05,0x00,0x5c,0xd6,0x01,0x05,0x0c,0x00]
 0x05,0x00,0x5c,0xd6,0x01,0x05,0x0c,0x00
 
+# GFX11: v_permlane16_b32 v5, v1, s2, s3 op_sel:[1,1] ; encoding: [0x05,0x18,0x5b,0xd6,0x01,0x05,0x0c,0x00]
+0x05,0x18,0x5b,0xd6,0x01,0x05,0x0c,0x00
+
+# GFX11: v_permlane16_b32 v5, v1, s2, s3 op_sel:[1,0] ; encoding: [0x05,0x08,0x5b,0xd6,0x01,0x05,0x0c,0x00]
+0x05,0x08,0x5b,0xd6,0x01,0x05,0x0c,0x00
+
+# GFX11: v_permlane16_b32 v5, v1, s2, s3 op_sel:[0,1] ; encoding: [0x05,0x10,0x5b,0xd6,0x01,0x05,0x0c,0x00]
+0x05,0x10,0x5b,0xd6,0x01,0x05,0x0c,0x00
+
 # GFX11: v_permlanex16_b32 v5, v1, s105, s105    ; encoding: [0x05,0x00,0x5c,0xd6,0x01,0xd3,0xa4,0x01]
 0x05,0x00,0x5c,0xd6,0x01,0xd3,0xa4,0x01
 
 # GFX11: v_permlanex16_b32 v5, v1, ttmp15, ttmp15 ; encoding: [0x05,0x00,0x5c,0xd6,0x01,0xf7,0xec,0x01]
 0x05,0x00,0x5c,0xd6,0x01,0xf7,0xec,0x01
 
 # GFX11: v_permlanex16_b32 v5, v1, vcc_hi, exec_hi ; encoding: [0x05,0x00,0x5c,0xd6,0x01,0xd7,0xfc,0x01]
 0x05,0x00,0x5c,0xd6,0x01,0xd7,0xfc,0x01

 0x05,0x00,0x5c,0xd6,0x01,0xe1,0xc1,0x03
 
 # GFX11: v_permlanex16_b32 v5, v1, src_scc, -1   ; encoding: [0x05,0x00,0x5c,0xd6,0x01,0xfb,0x05,0x03]
 0x05,0x00,0x5c,0xd6,0x01,0xfb,0x05,0x03
 
 # GFX11: v_permlanex16_b32 v255, v255, 0xaf123456, null ; encoding: [0xff,0x00,0x5c,0xd6,0xff,0xff,0xf1,0x01,0x56,0x34,0x12,0xaf]
 0xff,0x00,0x5c,0xd6,0xff,0xff,0xf1,0x01,0x56,0x34,0x12,0xaf
 
+# GFX11: v_permlanex16_b32 v5, v1, s2, s3 op_sel:[1,1] ; encoding: [0x05,0x18,0x5c,0xd6,0x01,0x05,0x0c,0x00]
+0x05,0x18,0x5c,0xd6,0x01,0x05,0x0c,0x00
+
+# GFX11: v_permlanex16_b32 v5, v1, s2, s3 op_sel:[1,0] ; encoding: [0x05,0x08,0x5c,0xd6,0x01,0x05,0x0c,0x00]
+0x05,0x08,0x5c,0xd6,0x01,0x05,0x0c,0x00
+
+# GFX11: v_permlanex16_b32 v5, v1, s2, s3 op_sel:[0,1] ; encoding: [0x05,0x10,0x5c,0xd6,0x01,0x05,0x0c,0x00]
+0x05,0x10,0x5c,0xd6,0x01,0x05,0x0c,0x00
+
 # GFX11: v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, ttmp[14:15] ; encoding: [0x05,0x00,0x3a,0xd6,0x01,0x05,0xea,0x01]
 0x05,0x00,0x3a,0xd6,0x01,0x05,0xea,0x01
 
 # GFX11: v_qsad_pk_u16_u8 v[5:6], v[1:2], v255, ttmp[14:15] ; encoding: [0x05,0x00,0x3a,0xd6,0x01,0xff,0xeb,0x01]
 0x05,0x00,0x3a,0xd6,0x01,0xff,0xeb,0x01
 
 # GFX11: v_qsad_pk_u16_u8 v[5:6], v[1:2], s2, ttmp[14:15] ; encoding: [0x05,0x00,0x3a,0xd6,0x01,0x05,0xe8,0x01]
 0x05,0x00,0x3a,0xd6,0x01,0x05,0xe8,0x01