[SPARC] Simplify instruction decoder.

[jyknight]

Summary

After https://reviews.llvm.org/D137653 named sub-operands can be used
in the auto-generated instruction decoders. This allows the
auto-generated decoders to work properly, so all the hand-coded
decoders in the sparc target can be removed.

In some instances, a manually-written decoder had not been implemented
for an instruction, and thus that instruction was not decoded
properly. These have been fixed (and tests added).

[MaskRay]

I think Sparc backend has many untested things and many(?) parts are somewhat broken. Perhaps @brad, @koakuma can do some verification

[brad]

In D137727#3939223, @MaskRay wrote:

I think Sparc backend has many untested things and many(?) parts are somewhat broken. Perhaps @brad, @koakuma can do some verification

It is definitely not of the same level of maturity as the other major CPU archs. It is inching towards being in a usable state.

[koakuma]

The patch doesn't apply cleanly as-is on my test system (seems like there are some of the proposed changes that's already in main?).
Once I got the patch to apply, though, it seems to be hitting some assertion failures:

******************** TEST 'LLVM :: MC/Disassembler/Sparc/sparc-mem.txt' FAILED ********************                                    
Script:                                                                                                                                
--                                                                                                                                     
: 'RUN: at line 1';   /home/k/llvm-debug/src/llvm-project/out/bin/llvm-mc --disassemble /home/k/llvm-debug/src/llvm-project/llvm/test/M
C/Disassembler/Sparc/sparc-mem.txt -triple=sparcv9-unknown-linux | /home/k/llvm-debug/src/llvm-project/out/bin/FileCheck /home/k/llvm-debug/src/llvm-project/llvm/test/MC/Disassembler/Sparc/sparc-mem.txt                                                                    --                                                                                                                                     Exit Code: 2                                                                                                                                                                                                                                                                  
Command Output (stderr):                                                                                                               
--                                                                                                                                     
llvm-mc: /home/k/llvm-debug/src/llvm-project/llvm/include/llvm/ADT/SmallVector.h:298: const T& llvm::SmallVectorTemplateCommon<T, <temp
late-parameter-1-2> >::operator[](llvm::SmallVectorTemplateCommon<T, <template-parameter-1-2> >::size_type) const [with T = llvm::MCOpe
rand; <template-parameter-1-2> = void; llvm::SmallVectorTemplateCommon<T, <template-parameter-1-2> >::const_reference = const llvm::MCOperand&; llvm::SmallVectorTemplateCommon<T, <template-parameter-1-2> >::size_type = long unsigned int]: Assertion `idx < size()' failed
.                                                                                                                                      
PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace.                            
Stack dump:                                                                                                                            
0.      Program arguments: /home/k/llvm-debug/src/llvm-project/out/bin/llvm-mc --disassemble /home/k/llvm-debug/src/llvm-project/llvm/t
est/MC/Disassembler/Sparc/sparc-mem.txt -triple=sparcv9-unknown-linux                                                                  
#0 0xfff80001013a3afc PrintStackTraceSignalHandler(void*) Signals.cpp:0:0                                                              
FileCheck error: '<stdin>' is empty.                                                                                                   
FileCheck command line:  /home/k/llvm-debug/src/llvm-project/out/bin/FileCheck /home/k/llvm-debug/src/llvm-project/llvm/test/MC/Disasse
mbler/Sparc/sparc-mem.txt                                                                                                              
                                                                                                                                       
--                                                                                                                                     
                                                                                                                                       
******************** TEST 'LLVM :: MC/Disassembler/Sparc/sparc-coproc.txt' FAILED ********************                                 
Script:                                                                                                                                
--                                                                                                                                     
: 'RUN: at line 1';   /home/k/llvm-debug/src/llvm-project/out/bin/llvm-mc --disassemble /home/k/llvm-debug/src/llvm-project/llvm/test/M
C/Disassembler/Sparc/sparc-coproc.txt -triple=sparcv9-unknown-linux | /home/k/llvm-debug/src/llvm-project/out/bin/FileCheck /home/k/llv
m-debug/src/llvm-project/llvm/test/MC/Disassembler/Sparc/sparc-coproc.txt                                                              
--                                                                                                                                     
Exit Code: 2                                                                                                                           
                                                                                                                                       
Command Output (stderr):                                                                                                               
--                                                                                                                                     
llvm-mc: /home/k/llvm-debug/src/llvm-project/llvm/include/llvm/ADT/SmallVector.h:298: const T& llvm::SmallVectorTemplateCommon<T, <temp
late-parameter-1-2> >::operator[](llvm::SmallVectorTemplateCommon<T, <template-parameter-1-2> >::size_type) const [with T = llvm::MCOpe
rand; <template-parameter-1-2> = void; llvm::SmallVectorTemplateCommon<T, <template-parameter-1-2> >::const_reference = const llvm::MCO
perand&; llvm::SmallVectorTemplateCommon<T, <template-parameter-1-2> >::size_type = long unsigned int]: Assertion `idx < size()' failed
.                                                                                                                                      
PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace.                            
Stack dump:                                                                                                                            
0.      Program arguments: /home/k/llvm-debug/src/llvm-project/out/bin/llvm-mc --disassemble /home/k/llvm-debug/src/llvm-project/llvm/t
est/MC/Disassembler/Sparc/sparc-coproc.txt -triple=sparcv9-unknown-linux                                                               
#0 0xfff80001014a3afc PrintStackTraceSignalHandler(void*) Signals.cpp:0:0                                                              
FileCheck error: '<stdin>' is empty.                                                                                                   
FileCheck command line:  /home/k/llvm-debug/src/llvm-project/out/bin/FileCheck /home/k/llvm-debug/src/llvm-project/llvm/test/MC/Disasse
mbler/Sparc/sparc-coproc.txt                                                                                                           
                                                                                                                                       
--

llvm/test/MC/Disassembler/Sparc/sparc-coproc.txt

1

Coprocessor instructions are only available in v8.
v9 reassigned the encoding to other instructions (see §A.23 and §A.53 of the v9 ISA spec, for example), so I think the decoder should differentiate between the two meanings, if possible.

[jyknight]

In D137727#3939675, @koakuma wrote:

The patch doesn't apply cleanly as-is on my test system (seems like there are some of the proposed changes that's already in main?).

It depends on https://reviews.llvm.org/D137653 which is not yet committed.

llvm/test/MC/Disassembler/Sparc/sparc-coproc.txt

1

I will switch the test to test v8, but changing the instruction definition to be v8-only is out of scope for this patch.

[jyknight]

Update coproc test to use v8 instead of v9.

[koakuma]

Looks okay here too, thanks.

llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp

static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo,
   unsigned Reg = IntRegDecoderTable[RegNo];
   Inst.addOperand(MCOperand::createReg(Reg));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeI64RegsRegisterClass(MCInst &Inst, unsigned RegNo,
                                                uint64_t Address,
                                                const MCDisassembler *Decoder) {
-  if (RegNo > 31)
-    return MCDisassembler::Fail;
-  unsigned Reg = IntRegDecoderTable[RegNo];
-  Inst.addOperand(MCOperand::createReg(Reg));
-  return MCDisassembler::Success;
+  return DecodeIntRegsRegisterClass(Inst, RegNo, Address, Decoder);
+}
+
+// This is used for the type "ptr_rc", which is either IntRegs or I64Regs
+// depending on SparcRegisterInfo::getPointerRegClass.
+static DecodeStatus DecodePointerLikeRegClass0(MCInst &Inst, unsigned RegNo,
+                                               uint64_t Address,
+                                               const MCDisassembler *Decoder) {
+  return DecodeIntRegsRegisterClass(Inst, RegNo, Address, Decoder);
 }
 
 static DecodeStatus DecodeFPRegsRegisterClass(MCInst &Inst, unsigned RegNo,
                                               uint64_t Address,
                                               const MCDisassembler *Decoder) {
   if (RegNo > 31)
     return MCDisassembler::Fail;
   unsigned Reg = FPRegDecoderTable[RegNo];
static DecodeStatus DecodeQFPRegsRegisterClass(MCInst &Inst, unsigned RegNo,
 
   unsigned Reg = QFPRegDecoderTable[RegNo];
   if (Reg == ~0U)
     return MCDisassembler::Fail;
   Inst.addOperand(MCOperand::createReg(Reg));
   return MCDisassembler::Success;
 }
 
-static DecodeStatus DecodeCPRegsRegisterClass(MCInst &Inst, unsigned RegNo,
-                                              uint64_t Address,
-                                              const MCDisassembler *Decoder) {
+static DecodeStatus
+DecodeCoprocRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
   if (RegNo > 31)
     return MCDisassembler::Fail;
   unsigned Reg = CPRegDecoderTable[RegNo];
   Inst.addOperand(MCOperand::createReg(Reg));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeFCCRegsRegisterClass(MCInst &Inst, unsigned RegNo,
static DecodeStatus DecodeIntPairRegisterClass(MCInst &Inst, unsigned RegNo,
   if ((RegNo & 1))
     S = MCDisassembler::SoftFail;
 
   unsigned RegisterPair = IntPairDecoderTable[RegNo/2];
   Inst.addOperand(MCOperand::createReg(RegisterPair));
   return S;
 }
 
-static DecodeStatus DecodeCPPairRegisterClass(MCInst &Inst, unsigned RegNo,
-                                              uint64_t Address,
-                                              const MCDisassembler *Decoder) {
+static DecodeStatus
+DecodeCoprocPairRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
   if (RegNo > 31)
     return MCDisassembler::Fail;
 
   unsigned RegisterPair = CPPairDecoderTable[RegNo/2];
   Inst.addOperand(MCOperand::createReg(RegisterPair));
   return MCDisassembler::Success;
 }
 
-static DecodeStatus DecodeLoadInt(MCInst &Inst, unsigned insn, uint64_t Address,
-                                  const MCDisassembler *Decoder);
-static DecodeStatus DecodeLoadIntPair(MCInst &Inst, unsigned insn,
-                                      uint64_t Address,
-                                      const MCDisassembler *Decoder);
-static DecodeStatus DecodeLoadFP(MCInst &Inst, unsigned insn, uint64_t Address,
-                                 const MCDisassembler *Decoder);
-static DecodeStatus DecodeLoadDFP(MCInst &Inst, unsigned insn, uint64_t Address,
-                                  const MCDisassembler *Decoder);
-static DecodeStatus DecodeLoadQFP(MCInst &Inst, unsigned insn, uint64_t Address,
-                                  const MCDisassembler *Decoder);
-static DecodeStatus DecodeLoadCP(MCInst &Inst, unsigned insn, uint64_t Address,
-                                 const MCDisassembler *Decoder);
-static DecodeStatus DecodeLoadCPPair(MCInst &Inst, unsigned insn,
-                                     uint64_t Address,
-                                     const MCDisassembler *Decoder);
-static DecodeStatus DecodeStoreInt(MCInst &Inst, unsigned insn,
-                                   uint64_t Address,
-                                   const MCDisassembler *Decoder);
-static DecodeStatus DecodeStoreIntPair(MCInst &Inst, unsigned insn,
-                                       uint64_t Address,
-                                       const MCDisassembler *Decoder);
-static DecodeStatus DecodeStoreFP(MCInst &Inst, unsigned insn, uint64_t Address,
-                                  const MCDisassembler *Decoder);
-static DecodeStatus DecodeStoreDFP(MCInst &Inst, unsigned insn,
-                                   uint64_t Address,
-                                   const MCDisassembler *Decoder);
-static DecodeStatus DecodeStoreQFP(MCInst &Inst, unsigned insn,
-                                   uint64_t Address,
-                                   const MCDisassembler *Decoder);
-static DecodeStatus DecodeStoreCP(MCInst &Inst, unsigned insn, uint64_t Address,
-                                  const MCDisassembler *Decoder);
-static DecodeStatus DecodeStoreCPPair(MCInst &Inst, unsigned insn,
-                                      uint64_t Address,
-                                      const MCDisassembler *Decoder);
 static DecodeStatus DecodeCall(MCInst &Inst, unsigned insn, uint64_t Address,
                                const MCDisassembler *Decoder);
 static DecodeStatus DecodeSIMM13(MCInst &Inst, unsigned insn, uint64_t Address,
                                  const MCDisassembler *Decoder);
-static DecodeStatus DecodeJMPL(MCInst &Inst, unsigned insn, uint64_t Address,
-                               const MCDisassembler *Decoder);
-static DecodeStatus DecodeReturn(MCInst &MI, unsigned insn, uint64_t Address,
-                                 const MCDisassembler *Decoder);
-static DecodeStatus DecodeSWAP(MCInst &Inst, unsigned insn, uint64_t Address,
-                               const MCDisassembler *Decoder);
-static DecodeStatus DecodeTRAP(MCInst &Inst, unsigned insn, uint64_t Address,
-                               const MCDisassembler *Decoder);
-static DecodeStatus DecodeFIXMEInstruction(MCInst &MI, unsigned insn,
-                                           uint64_t Address,
-                                           const MCDisassembler *Decoder);
 
 #include "SparcGenDisassemblerTables.inc"
 
 /// Read four bytes from the ArrayRef and return 32 bit word.
 static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address,
                                       uint64_t &Size, uint32_t &Insn,
                                       bool IsLittleEndian) {
   // We want to read exactly 4 Bytes of data.
DecodeStatus SparcDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
   if (Result != MCDisassembler::Fail) {
     Size = 4;
     return Result;
   }
 
   return MCDisassembler::Fail;
 }
 
-typedef DecodeStatus (*DecodeFunc)(MCInst &MI, unsigned insn, uint64_t Address,
-                                   const MCDisassembler *Decoder);
-
-static DecodeStatus DecodeMem(MCInst &MI, unsigned insn, uint64_t Address,
-                              const MCDisassembler *Decoder, bool isLoad,
-                              DecodeFunc DecodeRD) {
-  unsigned rd = fieldFromInstruction(insn, 25, 5);
-  unsigned rs1 = fieldFromInstruction(insn, 14, 5);
-  bool isImm = fieldFromInstruction(insn, 13, 1);
-  bool hasAsi = fieldFromInstruction(insn, 23, 1); // (in op3 field)
-  unsigned asi = fieldFromInstruction(insn, 5, 8);
-  unsigned rs2 = 0;
-  unsigned simm13 = 0;
-  if (isImm)
-    simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
-  else
-    rs2 = fieldFromInstruction(insn, 0, 5);
-
-  DecodeStatus status;
-  if (isLoad) {
-    status = DecodeRD(MI, rd, Address, Decoder);
-    if (status != MCDisassembler::Success)
-      return status;
-  }
-
-  // Decode rs1.
-  status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
-  if (status != MCDisassembler::Success)
-    return status;
-
-  // Decode imm|rs2.
-  if (isImm)
-    MI.addOperand(MCOperand::createImm(simm13));
-  else {
-    status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
-    if (status != MCDisassembler::Success)
-      return status;
-  }
-
-  if (hasAsi)
-    MI.addOperand(MCOperand::createImm(asi));
-
-  if (!isLoad) {
-    status = DecodeRD(MI, rd, Address, Decoder);
-    if (status != MCDisassembler::Success)
-      return status;
-  }
-  return MCDisassembler::Success;
-}
-
-static DecodeStatus DecodeLoadInt(MCInst &Inst, unsigned insn, uint64_t Address,
-                                  const MCDisassembler *Decoder) {
-  return DecodeMem(Inst, insn, Address, Decoder, true,
-                   DecodeIntRegsRegisterClass);
-}
-
-static DecodeStatus DecodeLoadIntPair(MCInst &Inst, unsigned insn,
-                                      uint64_t Address,
-                                      const MCDisassembler *Decoder) {
-  return DecodeMem(Inst, insn, Address, Decoder, true,
-                   DecodeIntPairRegisterClass);
-}
-
-static DecodeStatus DecodeLoadFP(MCInst &Inst, unsigned insn, uint64_t Address,
-                                 const MCDisassembler *Decoder) {
-  return DecodeMem(Inst, insn, Address, Decoder, true,
-                   DecodeFPRegsRegisterClass);
-}
-
-static DecodeStatus DecodeLoadDFP(MCInst &Inst, unsigned insn, uint64_t Address,
-                                  const MCDisassembler *Decoder) {
-  return DecodeMem(Inst, insn, Address, Decoder, true,
-                   DecodeDFPRegsRegisterClass);
-}
-
-static DecodeStatus DecodeLoadQFP(MCInst &Inst, unsigned insn, uint64_t Address,
-                                  const MCDisassembler *Decoder) {
-  return DecodeMem(Inst, insn, Address, Decoder, true,
-                   DecodeQFPRegsRegisterClass);
-}
-
-static DecodeStatus DecodeLoadCP(MCInst &Inst, unsigned insn, uint64_t Address,
-                                 const MCDisassembler *Decoder) {
-  return DecodeMem(Inst, insn, Address, Decoder, true,
-                   DecodeCPRegsRegisterClass);
-}
-
-static DecodeStatus DecodeLoadCPPair(MCInst &Inst, unsigned insn,
-                                     uint64_t Address,
-                                     const MCDisassembler *Decoder) {
-  return DecodeMem(Inst, insn, Address, Decoder, true,
-                   DecodeCPPairRegisterClass);
-}
-
-static DecodeStatus DecodeStoreInt(MCInst &Inst, unsigned insn,
-                                   uint64_t Address,
-                                   const MCDisassembler *Decoder) {
-  return DecodeMem(Inst, insn, Address, Decoder, false,
-                   DecodeIntRegsRegisterClass);
-}
-
-static DecodeStatus DecodeStoreIntPair(MCInst &Inst, unsigned insn,
-                                       uint64_t Address,
-                                       const MCDisassembler *Decoder) {
-  return DecodeMem(Inst, insn, Address, Decoder, false,
-                   DecodeIntPairRegisterClass);
-}
-
-static DecodeStatus DecodeStoreFP(MCInst &Inst, unsigned insn, uint64_t Address,
-                                  const MCDisassembler *Decoder) {
-  return DecodeMem(Inst, insn, Address, Decoder, false,
-                   DecodeFPRegsRegisterClass);
-}
-
-static DecodeStatus DecodeStoreDFP(MCInst &Inst, unsigned insn,
-                                   uint64_t Address,
-                                   const MCDisassembler *Decoder) {
-  return DecodeMem(Inst, insn, Address, Decoder, false,
-                   DecodeDFPRegsRegisterClass);
-}
-
-static DecodeStatus DecodeStoreQFP(MCInst &Inst, unsigned insn,
-                                   uint64_t Address,
-                                   const MCDisassembler *Decoder) {
-  return DecodeMem(Inst, insn, Address, Decoder, false,
-                   DecodeQFPRegsRegisterClass);
-}
-
-static DecodeStatus DecodeStoreCP(MCInst &Inst, unsigned insn, uint64_t Address,
-                                  const MCDisassembler *Decoder) {
-  return DecodeMem(Inst, insn, Address, Decoder, false,
-                   DecodeCPRegsRegisterClass);
-}
-
-static DecodeStatus DecodeStoreCPPair(MCInst &Inst, unsigned insn,
-                                      uint64_t Address,
-                                      const MCDisassembler *Decoder) {
-  return DecodeMem(Inst, insn, Address, Decoder, false,
-                   DecodeCPPairRegisterClass);
-}
-
 static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch,
                                      uint64_t Address, uint64_t Offset,
                                      uint64_t Width, MCInst &MI,
                                      const MCDisassembler *Decoder) {
   return Decoder->tryAddingSymbolicOperand(MI, Value, Address, isBranch, Offset,
                                            Width, /*InstSize=*/4);
 }
 
 static DecodeStatus DecodeCall(MCInst &MI, unsigned insn, uint64_t Address,
                                const MCDisassembler *Decoder) {
   unsigned tgt = fieldFromInstruction(insn, 0, 30);
   tgt <<= 2;
   if (!tryAddingSymbolicOperand(tgt+Address, false, Address,
                                 0, 30, MI, Decoder))
     MI.addOperand(MCOperand::createImm(tgt));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeSIMM13(MCInst &MI, unsigned insn, uint64_t Address,
                                  const MCDisassembler *Decoder) {
   unsigned tgt = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
   MI.addOperand(MCOperand::createImm(tgt));
   return MCDisassembler::Success;
 }
-
-static DecodeStatus DecodeJMPL(MCInst &MI, unsigned insn, uint64_t Address,
-                               const MCDisassembler *Decoder) {
-
-  unsigned rd = fieldFromInstruction(insn, 25, 5);
-  unsigned rs1 = fieldFromInstruction(insn, 14, 5);
-  unsigned isImm = fieldFromInstruction(insn, 13, 1);
-  unsigned rs2 = 0;
-  unsigned simm13 = 0;
-  if (isImm)
-    simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
-  else
-    rs2 = fieldFromInstruction(insn, 0, 5);
-
-  // Decode RD.
-  DecodeStatus status = DecodeIntRegsRegisterClass(MI, rd, Address, Decoder);
-  if (status != MCDisassembler::Success)
-    return status;
-
-  // Decode RS1.
-  status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
-  if (status != MCDisassembler::Success)
-    return status;
-
-  // Decode RS1 | SIMM13.
-  if (isImm)
-    MI.addOperand(MCOperand::createImm(simm13));
-  else {
-    status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
-    if (status != MCDisassembler::Success)
-      return status;
-  }
-  return MCDisassembler::Success;
-}
-
-static DecodeStatus DecodeReturn(MCInst &MI, unsigned insn, uint64_t Address,
-                                 const MCDisassembler *Decoder) {
-
-  unsigned rs1 = fieldFromInstruction(insn, 14, 5);
-  unsigned isImm = fieldFromInstruction(insn, 13, 1);
-  unsigned rs2 = 0;
-  unsigned simm13 = 0;
-  if (isImm)
-    simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
-  else
-    rs2 = fieldFromInstruction(insn, 0, 5);
-
-  // Decode RS1.
-  DecodeStatus status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
-  if (status != MCDisassembler::Success)
-    return status;
-
-  // Decode RS2 | SIMM13.
-  if (isImm)
-    MI.addOperand(MCOperand::createImm(simm13));
-  else {
-    status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
-    if (status != MCDisassembler::Success)
-      return status;
-  }
-  return MCDisassembler::Success;
-}
-
-// This instruction does not have a working decoder, and needs to be
-// fixed. This "fixme" function was introduced to keep the backend compiling,
-// while making changes to tablegen code.
-static DecodeStatus DecodeFIXMEInstruction(MCInst &Inst, unsigned Insn,
-                                           uint64_t Address,
-                                           const MCDisassembler *Decoder) {
-  return MCDisassembler::Fail;
-}
-
-static DecodeStatus DecodeSWAP(MCInst &MI, unsigned insn, uint64_t Address,
-                               const MCDisassembler *Decoder) {
-
-  unsigned rd = fieldFromInstruction(insn, 25, 5);
-  unsigned rs1 = fieldFromInstruction(insn, 14, 5);
-  unsigned isImm = fieldFromInstruction(insn, 13, 1);
-  bool hasAsi = fieldFromInstruction(insn, 23, 1); // (in op3 field)
-  unsigned asi = fieldFromInstruction(insn, 5, 8);
-  unsigned rs2 = 0;
-  unsigned simm13 = 0;
-  if (isImm)
-    simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
-  else
-    rs2 = fieldFromInstruction(insn, 0, 5);
-
-  // Decode RD.
-  DecodeStatus status = DecodeIntRegsRegisterClass(MI, rd, Address, Decoder);
-  if (status != MCDisassembler::Success)
-    return status;
-
-  // Decode RS1.
-  status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
-  if (status != MCDisassembler::Success)
-    return status;
-
-  // Decode RS1 | SIMM13.
-  if (isImm)
-    MI.addOperand(MCOperand::createImm(simm13));
-  else {
-    status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
-    if (status != MCDisassembler::Success)
-      return status;
-  }
-
-  if (hasAsi)
-    MI.addOperand(MCOperand::createImm(asi));
-
-  return MCDisassembler::Success;
-}
-
-static DecodeStatus DecodeTRAP(MCInst &MI, unsigned insn, uint64_t Address,
-                               const MCDisassembler *Decoder) {
-
-  unsigned rs1 = fieldFromInstruction(insn, 14, 5);
-  unsigned isImm = fieldFromInstruction(insn, 13, 1);
-  unsigned cc =fieldFromInstruction(insn, 25, 4);
-  unsigned rs2 = 0;
-  unsigned imm7 = 0;
-  if (isImm)
-    imm7 = fieldFromInstruction(insn, 0, 7);
-  else
-    rs2 = fieldFromInstruction(insn, 0, 5);
-
-  // Decode RS1.
-  DecodeStatus status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
-  if (status != MCDisassembler::Success)
-    return status;
-
-  // Decode RS1 | IMM7.
-  if (isImm)
-    MI.addOperand(MCOperand::createImm(imm7));
-  else {
-    status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
-    if (status != MCDisassembler::Success)
-      return status;
-  }
-
-  // Decode CC
-  MI.addOperand(MCOperand::createImm(cc));
-
-  return MCDisassembler::Success;
-}

llvm/lib/Target/Sparc/SparcInstr64Bit.td

 // zero-extended to i64. Their mnemonic is lduw in SPARC v9 (Load Unsigned
 // Word).
 //
 // SPARC v9 adds 64-bit loads as well as a sign-extending ldsw i32 loads.
 
 let Predicates = [Is64Bit] in {
 
 // 64-bit loads.
-let DecoderMethod = "DecodeLoadInt" in
-  defm LDX   : Load<"ldx", 0b001011, load, I64Regs, i64>;
 
 let mayLoad = 1, isAsmParserOnly = 1 in {
   def TLS_LDXrr : F3_1<3, 0b001011,
                        (outs IntRegs:$rd),
                        (ins (MEMrr $rs1, $rs2):$addr, TailRelocSymTLSLoad:$sym),
                        "ldx [$addr], $rd, $sym",
                        [(set i64:$rd,
                            (tlsld ADDRrr:$addr, tglobaltlsaddr:$sym))]>;

 def : Pat<(i64 (sextloadi16 ADDRri:$addr)), (LDSHri ADDRri:$addr)>;
 
 def : Pat<(i64 (zextloadi32 ADDRrr:$addr)), (LDrr ADDRrr:$addr)>;
 def : Pat<(i64 (zextloadi32 ADDRri:$addr)), (LDri ADDRri:$addr)>;
 def : Pat<(i64 (extloadi32 ADDRrr:$addr)),  (LDrr ADDRrr:$addr)>;
 def : Pat<(i64 (extloadi32 ADDRri:$addr)),  (LDri ADDRri:$addr)>;
 
 // Sign-extending load of i32 into i64 is a new SPARC v9 instruction.
-let DecoderMethod = "DecodeLoadInt" in
-  defm LDSW   : Load<"ldsw", 0b001000, sextloadi32, I64Regs, i64>;
 
 // 64-bit stores.
-let DecoderMethod = "DecodeStoreInt" in
-  defm STX    : Store<"stx", 0b001110, store,  I64Regs, i64>;
 
 // Truncating stores from i64 are identical to the i32 stores.
 def : Pat<(truncstorei8  i64:$src, ADDRrr:$addr), (STBrr ADDRrr:$addr, $src)>;
 def : Pat<(truncstorei8  i64:$src, ADDRri:$addr), (STBri ADDRri:$addr, $src)>;
 def : Pat<(truncstorei16 i64:$src, ADDRrr:$addr), (STHrr ADDRrr:$addr, $src)>;
 def : Pat<(truncstorei16 i64:$src, ADDRri:$addr), (STHri ADDRri:$addr, $src)>;
 def : Pat<(truncstorei32 i64:$src, ADDRrr:$addr), (STrr  ADDRrr:$addr, $src)>;
 def : Pat<(truncstorei32 i64:$src, ADDRri:$addr), (STri  ADDRri:$addr, $src)>;

llvm/lib/Target/Sparc/SparcInstrInfo.td

 
 def SparcMEMriAsmOperand : AsmOperandClass {
   let Name = "MEMri";
   let ParserMethod = "parseMEMOperand";
 }
 
 def MEMrr : Operand<iPTR> {
   let PrintMethod = "printMemOperand";
-  let MIOperandInfo = (ops ptr_rc:$rs1, ptr_rc:$rs2);
+  let MIOperandInfo = (ops ptr_rc, ptr_rc);
   let ParserMatchClass = SparcMEMrrAsmOperand;
 }
 def MEMri : Operand<iPTR> {
   let PrintMethod = "printMemOperand";
-  let MIOperandInfo = (ops ptr_rc:$rs1, i32imm:$simm13);
+  let MIOperandInfo = (ops ptr_rc, i32imm);
   let ParserMatchClass = SparcMEMriAsmOperand;
 }
 
 // Represents a tail relocation operand for instructions such as add, ld, call.
 class SparcTailRelocSymAsmOperand<string Kind> : AsmOperandClass {
   let Name = "TailRelocSym" # Kind;
   let RenderMethod = "addTailRelocSymOperands";
   let PredicateMethod = "isTailRelocSym";
multiclass LoadA<string OpcStr, bits<6> Op3Val, bits<6> LoadAOp3Val,
                  InstrItinClass itin = NoItinerary> :
              Load<OpcStr, Op3Val, OpNode, RC, Ty, itin> {
   def Arr  : LoadASI<OpcStr, LoadAOp3Val, RC>;
 }
 
 // The LDSTUB instruction is supported for asm only.
 // It is unlikely that general-purpose code could make use of it.
 // CAS is preferred for sparc v9.
-let DecoderMethod = "DecodeFIXMEInstruction" in {
 def LDSTUBrr : F3_1<3, 0b001101, (outs IntRegs:$rd), (ins (MEMrr $rs1, $rs2):$addr),
                     "ldstub [$addr], $rd", []>;
 def LDSTUBri : F3_2<3, 0b001101, (outs IntRegs:$rd), (ins (MEMri $rs1, $simm13):$addr),
                     "ldstub [$addr], $rd", []>;
 def LDSTUBArr : F3_1_asi<3, 0b011101, (outs IntRegs:$rd),
                          (ins (MEMrr $rs1, $rs2):$addr, i8imm:$asi),
                          "ldstuba [$addr] $asi, $rd", []>;
-}
 
 // Store multiclass - Define both Reg+Reg/Reg+Imm patterns in one shot.
 multiclass Store<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode,
            RegisterClass RC, ValueType Ty, InstrItinClass itin = IIC_st> {
   def rr  : F3_1<3, Op3Val,
                  (outs), (ins (MEMrr $rs1, $rs2):$addr, RC:$rd),
                  !strconcat(OpcStr, " $rd, [$addr]"),
                  [(OpNode Ty:$rd, ADDRrr:$addr)],
: Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
             [(set f64:$dst, (SPselectfcc f64:$T, f64:$F, imm:$Cond))]>;
   def SELECT_CC_QFP_FCC
    : Pseudo<(outs QFPRegs:$dst), (ins QFPRegs:$T, QFPRegs:$F, i32imm:$Cond),
             "; SELECT_CC_QFP_FCC PSEUDO!",
             [(set f128:$dst, (SPselectfcc f128:$T, f128:$F, imm:$Cond))]>;
 }
 
 // Section B.1 - Load Integer Instructions, p. 90
-let DecoderMethod = "DecodeLoadInt" in {
-  defm LDSB : LoadA<"ldsb", 0b001001, 0b011001, sextloadi8,  IntRegs, i32>;
-  defm LDSH : LoadA<"ldsh", 0b001010, 0b011010, sextloadi16, IntRegs, i32>;
-  defm LDUB : LoadA<"ldub", 0b000001, 0b010001, zextloadi8,  IntRegs, i32>;
-  defm LDUH : LoadA<"lduh", 0b000010, 0b010010, zextloadi16, IntRegs, i32>;
-  defm LD   : LoadA<"ld",   0b000000, 0b010000, load,        IntRegs, i32>;
-}
-
-let DecoderMethod = "DecodeLoadIntPair" in
-  defm LDD : LoadA<"ldd", 0b000011, 0b010011, load, IntPair, v2i32, IIC_ldd>;
 
 // Section B.2 - Load Floating-point Instructions, p. 92
-let DecoderMethod = "DecodeLoadFP" in {
-  defm LDF   : Load<"ld",  0b100000, load,    FPRegs,  f32, IIC_iu_or_fpu_instr>;
-  def LDFArr : LoadASI<"ld",  0b110000, FPRegs>,
-                Requires<[HasV9]>;
-}
-let DecoderMethod = "DecodeLoadDFP" in {
-  defm LDDF   : Load<"ldd", 0b100011, load,    DFPRegs, f64, IIC_ldd>;
-  def LDDFArr : LoadASI<"ldd", 0b110011, DFPRegs>,
-                 Requires<[HasV9]>;
-}
-let DecoderMethod = "DecodeLoadQFP" in
-  defm LDQF  : LoadA<"ldq", 0b100010, 0b110010, load, QFPRegs, f128>,
-               Requires<[HasV9, HasHardQuad]>;
+
 
-let DecoderMethod = "DecodeLoadCP" in
-  defm LDC   : Load<"ld", 0b110000, load, CoprocRegs, i32>;
-let DecoderMethod = "DecodeLoadCPPair" in
-  defm LDDC   : Load<"ldd", 0b110011, load, CoprocPair, v2i32, IIC_ldd>;
 
-let DecoderMethod = "DecodeLoadCP", Defs = [CPSR] in {
+let Defs = [CPSR] in {
   let rd = 0 in {
     def LDCSRrr : F3_1<3, 0b110001, (outs), (ins (MEMrr $rs1, $rs2):$addr),
                        "ld [$addr], %csr", []>;
     def LDCSRri : F3_2<3, 0b110001, (outs), (ins (MEMri $rs1, $simm13):$addr),
                        "ld [$addr], %csr", []>;
   }
 }
 
-let DecoderMethod = "DecodeLoadFP" in
-  let Defs = [FSR] in {
-    let rd = 0 in {
-      def LDFSRrr : F3_1<3, 0b100001, (outs), (ins (MEMrr $rs1, $rs2):$addr),
-                     "ld [$addr], %fsr", [], IIC_iu_or_fpu_instr>;
-      def LDFSRri : F3_2<3, 0b100001, (outs), (ins (MEMri $rs1, $simm13):$addr),
-                     "ld [$addr], %fsr", [], IIC_iu_or_fpu_instr>;
-    }
-    let rd = 1 in {
-      def LDXFSRrr : F3_1<3, 0b100001, (outs), (ins (MEMrr $rs1, $rs2):$addr),
-                     "ldx [$addr], %fsr", []>, Requires<[HasV9]>;
-      def LDXFSRri : F3_2<3, 0b100001, (outs), (ins (MEMri $rs1, $simm13):$addr),
-                     "ldx [$addr], %fsr", []>, Requires<[HasV9]>;
-    }
-  }
+       "ld [$addr], %fsr", [], IIC_iu_or_fpu_instr>;
+       "ld [$addr], %fsr", [], IIC_iu_or_fpu_instr>;
+       "ldx [$addr], %fsr", []>, Requires<[HasV9]>;
+       "ldx [$addr], %fsr", []>, Requires<[HasV9]>;
 
 let mayLoad = 1, isAsmParserOnly = 1 in {
   def GDOP_LDrr : F3_1<3, 0b000000,
                       (outs IntRegs:$rd),
                       (ins (MEMrr $rs1, $rs2):$addr, TailRelocSymGOTLoad:$sym),
                       "ld [$addr], $rd, $sym",
                       [(set i32:$rd,
                           (load_gdop ADDRrr:$addr, tglobaladdr:$sym))]>;
 }
 
 // Section B.4 - Store Integer Instructions, p. 95
-let DecoderMethod = "DecodeStoreInt" in {
-  defm STB   : StoreA<"stb", 0b000101, 0b010101, truncstorei8,  IntRegs, i32>;
-  defm STH   : StoreA<"sth", 0b000110, 0b010110, truncstorei16, IntRegs, i32>;
-  defm ST    : StoreA<"st",  0b000100, 0b010100, store,         IntRegs, i32>;
-}
-
-let DecoderMethod = "DecodeStoreIntPair" in
-  defm STD   : StoreA<"std", 0b000111, 0b010111, store, IntPair, v2i32>;
 
 // Section B.5 - Store Floating-point Instructions, p. 97
-let DecoderMethod = "DecodeStoreFP" in {
-  defm STF   : Store<"st",  0b100100, store,         FPRegs,  f32>;
-  def STFArr : StoreASI<"st",  0b110100, FPRegs>,
-               Requires<[HasV9]>;
-}
-let DecoderMethod = "DecodeStoreDFP" in {
-  defm STDF   : Store<"std", 0b100111, store,         DFPRegs, f64, IIC_std>;
-  def STDFArr : StoreASI<"std", 0b110111, DFPRegs>,
-                Requires<[HasV9]>;
-}
-let DecoderMethod = "DecodeStoreQFP" in
-  defm STQF  : StoreA<"stq", 0b100110, 0b110110, store, QFPRegs, f128>,
-               Requires<[HasV9, HasHardQuad]>;
+defm STF    : Store<"st",  0b100100, store,         FPRegs,  f32>;
+def STFArr  : StoreASI<"st",  0b110100, FPRegs>,
+defm STQF   : StoreA<"stq", 0b100110, 0b110110, store, QFPRegs, f128>,
 
-let DecoderMethod = "DecodeStoreCP" in
-  defm STC   : Store<"st", 0b110100, store, CoprocRegs, i32>;
-
-let DecoderMethod = "DecodeStoreCPPair" in
-  defm STDC   : Store<"std", 0b110111, store, CoprocPair, v2i32, IIC_std>;
 
-let DecoderMethod = "DecodeStoreCP", rd = 0 in {
+let rd = 0 in {
   let Defs = [CPSR] in {
     def STCSRrr : F3_1<3, 0b110101, (outs (MEMrr $rs1, $rs2):$addr), (ins),
                        "st %csr, [$addr]", [], IIC_st>;
     def STCSRri : F3_2<3, 0b110101, (outs (MEMri $rs1, $simm13):$addr), (ins),
                        "st %csr, [$addr]", [], IIC_st>;
   }
   let Defs = [CPQ] in {
     def STDCQrr : F3_1<3, 0b110110, (outs (MEMrr $rs1, $rs2):$addr), (ins),
                        "std %cq, [$addr]", [], IIC_std>;
     def STDCQri : F3_2<3, 0b110110, (outs (MEMri $rs1, $simm13):$addr), (ins),
                        "std %cq, [$addr]", [], IIC_std>;
   }
 }
 
-let DecoderMethod = "DecodeStoreFP" in {
-  let rd = 0 in {
-    let Defs = [FSR] in {
-      def STFSRrr : F3_1<3, 0b100101, (outs (MEMrr $rs1, $rs2):$addr), (ins),
-                     "st %fsr, [$addr]", [], IIC_st>;
-      def STFSRri : F3_2<3, 0b100101, (outs (MEMri $rs1, $simm13):$addr), (ins),
-                     "st %fsr, [$addr]", [], IIC_st>;
-    }
-    let Defs = [FQ] in {
-      def STDFQrr : F3_1<3, 0b100110, (outs (MEMrr $rs1, $rs2):$addr), (ins),
-                     "std %fq, [$addr]", [], IIC_std>;
-      def STDFQri : F3_2<3, 0b100110, (outs (MEMri $rs1, $simm13):$addr), (ins),
-                     "std %fq, [$addr]", [], IIC_std>;
-    }
-  }
-  let rd = 1, Defs = [FSR] in {
-    def STXFSRrr : F3_1<3, 0b100101, (outs (MEMrr $rs1, $rs2):$addr), (ins),
-                   "stx %fsr, [$addr]", []>, Requires<[HasV9]>;
-    def STXFSRri : F3_2<3, 0b100101, (outs (MEMri $rs1, $simm13):$addr), (ins),
-                   "stx %fsr, [$addr]", []>, Requires<[HasV9]>;
-  }
-}
+       "st %fsr, [$addr]", [], IIC_st>;
+       "st %fsr, [$addr]", [], IIC_st>;
+       "std %fq, [$addr]", [], IIC_std>;
+       "std %fq, [$addr]", [], IIC_std>;
+     "stx %fsr, [$addr]", []>, Requires<[HasV9]>;
+     "stx %fsr, [$addr]", []>, Requires<[HasV9]>;
 
 // Section B.8 - SWAP Register with Memory Instruction
 // (Atomic swap)
-let Constraints = "$val = $rd", DecoderMethod = "DecodeSWAP" in {
+let Constraints = "$val = $rd" in {
   def SWAPrr : F3_1<3, 0b001111,
                  (outs IntRegs:$rd), (ins (MEMrr $rs1, $rs2):$addr, IntRegs:$val),
                  "swap [$addr], $rd",
                  [(set i32:$rd, (atomic_swap_32 ADDRrr:$addr, i32:$val))]>;
   def SWAPri : F3_2<3, 0b001111,
                  (outs IntRegs:$rd), (ins (MEMri $rs1, $simm13):$addr, IntRegs:$val),
                  "swap [$addr], $rd",
                  [(set i32:$rd, (atomic_swap_32 ADDRri:$addr, i32:$val))]>;
def CALLri : F3_2<2, 0b111000,
                       [(call ADDRri:$addr)],
                       IIC_jmp_or_call>;
   }
 }
 
 // Section B.25 - Jump and Link Instruction
 
 // JMPL Instruction.
-let isTerminator = 1, hasDelaySlot = 1, isBarrier = 1,
-    DecoderMethod = "DecodeJMPL" in {
+let isTerminator = 1, hasDelaySlot = 1, isBarrier = 1 in {
   def JMPLrr: F3_1<2, 0b111000,
                    (outs IntRegs:$rd), (ins (MEMrr $rs1, $rs2):$addr),
                    "jmpl $addr, $rd",
                    [],
                    IIC_jmp_or_call>;
   def JMPLri: F3_2<2, 0b111000,
                    (outs IntRegs:$rd), (ins (MEMri $rs1, $simm13):$addr),
                    "jmpl $addr, $rd",
def RET: F3_2<2, 0b111000,
                   (outs), (ins i32imm:$simm13),
                   "jmp %i7+$simm13",
                   [],
                   IIC_jmp_or_call>;
 }
 
 // Section B.26 - Return from Trap Instruction
 let isReturn = 1, isTerminator = 1, hasDelaySlot = 1,
-     isBarrier = 1, rd = 0, DecoderMethod = "DecodeReturn" in {
+     isBarrier = 1, rd = 0 in {
   def RETTrr : F3_1<2, 0b111001,
                    (outs), (ins (MEMrr $rs1, $rs2):$addr),
                    "rett $addr",
                    [],
                    IIC_jmp_or_call>;
   def RETTri : F3_2<2, 0b111001,
                     (outs), (ins (MEMri $rs1, $simm13):$addr),
                     "rett $addr",
                     [],
                     IIC_jmp_or_call>;
 }
 
 
 // Section B.27 - Trap on Integer Condition Codes Instruction
 // conditional branch class:
-let DecoderNamespace = "SparcV8", DecoderMethod = "DecodeTRAP", hasSideEffects = 1, Uses = [ICC], cc = 0b00 in
+let DecoderNamespace = "SparcV8", hasSideEffects = 1, Uses = [ICC], cc = 0b00 in
 {
   def TRAPrr : TRAPSPrr<0b111010,
                         (outs), (ins IntRegs:$rs1, IntRegs:$rs2, CCOp:$cond),
                         "t$cond $rs1 + $rs2",
                         []>;
   def TRAPri : TRAPSPri<0b111010,
                         (outs), (ins IntRegs:$rs1, i32imm:$imm, CCOp:$cond),
                         "t$cond $rs1 + $imm",
                         []>;
 }
 
 multiclass TRAP<string regStr> {
   def rr : TRAPSPrr<0b111010,
                     (outs), (ins IntRegs:$rs1, IntRegs:$rs2, CCOp:$cond),
                     !strconcat(!strconcat("t$cond ", regStr), ", $rs1 + $rs2"),
                     []>;
   def ri : TRAPSPri<0b111010,
                     (outs), (ins IntRegs:$rs1, i32imm:$imm, CCOp:$cond),
                     !strconcat(!strconcat("t$cond ", regStr), ", $rs1 + $imm"),
                     []>;
 }
 
-let DecoderNamespace = "SparcV9", DecoderMethod = "DecodeTRAP", Predicates = [HasV9], hasSideEffects = 1, Uses = [ICC], cc = 0b00 in
+let DecoderNamespace = "SparcV9", Predicates = [HasV9], hasSideEffects = 1, Uses = [ICC], cc = 0b00 in
   defm TICC : TRAP<"%icc">;
 
 
 let isBarrier = 1, isTerminator = 1, rd = 0b01000, rs1 = 0, simm13 = 5 in
   def TA5 : F3_2<0b10, 0b111010, (outs), (ins), "ta 5", [(trap)]>;
 
 let hasSideEffects = 1, rd = 0b01000, rs1 = 0, simm13 = 1 in
   def TA1 : F3_2<0b10, 0b111010, (outs), (ins), "ta 1", [(debugtrap)]>;

 
 
 // Section B.31 - Unimplemented Instruction
 let rd = 0 in
   def UNIMP : F2_1<0b000, (outs), (ins i32imm:$imm22),
                   "unimp $imm22", []>;
 
 // Section B.32 - Flush Instruction Memory
-let DecoderMethod = "DecodeFIXMEInstruction", rd = 0 in {
+let rd = 0 in {
   def FLUSHrr : F3_1<2, 0b111011, (outs), (ins (MEMrr $rs1, $rs2):$addr),
                        "flush $addr", []>;
   def FLUSHri : F3_2<2, 0b111011, (outs), (ins (MEMri $rs1, $simm13):$addr),
                        "flush $addr", []>;
 
   // The no-arg FLUSH is only here for the benefit of the InstAlias
   // "flush", which cannot seem to use FLUSHrr, due to the inability
   // to construct a MEMrr with fixed G0 registers.

 
 let hasSideEffects = 1 in {
   defm TADDCCTV : F3_12np<"taddcctv", 0b100010>;
   defm TSUBCCTV : F3_12np<"tsubcctv", 0b100011>;
 }
 }
 
 // Section A.42 - Prefetch Data
-let DecoderMethod = "DecodeFIXMEInstruction", Predicates = [HasV9] in {
+let Predicates = [HasV9] in {
   def PREFETCHr : F3_1<3, 0b101101,
                    (outs), (ins (MEMrr $rs1, $rs2):$addr, shift_imm5:$rd),
                    "prefetch [$addr], $rd", []>;
   def PREFETCHi : F3_2<3, 0b101101,
                    (outs), (ins (MEMri $rs1, $simm13):$addr, shift_imm5:$rd),
                    "prefetch [$addr], $rd", []>;
 }
 

llvm/test/MC/Disassembler/Sparc/sparc-coproc.txt

+# RUN: llvm-mc --disassemble %s -triple=sparcv9-unknown-linux | FileCheck %s
+
+# CHECK:      ld [%i0+%l6], %c10
+0xd5 0x86 0x00 0x16
+
+# CHECK:      ld [%i0+32], %c10
+0xd5 0x86 0x20 0x20
+
+# CHECK:      ld [%g1], %c10
+0xd5 0x80 0x60 0x00
+
+# CHECK:      ld [%g1], %c10
+0xd5 0x80 0x40 0x00
+
+# CHECK:      st %c10, [%i0+%l6]
+0xd5 0xa6 0x00 0x16
+
+# CHECK:      st %c10, [%i0+32]
+0xd5 0xa6 0x20 0x20
+
+# CHECK:      st %c10, [%g1]
+0xd5 0xa0 0x60 0x00
+
+# CHECK:      st %c10, [%g1]
+0xd5 0xa0 0x40 0x00
+
+# CHECK:     ldd [%i0+%l6], %c10
+0xd5 0x9e 0x00 0x16
+
+# CHECK:     ldd [%i0+32], %c10
+0xd5 0x9e 0x20 0x20
+
+# CHECK:     ldd [%g1], %c10
+0xd5 0x98 0x60 0x00
+
+# CHECK:     ldd [%g1], %c10
+0xd5 0x98 0x40 0x00
+
+# CHECK:     std %c10, [%i0+%l6]
+0xd5 0xbe 0x00 0x16
+
+# CHECK:     std %c10, [%i0+32]
+0xd5 0xbe 0x20 0x20
+
+# CHECK:     std %c10, [%g1]
+0xd5 0xb8 0x60 0x00
+
+# CHECK:     std %c10, [%g1]
+0xd5 0xb8 0x40 0x00
+
+# CHECK:      ld [%i0+%l6], %csr
+0xc1 0x8e 0x00 0x16
+
+# CHECK:      ld [%i0+32], %csr
+0xc1 0x8e 0x20 0x20
+
+# CHECK:      ld [%g1], %csr
+0xc1 0x88 0x60 0x00
+
+# CHECK:      ld [%g1], %csr
+0xc1 0x88 0x40 0x00
+
+# CHECK:      st %csr, [%i0+%l6]
+0xc1 0xae 0x00 0x16
+
+# CHECK:      st %csr, [%i0+32]
+0xc1 0xae 0x20 0x20
+
+# CHECK:      st %csr, [%g1]
+0xc1 0xa8 0x60 0x00
+
+# CHECK:      st %csr, [%g1]
+0xc1 0xa8 0x40 0x00
+
+# CHECK:      std %cq, [%i0+%l6]
+0xc1 0xb6 0x00 0x16
+
+# CHECK:      std %cq, [%i0+32]
+0xc1 0xb6 0x20 0x20
+
+# CHECK:      std %cq, [%g1]
+0xc1 0xb0 0x60 0x00
+
+# CHECK:      std %cq, [%g1]
+0xc1 0xb0 0x40 0x00

llvm/test/MC/Disassembler/Sparc/sparc-mem.txt

 # RUN: llvm-mc --disassemble %s -triple=sparcv9-unknown-linux | FileCheck %s
 
 # CHECK:      ldsb [%i0+%l6], %o2
 0xd4 0x4e 0x00 0x16
 
 # CHECK:      ldsb [%i0+32], %o2
 0xd4 0x4e 0x20 0x20
 
 # CHECK:      ldsb [%g1], %o4
 0xd8 0x48 0x60 0x00
 
 # CHECK:      ldsb [%g1], %o4
 0xd8 0x48 0x40 0x00
 
+# CHECK:      ldsba [%i0+%l6] 131, %o2
+0xd4 0xce 0x10 0x76
+
 # CHECK:      ldsh [%i0+%l6], %o2
 0xd4 0x56 0x00 0x16
 
 # CHECK:      ldsh [%i0+32], %o2
 0xd4 0x56 0x20 0x20
 
 # CHECK:      ldsh [%g1], %o4
 0xd8 0x50 0x60 0x00
 
 # CHECK:      ldsh [%g1], %o4
 0xd8 0x50 0x40 0x00
 
+# CHECK:      ldsha [%i0+%l6] 131, %o2
+0xd4 0xd6 0x10 0x76
+
 # CHECK:      ldub [%i0+%l6], %o2
 0xd4 0x0e 0x00 0x16
 
 # CHECK:      ldub [%i0+32], %o2
 0xd4 0x0e 0x20 0x20
 
 # CHECK:      ldub [%g1], %o2
 0xd4 0x08 0x60 0x00
 
 # CHECK:      ldub [%g1], %o2
 0xd4 0x08 0x40 0x00
 
+# CHECK:      lduba [%i0+%l6] 131, %o2
+0xd4 0x8e 0x10 0x76
+
 # CHECK:      lduh [%i0+%l6], %o2
 0xd4 0x16 0x00 0x16
 
 # CHECK:      lduh [%i0+32], %o2
 0xd4 0x16 0x20 0x20
 
 # CHECK:      lduh [%g1], %o2
 0xd4 0x10 0x60 0x00
 
 # CHECK:      lduh [%g1], %o2
 0xd4 0x10 0x40 0x00
 
+# CHECK:      lduha [%i0+%l6] 131, %o2
+0xd4 0x96 0x10 0x76
+
 # CHECK:      ld [%i0+%l6], %o2
 0xd4 0x06 0x00 0x16
 
 # CHECK:      ld [%i0+32], %o2
 0xd4 0x06 0x20 0x20
 
 # CHECK:      ld [%g1], %o2
 0xd4 0x00 0x60 0x00
 
 # CHECK:      ld [%g1], %o2
 0xd4 0x00 0x40 0x00
 
+# CHECK:      lda [%i0+%l6] 131, %o2
+0xd4 0x86 0x10 0x76
+
 # CHECK:     ld [%i0+%l6], %f2
 0xc5 0x06 0x00 0x16
 
 # CHECK:     ld [%i0+32], %f2
 0xc5 0x06 0x20 0x20
 
 # CHECK:     ld [%g1], %f2
 0xc5 0x00 0x60 0x00
 
 # CHECK:     ld [%g1], %f2
 0xc5 0x00 0x40 0x00
 
+# CHECK:     lda [%i0+%l6] 131, %f2
+0xc5 0x86 0x10 0x76
+
 # CHECK:     ldd [%i0+%l6], %f2
 0xc5 0x1e 0x00 0x16
 
 # CHECK:     ldd [%i0+32], %f2
 0xc5 0x1e 0x20 0x20
 
 # CHECK:     ldd [%g1], %f2
 0xc5 0x18 0x60 0x00
 
 # CHECK:     ldd [%g1], %f2
 0xc5 0x18 0x40 0x00
 
+# CHECK:     ldda [%i0+%l6] 131, %f2
+0xc5 0x9e 0x10 0x76
+
 # CHECK:     ldq [%i0+%l6], %f4
 0xc9 0x16 0x00 0x16
 
 # CHECK:     ldq [%i0+32], %f4
 0xc9 0x16 0x20 0x20
 
 # CHECK:     ldq [%g1], %f4
 0xc9 0x10 0x60 0x00

 0xd4 0x2e 0x20 0x20
 
 # CHECK:      stb %o2, [%g1]
 0xd4 0x28 0x60 0x00
 
 # CHECK:      stb %o2, [%g1]
 0xd4 0x28 0x40 0x00
 
+# CHECK:      stba %o2, [%i0+%l6] 131
+0xd4 0xae 0x10 0x76
+
 # CHECK:      sth %o2, [%i0+%l6]
 0xd4 0x36 0x00 0x16
 
 # CHECK:      sth %o2, [%i0+32]
 0xd4 0x36 0x20 0x20
 
 # CHECK:      sth %o2, [%g1]
 0xd4 0x30 0x60 0x00
 
 # CHECK:      sth %o2, [%g1]
 0xd4 0x30 0x40 0x00
 
+# CHECK:      stha %o2, [%i0+%l6] 131
+0xd4 0xb6 0x10 0x76
+
 # CHECK:      st %o2, [%i0+%l6]
 0xd4 0x26 0x00 0x16
 
 # CHECK:      st %o2, [%i0+32]
 0xd4 0x26 0x20 0x20
 
 # CHECK:      st %o2, [%g1]
 0xd4 0x20 0x60 0x00
 
 # CHECK:      st %o2, [%g1]
 0xd4 0x20 0x40 0x00
 
+# CHECK:      sta %o2, [%i0+%l6] 131
+0xd4 0xa6 0x10 0x76
+
 # CHECK:      st %f2, [%i0+%l6]
 0xc5 0x26 0x00 0x16
 
 # CHECK:      st %f2, [%i0+32]
 0xc5 0x26 0x20 0x20
 
 # CHECK:      st %f2, [%g1]
 0xc5 0x20 0x60 0x00
 
 # CHECK:      st %f2, [%g1]
 0xc5 0x20 0x40 0x00
 
+# CHECK:      sta %f2, [%i0+%l6] 131
+0xc5 0xa6 0x10 0x76
+
 # CHECK:      std %f2, [%i0+%l6]
 0xc5 0x3e 0x00 0x16
 
 # CHECK:      std %f2, [%i0+32]
 0xc5 0x3e 0x20 0x20
 
 # CHECK:      std %f2, [%g1]
 0xc5 0x38 0x60 0x00
 
 # CHECK:      std %f2, [%g1]
 0xc5 0x38 0x40 0x00
 
+# CHECK:      stda %f2, [%i0+%l6] 131
+0xc5 0xbe 0x10 0x76
+
 # CHECK:      stq %f4, [%i0+%l6]
 0xc9 0x36 0x00 0x16
 
 # CHECK:      stq %f4, [%i0+32]
 0xc9 0x36 0x20 0x20
 
 # CHECK:      stq %f4, [%g1]
 0xc9 0x30 0x60 0x00

 # CHECK:     std %o2, [%i0+32]
 0xd4 0x3e 0x20 0x20
 
 # CHECK:     std %o2, [%g1]
 0xd4 0x38 0x60 0x00
 
 # CHECK:     std %o2, [%g1]
 0xd4 0x38 0x40 0x00
+
+# CHECK:     stda %o2, [%i0+%l6] 131
+0xd4 0xbe 0x10 0x76
+
+# CHECK:     ldstub [%i0+%l6], %o2
+0xd4 0x6e 0x00 0x16
+
+# CHECK:     ldstub [%i0+32], %o2
+0xd4 0x6e 0x20 0x20
+
+# CHECK:     ldstub [%g1], %o2
+0xd4 0x68 0x60 0x00
+
+# CHECK:     ldstub [%g1], %o2
+0xd4 0x68 0x40 0x00
+
+# CHECK:     ldstuba [%i0+%l6] 131, %o2
+0xd4 0xee 0x10 0x76
+
+# CHECK:     ldstuba [%g1] 131, %o2
+0xd4 0xe8 0x50 0x60
+
+# CHECK:     flush %g1+%g2
+0x81 0xd8 0x40 0x02
+
+# CHECK:     flush %g1+8
+0x81 0xd8 0x60 0x08
+
+# CHECK:     flush %g1
+0x81 0xd8 0x40 0x00
+
+# CHECK:     flush %g1
+0x81 0xd8 0x60 0x00
+
+# CHECK:     ld [%i0+%l6], %fsr
+0xc1 0x0e 0x00 0x16
+
+# CHECK:     ld [%i0+32], %fsr
+0xc1 0x0e 0x20 0x20
+
+# CHECK:     ld [%g1], %fsr
+0xc1 0x08 0x60 0x00
+
+# CHECK:     ld [%g1], %fsr
+0xc1 0x08 0x40 0x00
+
+# CHECK:      st %fsr, [%i0+%l6]
+0xc1 0x2e 0x00 0x16
+
+# CHECK:      st %fsr, [%i0+32]
+0xc1 0x2e 0x20 0x20
+
+# CHECK:      st %fsr, [%g1]
+0xc1 0x28 0x60 0x00
+
+# CHECK:      st %fsr, [%g1]
+0xc1 0x28 0x40 0x00
+
+# CHECK:     ldx [%i0+%l6], %fsr
+0xc3 0x0e 0x00 0x16
+
+# CHECK:     ldx [%i0+32], %fsr
+0xc3 0x0e 0x20 0x20
+
+# CHECK:     ldx [%g1], %fsr
+0xc3 0x08 0x60 0x00
+
+# CHECK:     ldx [%g1], %fsr
+0xc3 0x08 0x40 0x00
+
+# CHECK:      stx %fsr, [%i0+%l6]
+0xc3 0x2e 0x00 0x16
+
+# CHECK:      stx %fsr, [%i0+32]
+0xc3 0x2e 0x20 0x20
+
+# CHECK:      stx %fsr, [%g1]
+0xc3 0x28 0x60 0x00
+
+# CHECK:      stx %fsr, [%g1]
+0xc3 0x28 0x40 0x00

llvm/test/MC/Disassembler/Sparc/sparc-special-registers.txt

 0x81 0x96 0x20 0x05
 
 # CHECK: wr %i0, 5, %tbr
 0x81 0x9e 0x20 0x05
 
 # CHECK: st %fsr, [%i5]
 0xc1 0x2f 0x40 0x00
 
-# CHECK: st %csr, [%i5]
-0xc1 0xaf 0x40 0x00
-
-# CHECK: std %cq, [%o3+-93]
-0xc1 0xb2 0xff 0xa3
-
 # CHECK: std %fq, [%i5+%l1]
 0xc1 0x37 0x40 0x11

llvm/test/MC/Disassembler/Sparc/sparc-v9.txt

 # CHECK: membar #LoadLoad
 0x81 0x43 0xe0 0x01
 
 # CHECK: membar #LoadLoad | #StoreStore
 0x81 0x43 0xe0 0x09
 
 # CHECK: membar #LoadLoad | #StoreLoad | #LoadStore | #StoreStore | #Lookaside | #MemIssue | #Sync
 0x81 0x43 0xe0 0x7f
+
+# CHECK: prefetch  [%i1+3968], 1
+0xc3,0x6e,0x6f,0x80
+
+# CHECK: prefetch  [%i1+%i2], 1
+0xc3,0x6e,0x40,0x1a

llvm/test/MC/Disassembler/Sparc/sparc.txt

 0x81 0xc3 0xe0 0x08
 
 # CHECK: ret
 0x81 0xc7 0xe0 0x08
 
 # CHECK:  rett %i7+8
 0x81 0xcf 0xe0 0x08
 
+# CHECK:  rett %i7+%i0
+0x81 0xcf 0xc0 0x18
+
 # CHECK: stbar
 0x81 0x43 0xc0 0x00
 
 # CHECK: ta %i5
 0x91 0xd0 0x00 0x1d
 
 # CHECK: ta 82
 0x91 0xd0 0x20 0x52