[PowerPC] Switch to by-name matching for instructions (part 2 of 2).

[jyknight]

Summary

Currently, all of the "memri"-style complex operands, which contain
both a register and an immediate, are encoded into a single field in
the instruction definition. This requires complex encoders/decoders,
and instruction definitions that insert and extract the correct parts
of the bits.

Now, switch to naming and encoding/decoding the sub-operands
separately.

Thus, we can now disable useDeprecatedPositionallyEncodedOperands.

[jyknight]

Rebase

[jyknight]

Rebase.

[barannikov88]

LGTM with one note

llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp

242

The new version lacks the assertion. Does it make sense to add an EncoderMethod to immZero just for this?

[jyknight]

Thanks for the reviews!

llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp

242

Verification in an encoder method that the MachineInstruction operand has a valid value is not typically done currently, for other kinds of operands. E.g. u5imm/etc don't have an EncoderMethod. Nor do other backends e.g. aarch64's simm8_32b/etc.

So I think it's probably not needed here, either.

llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp

static DecodeStatus decodeVSRpEvenOperands(MCInst &Inst, uint64_t RegNo,
                                            uint64_t Address,
                                            const MCDisassembler *Decoder) {
   if (RegNo & 1)
     return MCDisassembler::Fail;
   Inst.addOperand(MCOperand::createReg(VSRpRegs[RegNo >> 1]));
   return MCDisassembler::Success;
 }
 
-static DecodeStatus decodeMemRIOperands(MCInst &Inst, uint64_t Imm,
+static DecodeStatus decodeDispRIXOperand(MCInst &Inst, uint64_t Imm,
                                          int64_t Address,
                                          const MCDisassembler *Decoder) {
-  // Decode the memri field (imm, reg), which has the low 16-bits as the
-  // displacement and the next 5 bits as the register #.
-
-  uint64_t Base = Imm >> 16;
-  uint64_t Disp = Imm & 0xFFFF;
-
-  assert(Base < 32 && "Invalid base register");
-
-  switch (Inst.getOpcode()) {
-  default: break;
-  case PPC::LBZU:
-  case PPC::LHAU:
-  case PPC::LHZU:
-  case PPC::LWZU:
-  case PPC::LFSU:
-  case PPC::LFDU:
-    // Add the tied output operand.
-    Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
-    break;
-  case PPC::STBU:
-  case PPC::STHU:
-  case PPC::STWU:
-  case PPC::STFSU:
-  case PPC::STFDU:
-    Inst.insert(Inst.begin(), MCOperand::createReg(RRegsNoR0[Base]));
-    break;
-  }
-
-  Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp)));
-  Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
-  return MCDisassembler::Success;
-}
-
-static DecodeStatus decodeMemRIXOperands(MCInst &Inst, uint64_t Imm,
-                                         int64_t Address,
-                                         const MCDisassembler *Decoder) {
-  // Decode the memrix field (imm, reg), which has the low 14-bits as the
-  // displacement and the next 5 bits as the register #.
-
-  uint64_t Base = Imm >> 14;
-  uint64_t Disp = Imm & 0x3FFF;
-
-  assert(Base < 32 && "Invalid base register");
-
-  if (Inst.getOpcode() == PPC::LDU)
-    // Add the tied output operand.
-    Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
-  else if (Inst.getOpcode() == PPC::STDU)
-    Inst.insert(Inst.begin(), MCOperand::createReg(RRegsNoR0[Base]));
-
-  Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp << 2)));
-  Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
+  // The rix displacement is an immediate shifted by 2
+  Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Imm << 2)));
   return MCDisassembler::Success;
 }
 
-static DecodeStatus decodeMemRIHashOperands(MCInst &Inst, uint64_t Imm,
+static DecodeStatus decodeDispRIHashOperand(MCInst &Inst, uint64_t Imm,
                                             int64_t Address,
                                             const MCDisassembler *Decoder) {
-  // Decode the memrix field for a hash store or hash check operation.
-  // The field is composed of a register and an immediate value that is 6 bits
+  // Decode the disp field for a hash store or hash check operation.
+  // The field is composed of an immediate value that is 6 bits
   // and covers the range -8 to -512. The immediate is always negative and 2s
   // complement which is why we sign extend a 7 bit value.
-  const uint64_t Base = Imm >> 6;
   const int64_t Disp = SignExtend64<7>((Imm & 0x3F) + 64) * 8;
 
-  assert(Base < 32 && "Invalid base register");
-
   Inst.addOperand(MCOperand::createImm(Disp));
-  Inst.addOperand(MCOperand::createReg(RRegs[Base]));
   return MCDisassembler::Success;
 }
 
-static DecodeStatus decodeMemRIX16Operands(MCInst &Inst, uint64_t Imm,
+static DecodeStatus decodeDispRIX16Operand(MCInst &Inst, uint64_t Imm,
                                            int64_t Address,
                                            const MCDisassembler *Decoder) {
-  // Decode the memrix16 field (imm, reg), which has the low 12-bits as the
-  // displacement with 16-byte aligned, and the next 5 bits as the register #.
-
-  uint64_t Base = Imm >> 12;
-  uint64_t Disp = Imm & 0xFFF;
-
-  assert(Base < 32 && "Invalid base register");
-
-  Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp << 4)));
-  Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
+  // The rix16 displacement has 12-bits which are shifted by 4.
+  Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Imm << 4)));
   return MCDisassembler::Success;
 }
 
-static DecodeStatus decodeMemRI34PCRelOperands(MCInst &Inst, uint64_t Imm,
-                                               int64_t Address,
-                                               const MCDisassembler *Decoder) {
-  // Decode the memri34_pcrel field (imm, reg), which has the low 34-bits as the
-  // displacement, and the next 5 bits as an immediate 0.
-  uint64_t Base = Imm >> 34;
-  uint64_t Disp = Imm & 0x3FFFFFFFFUL;
+static DecodeStatus decodeDispSPE8Operand(MCInst &Inst, uint64_t Imm,
+  // Decode the dispSPE8 field, which has 5-bits, 8-byte aligned.
 
-  assert(Base < 32 && "Invalid base register");
-
-  Inst.addOperand(MCOperand::createImm(SignExtend64<34>(Disp)));
-  return decodeImmZeroOperand(Inst, Base, Address, Decoder);
-}
-
-static DecodeStatus decodeMemRI34Operands(MCInst &Inst, uint64_t Imm,
-                                          int64_t Address,
-                                          const MCDisassembler *Decoder) {
-  // Decode the memri34 field (imm, reg), which has the low 34-bits as the
-  // displacement, and the next 5 bits as the register #.
-  uint64_t Base = Imm >> 34;
-  uint64_t Disp = Imm & 0x3FFFFFFFFUL;
-
-  assert(Base < 32 && "Invalid base register");
-
-  Inst.addOperand(MCOperand::createImm(SignExtend64<34>(Disp)));
-  Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
-  return MCDisassembler::Success;
-}
-
-static DecodeStatus decodeSPE8Operands(MCInst &Inst, uint64_t Imm,
-                                       int64_t Address,
-                                       const MCDisassembler *Decoder) {
-  // Decode the spe8disp field (imm, reg), which has the low 5-bits as the
-  // displacement with 8-byte aligned, and the next 5 bits as the register #.
-
-  uint64_t Base = Imm >> 5;
   uint64_t Disp = Imm & 0x1F;
 
-  assert(Base < 32 && "Invalid base register");
-
   Inst.addOperand(MCOperand::createImm(Disp << 3));
-  Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
   return MCDisassembler::Success;
 }
 
-static DecodeStatus decodeSPE4Operands(MCInst &Inst, uint64_t Imm,
+static DecodeStatus decodeDispSPE4Operand(MCInst &Inst, uint64_t Imm,
                                           int64_t Address,
                                           const MCDisassembler *Decoder) {
-  // Decode the spe4disp field (imm, reg), which has the low 5-bits as the
-  // displacement with 4-byte aligned, and the next 5 bits as the register #.
+  // Decode the dispSPE8 field, which has 5-bits, 4-byte aligned.
 
-  uint64_t Base = Imm >> 5;
   uint64_t Disp = Imm & 0x1F;
 
-  assert(Base < 32 && "Invalid base register");
-
   Inst.addOperand(MCOperand::createImm(Disp << 2));
-  Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
   return MCDisassembler::Success;
 }
 
-static DecodeStatus decodeSPE2Operands(MCInst &Inst, uint64_t Imm,
+static DecodeStatus decodeDispSPE2Operand(MCInst &Inst, uint64_t Imm,
                                           int64_t Address,
                                           const MCDisassembler *Decoder) {
-  // Decode the spe2disp field (imm, reg), which has the low 5-bits as the
-  // displacement with 2-byte aligned, and the next 5 bits as the register #.
+  // Decode the dispSPE8 field, which has 5-bits, 2-byte aligned.
 
-  uint64_t Base = Imm >> 5;
   uint64_t Disp = Imm & 0x1F;
-
-  assert(Base < 32 && "Invalid base register");
-
   Inst.addOperand(MCOperand::createImm(Disp << 1));
-  Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus decodeCRBitMOperand(MCInst &Inst, uint64_t Imm,
                                         int64_t Address,
                                         const MCDisassembler *Decoder) {
   // The cr bit encoding is 0x80 >> cr_reg_num.
 

llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.h

uint64_t getImm34Encoding(const MCInst &MI, unsigned OpNo,
                             const MCSubtargetInfo &STI,
                             MCFixupKind Fixup) const;
   uint64_t getImm34EncodingNoPCRel(const MCInst &MI, unsigned OpNo,
                                    SmallVectorImpl<MCFixup> &Fixups,
                                    const MCSubtargetInfo &STI) const;
   uint64_t getImm34EncodingPCRel(const MCInst &MI, unsigned OpNo,
                                  SmallVectorImpl<MCFixup> &Fixups,
                                  const MCSubtargetInfo &STI) const;
-  unsigned getMemRIEncoding(const MCInst &MI, unsigned OpNo,
+  unsigned getDispRIEncoding(const MCInst &MI, unsigned OpNo,
                              SmallVectorImpl<MCFixup> &Fixups,
                              const MCSubtargetInfo &STI) const;
-  unsigned getMemRIXEncoding(const MCInst &MI, unsigned OpNo,
+  unsigned getDispRIXEncoding(const MCInst &MI, unsigned OpNo,
                               SmallVectorImpl<MCFixup> &Fixups,
                               const MCSubtargetInfo &STI) const;
-  unsigned getMemRIX16Encoding(const MCInst &MI, unsigned OpNo,
+  unsigned getDispRIX16Encoding(const MCInst &MI, unsigned OpNo,
                                 SmallVectorImpl<MCFixup> &Fixups,
                                 const MCSubtargetInfo &STI) const;
-  unsigned getMemRIHashEncoding(const MCInst &MI, unsigned OpNo,
+  unsigned getDispRIHashEncoding(const MCInst &MI, unsigned OpNo,
                                  SmallVectorImpl<MCFixup> &Fixups,
                                  const MCSubtargetInfo &STI) const;
-  uint64_t getMemRI34PCRelEncoding(const MCInst &MI, unsigned OpNo,
+  uint64_t getDispRI34PCRelEncoding(const MCInst &MI, unsigned OpNo,
                                     SmallVectorImpl<MCFixup> &Fixups,
                                     const MCSubtargetInfo &STI) const;
-  uint64_t getMemRI34Encoding(const MCInst &MI, unsigned OpNo,
+  uint64_t getDispRI34Encoding(const MCInst &MI, unsigned OpNo,
                                SmallVectorImpl<MCFixup> &Fixups,
                                const MCSubtargetInfo &STI) const;
-  unsigned getSPE8DisEncoding(const MCInst &MI, unsigned OpNo,
+  unsigned getDispSPE8Encoding(const MCInst &MI, unsigned OpNo,
                                SmallVectorImpl<MCFixup> &Fixups,
                                const MCSubtargetInfo &STI) const;
-  unsigned getSPE4DisEncoding(const MCInst &MI, unsigned OpNo,
+  unsigned getDispSPE4Encoding(const MCInst &MI, unsigned OpNo,
                                SmallVectorImpl<MCFixup> &Fixups,
                                const MCSubtargetInfo &STI) const;
-  unsigned getSPE2DisEncoding(const MCInst &MI, unsigned OpNo,
+  unsigned getDispSPE2Encoding(const MCInst &MI, unsigned OpNo,
                                SmallVectorImpl<MCFixup> &Fixups,
                                const MCSubtargetInfo &STI) const;
   unsigned getTLSRegEncoding(const MCInst &MI, unsigned OpNo,
                              SmallVectorImpl<MCFixup> &Fixups,
                              const MCSubtargetInfo &STI) const;
   unsigned getTLSCallEncoding(const MCInst &MI, unsigned OpNo,
                               SmallVectorImpl<MCFixup> &Fixups,
                               const MCSubtargetInfo &STI) const;
   unsigned get_crbitm_encoding(const MCInst &MI, unsigned OpNo,
                                SmallVectorImpl<MCFixup> &Fixups,

llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp

 uint64_t
 PPCMCCodeEmitter::getImm34EncodingPCRel(const MCInst &MI, unsigned OpNo,
                                         SmallVectorImpl<MCFixup> &Fixups,
                                         const MCSubtargetInfo &STI) const {
   return getImm34Encoding(MI, OpNo, Fixups, STI,
                           (MCFixupKind)PPC::fixup_ppc_pcrel34);
 }
 
-unsigned PPCMCCodeEmitter::getMemRIEncoding(const MCInst &MI, unsigned OpNo,
+unsigned PPCMCCodeEmitter::getDispRIEncoding(const MCInst &MI, unsigned OpNo,
                                              SmallVectorImpl<MCFixup> &Fixups,
                                              const MCSubtargetInfo &STI) const {
-  // Encode (imm, reg) as a memri, which has the low 16-bits as the
-  // displacement and the next 5 bits as the register #.
-  assert(MI.getOperand(OpNo+1).isReg());
-  unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 16;
-
   const MCOperand &MO = MI.getOperand(OpNo);
   if (MO.isImm())
-    return (getMachineOpValue(MI, MO, Fixups, STI) & 0xFFFF) | RegBits;
+    return getMachineOpValue(MI, MO, Fixups, STI) & 0xFFFF;
 
   // Add a fixup for the displacement field.
   Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(),
                                    (MCFixupKind)PPC::fixup_ppc_half16));
-  return RegBits;
+  return 0;
 }
 
-unsigned PPCMCCodeEmitter::getMemRIXEncoding(const MCInst &MI, unsigned OpNo,
-                                       SmallVectorImpl<MCFixup> &Fixups,
-                                       const MCSubtargetInfo &STI) const {
-  // Encode (imm, reg) as a memrix, which has the low 14-bits as the
-  // displacement and the next 5 bits as the register #.
-  assert(MI.getOperand(OpNo+1).isReg());
-  unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 14;
-
+unsigned
+PPCMCCodeEmitter::getDispRIXEncoding(const MCInst &MI, unsigned OpNo,
   const MCOperand &MO = MI.getOperand(OpNo);
   if (MO.isImm())
-    return ((getMachineOpValue(MI, MO, Fixups, STI) >> 2) & 0x3FFF) | RegBits;
+    return ((getMachineOpValue(MI, MO, Fixups, STI) >> 2) & 0x3FFF);
 
   // Add a fixup for the displacement field.
   Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(),
                                    (MCFixupKind)PPC::fixup_ppc_half16ds));
-  return RegBits;
+  return 0;
 }
 
-unsigned PPCMCCodeEmitter::getMemRIX16Encoding(const MCInst &MI, unsigned OpNo,
+unsigned
+PPCMCCodeEmitter::getDispRIX16Encoding(const MCInst &MI, unsigned OpNo,
                                        SmallVectorImpl<MCFixup> &Fixups,
                                        const MCSubtargetInfo &STI) const {
-  // Encode (imm, reg) as a memrix16, which has the low 12-bits as the
-  // displacement and the next 5 bits as the register #.
-  assert(MI.getOperand(OpNo+1).isReg());
-  unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 12;
-
   const MCOperand &MO = MI.getOperand(OpNo);
   if (MO.isImm()) {
     assert(!(MO.getImm() % 16) &&
            "Expecting an immediate that is a multiple of 16");
-    return ((getMachineOpValue(MI, MO, Fixups, STI) >> 4) & 0xFFF) | RegBits;
+    return ((getMachineOpValue(MI, MO, Fixups, STI) >> 4) & 0xFFF);
   }
 
   // Otherwise add a fixup for the displacement field.
   Fixups.push_back(MCFixup::create(IsLittleEndian ? 0 : 2, MO.getExpr(),
                                    (MCFixupKind)PPC::fixup_ppc_half16dq));
-  return RegBits;
+  return 0;
 }
 
 unsigned
-PPCMCCodeEmitter::getMemRIHashEncoding(const MCInst &MI, unsigned OpNo,
+PPCMCCodeEmitter::getDispRIHashEncoding(const MCInst &MI, unsigned OpNo,
                                         SmallVectorImpl<MCFixup> &Fixups,
                                         const MCSubtargetInfo &STI) const {
-  // Encode (imm, reg) for the hash load/store to stack for the ROP Protection
+  // Encode imm for the hash load/store to stack for the ROP Protection
   // instructions.
-  const MCOperand &RegMO = MI.getOperand(OpNo + 1);
   const MCOperand &MO = MI.getOperand(OpNo);
 
-  assert(RegMO.isReg() && "Base address must be a register.");
   assert(MO.isImm() && "Expecting an immediate operand.");
   assert(!(MO.getImm() % 8) && "Expecting offset to be 8 byte aligned.");
 
-  unsigned RegBits = getMachineOpValue(MI, RegMO, Fixups, STI) << 6;
   unsigned DX = (MO.getImm() >> 3) & 0x3F;
-  return RegBits | DX;
+  return DX;
 }
 
 uint64_t
-PPCMCCodeEmitter::getMemRI34PCRelEncoding(const MCInst &MI, unsigned OpNo,
+PPCMCCodeEmitter::getDispRI34PCRelEncoding(const MCInst &MI, unsigned OpNo,
                                            SmallVectorImpl<MCFixup> &Fixups,
                                            const MCSubtargetInfo &STI) const {
-  // Encode the PCRelative version of memri34: imm34(r0).
-  // In the PC relative version the register for the address must be zero.
+  // Encode the displacement part of pc-relative memri34, which is an imm34.
   // The 34 bit immediate can fall into one of three cases:
   // 1) It is a relocation to be filled in by the linker represented as:
   //    (MCExpr::SymbolRef)
   // 2) It is a relocation + SignedOffset represented as:
   //    (MCExpr::Binary(MCExpr::SymbolRef + MCExpr::Constant))
   // 3) It is a known value at compile time.
 
-  // Make sure that the register is a zero as expected.
-  assert(MI.getOperand(OpNo + 1).isImm() && "Expecting an immediate.");
-  uint64_t RegBits =
-    getMachineOpValue(MI, MI.getOperand(OpNo + 1), Fixups, STI) << 34;
-  assert(RegBits == 0 && "Operand must be 0.");
-
   // If this is not a MCExpr then we are in case 3) and we are dealing with
   // a value known at compile time, not a relocation.
   const MCOperand &MO = MI.getOperand(OpNo);
   if (!MO.isExpr())
-    return ((getMachineOpValue(MI, MO, Fixups, STI)) & 0x3FFFFFFFFUL) | RegBits;
+    return (getMachineOpValue(MI, MO, Fixups, STI)) & 0x3FFFFFFFFUL;
 
   // At this point in the function it is known that MO is of type MCExpr.
   // Therefore we are dealing with either case 1) a symbol ref or
   // case 2) a symbol ref plus a constant.
   const MCExpr *Expr = MO.getExpr();
   switch (Expr->getKind()) {
   default:
     llvm_unreachable("Unsupported MCExpr for getMemRI34PCRelEncoding.");
case MCExpr::Binary: {
     // Put zero in the location of the immediate. The linker will fill in the
     // correct value based on the relocation.
     return 0;
     }
   }
 }
 
 uint64_t
-PPCMCCodeEmitter::getMemRI34Encoding(const MCInst &MI, unsigned OpNo,
+PPCMCCodeEmitter::getDispRI34Encoding(const MCInst &MI, unsigned OpNo,
                                       SmallVectorImpl<MCFixup> &Fixups,
                                       const MCSubtargetInfo &STI) const {
-  // Encode (imm, reg) as a memri34, which has the low 34-bits as the
-  // displacement and the next 5 bits as the register #.
-  assert(MI.getOperand(OpNo + 1).isReg() && "Expecting a register.");
-  uint64_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo + 1), Fixups, STI)
-                     << 34;
+  // Encode the displacement part of a memri34.
   const MCOperand &MO = MI.getOperand(OpNo);
-  return ((getMachineOpValue(MI, MO, Fixups, STI)) & 0x3FFFFFFFFUL) | RegBits;
+  return (getMachineOpValue(MI, MO, Fixups, STI)) & 0x3FFFFFFFFUL;
 }
 
-unsigned PPCMCCodeEmitter::getSPE8DisEncoding(const MCInst &MI, unsigned OpNo,
-                                              SmallVectorImpl<MCFixup> &Fixups,
-                                              const MCSubtargetInfo &STI)
-                                              const {
-  // Encode (imm, reg) as a spe8dis, which has the low 5-bits of (imm / 8)
-  // as the displacement and the next 5 bits as the register #.
-  assert(MI.getOperand(OpNo+1).isReg());
-  uint32_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 5;
-
+unsigned
+PPCMCCodeEmitter::getDispSPE8Encoding(const MCInst &MI, unsigned OpNo,
+                                      const MCSubtargetInfo &STI) const {
+  // Encode imm as a dispSPE8, which has the low 5-bits of (imm / 8).
   const MCOperand &MO = MI.getOperand(OpNo);
   assert(MO.isImm());
-  uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 3;
-  return reverseBits(Imm | RegBits) >> 22;
+  return getMachineOpValue(MI, MO, Fixups, STI) >> 3;
 }
 
-unsigned PPCMCCodeEmitter::getSPE4DisEncoding(const MCInst &MI, unsigned OpNo,
-                                              SmallVectorImpl<MCFixup> &Fixups,
-                                              const MCSubtargetInfo &STI)
-                                              const {
-  // Encode (imm, reg) as a spe4dis, which has the low 5-bits of (imm / 4)
-  // as the displacement and the next 5 bits as the register #.
-  assert(MI.getOperand(OpNo+1).isReg());
-  uint32_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 5;
-
+unsigned
+PPCMCCodeEmitter::getDispSPE4Encoding(const MCInst &MI, unsigned OpNo,
+                                      const MCSubtargetInfo &STI) const {
+  // Encode imm as a dispSPE8, which has the low 5-bits of (imm / 4).
   const MCOperand &MO = MI.getOperand(OpNo);
   assert(MO.isImm());
-  uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 2;
-  return reverseBits(Imm | RegBits) >> 22;
+  return getMachineOpValue(MI, MO, Fixups, STI) >> 2;
 }
 
-unsigned PPCMCCodeEmitter::getSPE2DisEncoding(const MCInst &MI, unsigned OpNo,
-                                              SmallVectorImpl<MCFixup> &Fixups,
-                                              const MCSubtargetInfo &STI)
-                                              const {
-  // Encode (imm, reg) as a spe2dis, which has the low 5-bits of (imm / 2)
-  // as the displacement and the next 5 bits as the register #.
-  assert(MI.getOperand(OpNo+1).isReg());
-  uint32_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 5;
-
+unsigned
+PPCMCCodeEmitter::getDispSPE2Encoding(const MCInst &MI, unsigned OpNo,
+                                      const MCSubtargetInfo &STI) const {
+  // Encode imm as a dispSPE8, which has the low 5-bits of (imm / 2).
   const MCOperand &MO = MI.getOperand(OpNo);
   assert(MO.isImm());
-  uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 1;
-  return reverseBits(Imm | RegBits) >> 22;
+  return getMachineOpValue(MI, MO, Fixups, STI) >> 1;
 }
 
 unsigned PPCMCCodeEmitter::getTLSRegEncoding(const MCInst &MI, unsigned OpNo,
                                        SmallVectorImpl<MCFixup> &Fixups,
                                        const MCSubtargetInfo &STI) const {
   const MCOperand &MO = MI.getOperand(OpNo);
   if (MO.isReg()) return getMachineOpValue(MI, MO, Fixups, STI);
 

llvm/lib/Target/PowerPC/PPC.td

 //===----------------------------------------------------------------------===//
 // Calling Conventions
 //===----------------------------------------------------------------------===//
 
 include "PPCCallingConv.td"
 
 def PPCInstrInfo : InstrInfo {
   let isLittleEndianEncoding = 1;
-
-  // FIXME: Unset this when no longer needed!
-  let decodePositionallyEncodedOperands = 1;
-
-  let noNamedPositionallyEncodedOperands = 1;
-  let useDeprecatedPositionallyEncodedOperands = 1;
 }
 
 def PPCAsmWriter : AsmWriter {
   string AsmWriterClassName  = "InstPrinter";
   int PassSubtarget = 1;
   int Variant = 0;
   bit isMCAsmWriter = 1;
 }

llvm/lib/Target/PowerPC/PPCInstr64Bit.td

let isPredicable = 1 in
                    Requires<[In64BitMode]>;
   }
 }
 
 let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1,
     Defs = [LR8, X2], Uses = [CTR8, RM], RST = 2 in {
   def BCTRL8_LDinto_toc :
     XLForm_2_ext_and_DSForm_1<19, 528, 20, 0, 1, 58, 0, (outs),
-                              (ins memrix:$src),
+                              (ins (memrix $D, $RA):$src),
                               "bctrl\n\tld 2, $src", IIC_BrB,
                               [(PPCbctrl_load_toc iaddrX4:$src)]>,
     Requires<[In64BitMode]>;
 }
 
 let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1,
     Defs = [LR8, X2, RM], Uses = [CTR8, RM], RST = 2 in {
   def BCTRL8_LDinto_toc_RM :
     XLForm_2_ext_and_DSForm_1<19, 528, 20, 0, 1, 58, 0, (outs),
-                              (ins memrix:$src),
+                              (ins (memrix $D, $RA):$src),
                               "bctrl\n\tld 2, $src", IIC_BrB,
                               [(PPCbctrl_load_toc_rm iaddrX4:$src)]>,
     Requires<[In64BitMode]>;
 }
 
 } // Interpretation64Bit
 
 // FIXME: Duplicating this for the asm parser should be unnecessary, but the

 //===----------------------------------------------------------------------===//
 // Load/Store instructions.
 //
 
 
 // Sign extending loads.
 let PPC970_Unit = 2 in {
 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
-def LHA8: DForm_1<42, (outs g8rc:$RST), (ins memri:$addr),
+def LHA8: DForm_1<42, (outs g8rc:$RST), (ins (memri $D, $RA):$addr),
                   "lha $RST, $addr", IIC_LdStLHA,
                   [(set i64:$RST, (sextloadi16 DForm:$addr))]>,
                   PPC970_DGroup_Cracked, SExt32To64;
-def LWA  : DSForm_1<58, 2, (outs g8rc:$RST), (ins memrix:$addr),
+def LWA  : DSForm_1<58, 2, (outs g8rc:$RST), (ins (memrix $D, $RA):$addr),
                     "lwa $RST, $addr", IIC_LdStLWA,
                     [(set i64:$RST,
                           (sextloadi32 DSForm:$addr))]>, isPPC64,
                     PPC970_DGroup_Cracked, SExt32To64;
 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
 def LHAX8: XForm_1_memOp<31, 343, (outs g8rc:$RST), (ins (memrr $RA, $RB):$addr),
                         "lhax $RST, $addr", IIC_LdStLHA,
                         [(set i64:$RST, (sextloadi16 XForm:$addr))]>,
                         PPC970_DGroup_Cracked, SExt32To64;
 def LWAX : XForm_1_memOp<31, 341, (outs g8rc:$RST), (ins (memrr $RA, $RB):$addr),
                         "lwax $RST, $addr", IIC_LdStLHA,
                         [(set i64:$RST, (sextloadi32 XForm:$addr))]>, isPPC64,
                         PPC970_DGroup_Cracked, SExt32To64;
 // For fast-isel:
 let isCodeGenOnly = 1, mayLoad = 1, hasSideEffects = 0 in {
-def LWA_32  : DSForm_1<58, 2, (outs gprc:$RST), (ins memrix:$addr),
+def LWA_32  : DSForm_1<58, 2, (outs gprc:$RST), (ins (memrix $D, $RA):$addr),
                       "lwa $RST, $addr", IIC_LdStLWA, []>, isPPC64,
                       PPC970_DGroup_Cracked, SExt32To64;
 def LWAX_32 : XForm_1_memOp<31, 341, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr),
                             "lwax $RST, $addr", IIC_LdStLHA, []>, isPPC64,
                             PPC970_DGroup_Cracked, SExt32To64;
 } // end fast-isel isCodeGenOnly
 
 // Update forms.
 let mayLoad = 1, hasSideEffects = 0 in {
 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
 def LHAU8 : DForm_1<43, (outs g8rc:$RST, ptr_rc_nor0:$ea_result),
-                    (ins memri:$addr),
+                    (ins (memri $D, $RA):$addr),
                     "lhau $RST, $addr", IIC_LdStLHAU,
                     []>, RegConstraint<"$addr.reg = $ea_result">,
                     NoEncode<"$ea_result">;
 // NO LWAU!
 
 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
 def LHAUX8 : XForm_1_memOp<31, 375, (outs g8rc:$RST, ptr_rc_nor0:$ea_result),
                           (ins (memrr $RA, $RB):$addr),
                           "lhaux $RST, $addr", IIC_LdStLHAUX,
                           []>, RegConstraint<"$addr.ptrreg = $ea_result">,
                           NoEncode<"$ea_result">;
 def LWAUX : XForm_1_memOp<31, 373, (outs g8rc:$RST, ptr_rc_nor0:$ea_result),
                           (ins (memrr $RA, $RB):$addr),
                           "lwaux $RST, $addr", IIC_LdStLHAUX,
                           []>, RegConstraint<"$addr.ptrreg = $ea_result">,
                           NoEncode<"$ea_result">, isPPC64;
 }
 }
 
 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
 // Zero extending loads.
 let PPC970_Unit = 2 in {
-def LBZ8 : DForm_1<34, (outs g8rc:$RST), (ins memri:$addr),
+def LBZ8 : DForm_1<34, (outs g8rc:$RST), (ins (memri $D, $RA):$addr),
                   "lbz $RST, $addr", IIC_LdStLoad,
                   [(set i64:$RST, (zextloadi8 DForm:$addr))]>, ZExt32To64,
                   SExt32To64;
-def LHZ8 : DForm_1<40, (outs g8rc:$RST), (ins memri:$addr),
+def LHZ8 : DForm_1<40, (outs g8rc:$RST), (ins (memri $D, $RA):$addr),
                   "lhz $RST, $addr", IIC_LdStLoad,
                   [(set i64:$RST, (zextloadi16 DForm:$addr))]>, ZExt32To64,
                   SExt32To64;
-def LWZ8 : DForm_1<32, (outs g8rc:$RST), (ins memri:$addr),
+def LWZ8 : DForm_1<32, (outs g8rc:$RST), (ins (memri $D, $RA):$addr),
                   "lwz $RST, $addr", IIC_LdStLoad,
                   [(set i64:$RST, (zextloadi32 DForm:$addr))]>, isPPC64,
                   ZExt32To64;
 
 def LBZX8 : XForm_1_memOp<31,  87, (outs g8rc:$RST), (ins (memrr $RA, $RB):$addr),
                           "lbzx $RST, $addr", IIC_LdStLoad,
                           [(set i64:$RST, (zextloadi8 XForm:$addr))]>, ZExt32To64,
                           SExt32To64;
 def LHZX8 : XForm_1_memOp<31, 279, (outs g8rc:$RST), (ins (memrr $RA, $RB):$addr),
                           "lhzx $RST, $addr", IIC_LdStLoad,
                           [(set i64:$RST, (zextloadi16 XForm:$addr))]>,
                           ZExt32To64, SExt32To64;
 def LWZX8 : XForm_1_memOp<31,  23, (outs g8rc:$RST), (ins (memrr $RA, $RB):$addr),
                           "lwzx $RST, $addr", IIC_LdStLoad,
                           [(set i64:$RST, (zextloadi32 XForm:$addr))]>,
                           ZExt32To64;
                    
                    
 // Update forms.
 let mayLoad = 1, hasSideEffects = 0 in {
 def LBZU8 : DForm_1<35, (outs g8rc:$RST, ptr_rc_nor0:$ea_result),
-                    (ins memri:$addr),
+                    (ins (memri $D, $RA):$addr),
                     "lbzu $RST, $addr", IIC_LdStLoadUpd,
                     []>, RegConstraint<"$addr.reg = $ea_result">,
                     NoEncode<"$ea_result">;
 def LHZU8 : DForm_1<41, (outs g8rc:$RST, ptr_rc_nor0:$ea_result),
-                    (ins memri:$addr),
+                    (ins (memri $D, $RA):$addr),
                     "lhzu $RST, $addr", IIC_LdStLoadUpd,
                     []>, RegConstraint<"$addr.reg = $ea_result">,
                     NoEncode<"$ea_result">;
 def LWZU8 : DForm_1<33, (outs g8rc:$RST, ptr_rc_nor0:$ea_result),
-                    (ins memri:$addr),
+                    (ins (memri $D, $RA):$addr),
                     "lwzu $RST, $addr", IIC_LdStLoadUpd,
                     []>, RegConstraint<"$addr.reg = $ea_result">,
                     NoEncode<"$ea_result">;
 
 def LBZUX8 : XForm_1_memOp<31, 119, (outs g8rc:$RST, ptr_rc_nor0:$ea_result),
                           (ins (memrr $RA, $RB):$addr),
                           "lbzux $RST, $addr", IIC_LdStLoadUpdX,
                           []>, RegConstraint<"$addr.ptrreg = $ea_result">,
def LWZUX8 : XForm_1_memOp<31, 55, (outs g8rc:$RST, ptr_rc_nor0:$ea_result),
                           NoEncode<"$ea_result">;
 }
 }
 } // Interpretation64Bit
 
 
 // Full 8-byte loads.
 let PPC970_Unit = 2 in {
-def LD   : DSForm_1<58, 0, (outs g8rc:$RST), (ins memrix:$addr),
+def LD   : DSForm_1<58, 0, (outs g8rc:$RST), (ins (memrix $D, $RA):$addr),
                     "ld $RST, $addr", IIC_LdStLD,
                     [(set i64:$RST, (load DSForm:$addr))]>, isPPC64;
 // The following four definitions are selected for small code model only.
 // Otherwise, we need to create two instructions to form a 32-bit offset,
 // so we have a custom matcher for TOC_ENTRY in PPCDAGToDAGIsel::Select().
 def LDtoc: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg),
                   "#LDtoc",
                   [(set i64:$rD,

 def LHBRX8 : XForm_1_memOp<31, 790, (outs g8rc:$RST), (ins (memrr $RA, $RB):$addr),
                           "lhbrx $RST, $addr", IIC_LdStLoad, []>, ZExt32To64;
 def LWBRX8 : XForm_1_memOp<31,  534, (outs g8rc:$RST), (ins (memrr $RA, $RB):$addr),
                           "lwbrx $RST, $addr", IIC_LdStLoad, []>, ZExt32To64;
 }
 
 let mayLoad = 1, hasSideEffects = 0 in {
 def LDU  : DSForm_1<58, 1, (outs g8rc:$RST, ptr_rc_nor0:$ea_result),
-                    (ins memrix:$addr),
+                    (ins (memrix $D, $RA):$addr),
                     "ldu $RST, $addr", IIC_LdStLDU,
                     []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64,
                     NoEncode<"$ea_result">;
 
 def LDUX : XForm_1_memOp<31, 53, (outs g8rc:$RST, ptr_rc_nor0:$ea_result),
                         (ins (memrr $RA, $RB):$addr),
                         "ldux $RST, $addr", IIC_LdStLDUX,
                         []>, RegConstraint<"$addr.ptrreg = $ea_result">,
                         NoEncode<"$ea_result">, isPPC64;
 }
 
 let mayLoad = 1, hasNoSchedulingInfo = 1 in {
 // Full 16-byte load.
 // Early clobber $RTp to avoid assigned to the same register as RA.
 // TODO: Add scheduling info.
 def LQ   : DQForm_RTp5_RA17_MEM<56, 0,
                                 (outs g8prc:$RTp),
-                                (ins memrix16:$addr),
+                                (ins (memrix16 $DQ, $RA):$addr),
                                 "lq $RTp, $addr", IIC_LdStLQ,
                                 []>,
                                 RegConstraint<"@earlyclobber $RTp">,
                                 isPPC64;
 // We don't really have LQX in the ISA, make a pseudo one so that we can
 // handle x-form during isel. Make it pre-ra may expose
 // oppotunities to some opts(CSE, LICM and etc.) for the result of adding
 // RA and RB.
def PADDIdtprel : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
                           "#PADDIdtprel",
                           [(set i64:$rD,
                             (PPCpaddiDtprel i64:$reg, tglobaltlsaddr:$disp))]>,
                   isPPC64;
 
 let PPC970_Unit = 2 in {
 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
 // Truncating stores.                       
-def STB8 : DForm_1<38, (outs), (ins g8rc:$RST, memri:$addr),
+def STB8 : DForm_1<38, (outs), (ins g8rc:$RST, (memri $D, $RA):$addr),
                    "stb $RST, $addr", IIC_LdStStore,
                    [(truncstorei8 i64:$RST, DForm:$addr)]>;
-def STH8 : DForm_1<44, (outs), (ins g8rc:$RST, memri:$addr),
+def STH8 : DForm_1<44, (outs), (ins g8rc:$RST, (memri $D, $RA):$addr),
                    "sth $RST, $addr", IIC_LdStStore,
                    [(truncstorei16 i64:$RST, DForm:$addr)]>;
-def STW8 : DForm_1<36, (outs), (ins g8rc:$RST, memri:$addr),
+def STW8 : DForm_1<36, (outs), (ins g8rc:$RST, (memri $D, $RA):$addr),
                    "stw $RST, $addr", IIC_LdStStore,
                    [(truncstorei32 i64:$RST, DForm:$addr)]>;
 def STBX8 : XForm_8_memOp<31, 215, (outs), (ins g8rc:$RST, (memrr $RA, $RB):$addr),
                           "stbx $RST, $addr", IIC_LdStStore,
                           [(truncstorei8 i64:$RST, XForm:$addr)]>,
                           PPC970_DGroup_Cracked;
 def STHX8 : XForm_8_memOp<31, 407, (outs), (ins g8rc:$RST, (memrr $RA, $RB):$addr),
                           "sthx $RST, $addr", IIC_LdStStore,
                           [(truncstorei16 i64:$RST, XForm:$addr)]>,
                           PPC970_DGroup_Cracked;
 def STWX8 : XForm_8_memOp<31, 151, (outs), (ins g8rc:$RST, (memrr $RA, $RB):$addr),
                           "stwx $RST, $addr", IIC_LdStStore,
                           [(truncstorei32 i64:$RST, XForm:$addr)]>,
                           PPC970_DGroup_Cracked;
 } // Interpretation64Bit
 
 // Normal 8-byte stores.
-def STD  : DSForm_1<62, 0, (outs), (ins g8rc:$RST, memrix:$addr),
+def STD  : DSForm_1<62, 0, (outs), (ins g8rc:$RST, (memrix $D, $RA):$addr),
                     "std $RST, $addr", IIC_LdStSTD,
                     [(store i64:$RST, DSForm:$addr)]>, isPPC64;
 def STDX  : XForm_8_memOp<31, 149, (outs), (ins g8rc:$RST, (memrr $RA, $RB):$addr),
                           "stdx $RST, $addr", IIC_LdStSTD,
                           [(store i64:$RST, XForm:$addr)]>, isPPC64,
                           PPC970_DGroup_Cracked;
 
 let Predicates = [IsISA2_06] in {
 def STDBRX: XForm_8_memOp<31, 660, (outs), (ins g8rc:$RST, (memrr $RA, $RB):$addr),
                           "stdbrx $RST, $addr", IIC_LdStStore,
                           [(PPCstbrx i64:$RST, ForceXForm:$addr, i64)]>, isPPC64,
                           PPC970_DGroup_Cracked;
 }
 
 let mayStore = 1, hasNoSchedulingInfo = 1 in {
 // Normal 16-byte stores.
 // TODO: Add scheduling info.
-def STQ : DSForm_1<62, 2, (outs), (ins g8prc:$RST, memrix:$addr),
+def STQ : DSForm_1<62, 2, (outs), (ins g8prc:$RST, (memrix $D, $RA):$addr),
                    "stq $RST, $addr", IIC_LdStSTQ,
                    []>, isPPC64;
 
 def STQX_PSEUDO : PPCCustomInserterPseudo<(outs),
                                           (ins g8prc:$RSp, memrr:$dst),
                                           "#STQX_PSEUDO", []>;
 
 def SPILL_QUADWORD : PPCEmitTimePseudo<(outs), (ins g8prc:$RSp, memrix:$dst),
def : Pat<(int_ppc_atomic_store_i128 i64:$lo, i64:$hi, DSForm:$dst),
           (STQ (BUILD_QUADWORD g8rc:$lo, g8rc:$hi), memrix:$dst)>;
 
 def : Pat<(int_ppc_atomic_store_i128 i64:$lo, i64:$hi, ForceXForm:$dst),
           (STQX_PSEUDO (BUILD_QUADWORD g8rc:$lo, g8rc:$hi), memrr:$dst)>;
 
 // Stores with Update (pre-inc).
 let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in {
 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
-def STBU8 : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$RST, memri:$addr),
+def STBU8 : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$RST, (memri $D, $RA):$addr),
                    "stbu $RST, $addr", IIC_LdStSTU, []>,
                    RegConstraint<"$addr.reg = $ea_res">, NoEncode<"$ea_res">;
-def STHU8 : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$RST, memri:$addr),
+def STHU8 : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$RST, (memri $D, $RA):$addr),
                    "sthu $RST, $addr", IIC_LdStSTU, []>,
                    RegConstraint<"$addr.reg = $ea_res">, NoEncode<"$ea_res">;
-def STWU8 : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$RST, memri:$addr),
+def STWU8 : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$RST, (memri $D, $RA):$addr),
                    "stwu $RST, $addr", IIC_LdStSTU, []>,
                    RegConstraint<"$addr.reg = $ea_res">, NoEncode<"$ea_res">;
 
 def STBUX8: XForm_8_memOp<31, 247, (outs ptr_rc_nor0:$ea_res),
                           (ins g8rc:$RST, (memrr $RA, $RB):$addr),
                           "stbux $RST, $addr", IIC_LdStSTUX, []>,
                           RegConstraint<"$addr.ptrreg = $ea_res">,
                           NoEncode<"$ea_res">,
                           PPC970_DGroup_Cracked;
 def STHUX8: XForm_8_memOp<31, 439, (outs ptr_rc_nor0:$ea_res),
                           (ins g8rc:$RST, (memrr $RA, $RB):$addr),
                           "sthux $RST, $addr", IIC_LdStSTUX, []>,
                           RegConstraint<"$addr.ptrreg = $ea_res">,
                           NoEncode<"$ea_res">,
                           PPC970_DGroup_Cracked;
 def STWUX8: XForm_8_memOp<31, 183, (outs ptr_rc_nor0:$ea_res),
                           (ins g8rc:$RST, (memrr $RA, $RB):$addr),
                           "stwux $RST, $addr", IIC_LdStSTUX, []>,
                           RegConstraint<"$addr.ptrreg = $ea_res">,
                           NoEncode<"$ea_res">,
                           PPC970_DGroup_Cracked;
 } // Interpretation64Bit
 
 def STDU : DSForm_1<62, 1, (outs ptr_rc_nor0:$ea_res),
-                   (ins g8rc:$RST, memrix:$addr),
+                   (ins g8rc:$RST, (memrix $D, $RA):$addr),
                    "stdu $RST, $addr", IIC_LdStSTU, []>,
                    RegConstraint<"$addr.reg = $ea_res">, NoEncode<"$ea_res">,
                    isPPC64;
 
 def STDUX : XForm_8_memOp<31, 181, (outs ptr_rc_nor0:$ea_res),
                           (ins g8rc:$RST, (memrr $RA, $RB):$addr),
                           "stdux $RST, $addr", IIC_LdStSTUX, []>,
                           RegConstraint<"$addr.ptrreg = $ea_res">,
defm FCTIWUZ : XForm_26r<63, 143, (outs f8rc:$RST), (ins f8rc:$RB),
                         "fctiwuz", "$RST, $RB", IIC_FPGeneral,
                         [(set f64:$RST, (PPCany_fctiwuz f64:$RB))]>, isPPC64;
 }
 
 // These instructions store a hash computed from the value of the link register
 // and the value of the stack pointer.
 let mayStore = 1, Interpretation64Bit = 1, isCodeGenOnly = 1 in {
 def HASHST8 : XForm_XD6_RA5_RB5<31, 722, (outs),
-                                (ins g8rc:$RB, memrihash:$D_RA_XD),
-                                "hashst $RB, $D_RA_XD", IIC_IntGeneral, []>;
+                                (ins g8rc:$RB, (memrihash $D, $RA):$addr),
+                                "hashst $RB, $addr", IIC_IntGeneral, []>;
 def HASHSTP8 : XForm_XD6_RA5_RB5<31, 658, (outs),
-                                 (ins g8rc:$RB, memrihash:$D_RA_XD),
-                                 "hashstp $RB, $D_RA_XD", IIC_IntGeneral, []>;
+                                 (ins g8rc:$RB, (memrihash $D, $RA):$addr),
+                                 "hashstp $RB, $addr", IIC_IntGeneral, []>;
 }
 
 // These instructions check a hash computed from the value of the link register
 // and the value of the stack pointer. The hasSideEffects flag is needed as the
 // instruction may TRAP if the hash does not match the hash stored at the
 // specified address.
 let mayLoad = 1, hasSideEffects = 1,
     Interpretation64Bit = 1, isCodeGenOnly = 1 in {
 def HASHCHK8 : XForm_XD6_RA5_RB5<31, 754, (outs),
-                                 (ins g8rc:$RB, memrihash:$D_RA_XD),
-                                 "hashchk $RB, $D_RA_XD", IIC_IntGeneral, []>;
+                                 (ins g8rc:$RB, (memrihash $D, $RA):$addr),
+                                 "hashchk $RB, $addr", IIC_IntGeneral, []>;
 def HASHCHKP8 : XForm_XD6_RA5_RB5<31, 690, (outs),
-                                  (ins g8rc:$RB, memrihash:$D_RA_XD),
-                                  "hashchkp $RB, $D_RA_XD", IIC_IntGeneral, []>;
+                                  (ins g8rc:$RB, (memrihash $D, $RA):$addr),
+                                  "hashchkp $RB, $addr", IIC_IntGeneral, []>;
 }
 
 let Interpretation64Bit = 1, isCodeGenOnly = 1, hasSideEffects = 1 in
 def ADDEX8 : Z23Form_RTAB5_CY2<31, 170, (outs g8rc:$RT),
                               (ins g8rc:$RA, g8rc:$RB, u2imm:$CY),
                               "addex $RT, $RA, $RB, $CY", IIC_IntGeneral,
                               [(set i64:$RT, (int_ppc_addex i64:$RA, i64:$RB,
                                                             timm:$CY))]>;

llvm/lib/Target/PowerPC/PPCInstrFormats.td

class DForm_base<bits<6> opcode, dag OOL, dag IOL, string asmstr,
 
   let Inst{6-10}  = RST;
   let Inst{11-15} = RA;
   let Inst{16-31} = D;
 }
 
 class DForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr,
               InstrItinClass itin, list<dag> pattern>
-  : I<opcode, OOL, IOL, asmstr, itin> {
-  bits<5>  RST;
-  // FIXME: bogus names, to force positional matching for the moment.
-  bits<21> addr_foo;
-
-  let Pattern = pattern;
-
-  let Inst{6-10}  = RST;
-  let Inst{11-15} = addr_foo{20-16}; // Base Reg
-  let Inst{16-31} = addr_foo{15-0};  // Displacement
+  : DForm_base<opcode, OOL, IOL, asmstr, itin, pattern> {
 }
 
 class DForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr,
               InstrItinClass itin, list<dag> pattern>
   : DForm_base<opcode, OOL, IOL, asmstr, itin, pattern> {
 
   // Even though ADDIC_rec does not really have an RC bit, provide
   // the declaration of one here so that isRecordForm has something to set.
class DForm_4<bits<6> opcode, dag OOL, dag IOL, string asmstr,
   let Inst{11-15} = RA;
   let Inst{16-31} = D;
 }
 
 class DForm_4_zero<bits<6> opcode, dag OOL, dag IOL, string asmstr,
                    InstrItinClass itin, list<dag> pattern>
   : DForm_1<opcode, OOL, IOL, asmstr, itin, pattern> {
   let RST = 0;
-  let addr_foo = 0;
+  let RA = 0;
+  let D = 0;
 }
 
 class DForm_4_fixedreg_zero<bits<6> opcode, bits<5> R, dag OOL, dag IOL,
                             string asmstr, InstrItinClass itin,
                             list<dag> pattern>
   : DForm_4<opcode, OOL, IOL, asmstr, itin, pattern> {
   let RST = R;
   let RA = R;
   let D = 0;
 }
 
 class IForm_and_DForm_1<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2,
             dag OOL, dag IOL, string asmstr,
             InstrItinClass itin, list<dag> pattern>
          : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> {
   bits<5>  RST;
-  bits<21> addr;
+  bits<5>  RA;
+  bits<16> D;
 
   let Pattern = pattern;
   bits<24> LI;
 
   let Inst{6-29}  = LI;
   let Inst{30}    = aa;
   let Inst{31}    = lk;
 
   let Inst{38-42}  = RST;
-  let Inst{43-47} = addr{20-16}; // Base Reg
-  let Inst{48-63} = addr{15-0};  // Displacement
+  let Inst{43-47} = RA;
+  let Inst{48-63} = D;
 }
 
 // This is used to emit BL8+NOP.
 class IForm_and_DForm_4_zero<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2,
             dag OOL, dag IOL, string asmstr,
             InstrItinClass itin, list<dag> pattern>
          :  IForm_and_DForm_1<opcode1, aa, lk, opcode2,
                               OOL, IOL, asmstr, itin, pattern> {
   let RST = 0;
-  let addr = 0;
+  let RA = 0;
+  let D = 0;
 }
 
 class DForm_5<bits<6> opcode, dag OOL, dag IOL, string asmstr,
               InstrItinClass itin>
   : I<opcode, OOL, IOL, asmstr, itin> {
   bits<3>  BF;
   bits<1>  L;
   bits<5>  RA;

 }
 
 
 // 1.7.5 DS-Form
 class DSForm_1<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr,
                InstrItinClass itin, list<dag> pattern>
          : I<opcode, OOL, IOL, asmstr, itin> {
   bits<5>  RST;
-  // FIXME: bogus names, to force positional matching for the moment.rr
-  bits<19> addr_foo;
-  bits<14> DS;
-  bits<5> RA;
-
-  let DS = addr_foo{13-0};
-  let RA = addr_foo{18-14};
+  bits<5>  RA;
+  bits<14> D;
 
   let Pattern = pattern;
 
   let Inst{6-10}  = RST;
   let Inst{11-15} = RA;
-  let Inst{16-29} = DS;
+  let Inst{16-29} = D;
   let Inst{30-31} = xo;
 }
 
 // ISA V3.0B 1.6.6 DX-Form
 class DXForm<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
              InstrItinClass itin, list<dag> pattern>
          : I<opcode, OOL, IOL, asmstr, itin> {
   bits<5>  RT;
   bits<16> D;
 
   let Pattern = pattern;
 
   let Inst{6-10}  = RT;
   let Inst{11-15} = D{5-1};  // d1
   let Inst{16-25} = D{15-6}; // d0
   let Inst{26-30} = xo;
   let Inst{31}    = D{0};    // d2
 }
 
 // DQ-Form: [PO T RA DQ TX XO] or [PO S RA DQ SX XO]
 class DQ_RD6_RS5_DQ12<bits<6> opcode, bits<3> xo, dag OOL, dag IOL,
                       string asmstr, InstrItinClass itin, list<dag> pattern>
   : I<opcode, OOL, IOL, asmstr, itin> {
   bits<6>  XT;
-  bits<17> addr;
   bits<5> RA;
   bits<12> DQ;
-  let RA = addr{16-12};
-  let DQ = addr{11-0};
 
   let Pattern = pattern;
 
   let Inst{6-10}  = XT{4-0};
   let Inst{11-15} = RA;
   let Inst{16-27} = DQ;
   let Inst{28}    = XT{5};
   let Inst{29-31} = xo;
 }
 
 class DQForm_RTp5_RA17_MEM<bits<6> opcode, bits<4> xo, dag OOL, dag IOL,
                            string asmstr, InstrItinClass itin,
                            list<dag> pattern>
   : I<opcode, OOL, IOL, asmstr, itin> {
   bits<5> RTp;
-  bits<17> addr;
   bits<5> RA;
   bits<12> DQ;
-  let RA = addr{16-12};
-  let DQ = addr{11-0};
   let Pattern = pattern;
 
   let Inst{6-10} =  RTp{4-0};
   let Inst{11-15} = RA;
   let Inst{16-27} = DQ;
   let Inst{28-31} = xo;
 }
 
class XX2_RD6_DCMX7_RS6<bits<6> opcode, bits<4> xo1, bits<3> xo2,
   let Inst{29}    = DCMX{5};
   let Inst{30}    = XB{5};
   let Inst{31}    = XT{5};
 }
 
 class XForm_XD6_RA5_RB5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
                         string asmstr, InstrItinClass itin, list<dag> pattern>
   : I<opcode, OOL, IOL, asmstr, itin> {
-  bits<11> D_RA_XD;
+  bits<5> RA;
+  bits<6> D;
   bits<5> RB;
 
   let Pattern = pattern;
 
-  let Inst{6-10}  = D_RA_XD{4-0};  // D
-  let Inst{11-15} = D_RA_XD{10-6}; // RA
+  let Inst{6-10}  = D{4-0};  // D
+  let Inst{11-15} = RA;
   let Inst{16-20} = RB;
   let Inst{21-30} = xo;
-  let Inst{31}    = D_RA_XD{5};    // DX
+  let Inst{31}    = D{5};    // DX
 }
 
 class XX3Form<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 
               InstrItinClass itin, list<dag> pattern>
   : I<opcode, OOL, IOL, asmstr, itin> {
   bits<6> XT;
   bits<6> XA;
   bits<6> XB;
class XLForm_2_and_DSForm_1<bits<6> opcode1, bits<10> xo1, bit lk,
                             dag OOL, dag IOL, string asmstr,
                             InstrItinClass itin, list<dag> pattern>
         : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> {
   bits<5> BO;
   bits<5> BI;
   bits<2> BH;
 
   bits<5>  RST;
-  bits<19> DS_RA;
+  bits<5>  RA;
+  bits<14> D;
 
   let Pattern = pattern;
 
   let Inst{6-10}  = BO;
   let Inst{11-15} = BI;
   let Inst{16-18} = 0;
   let Inst{19-20} = BH;
   let Inst{21-30} = xo1;
   let Inst{31}    = lk;
 
   let Inst{38-42} = RST;
-  let Inst{43-47} = DS_RA{18-14};  // Register #
-  let Inst{48-61} = DS_RA{13-0};   // Displacement.
+  let Inst{43-47} = RA;
+  let Inst{48-61} = D;
   let Inst{62-63} = xo2;
 }
 
 class XLForm_2_ext_and_DSForm_1<bits<6> opcode1, bits<10> xo1,
                                 bits<5> bo, bits<5> bi, bit lk,
                                 bits<6> opcode2, bits<2> xo2,
                                 dag OOL, dag IOL, string asmstr,
                                 InstrItinClass itin, list<dag> pattern>
   : XLForm_2_and_DSForm_1<opcode1, xo1, lk, opcode2, xo2,
                           OOL, IOL, asmstr, itin, pattern> {
   let BO = bo;
   let BI = bi;
   let BH = 0;
 }
 
 class XLForm_2_ext_and_DForm_1<bits<6> opcode1, bits<10> xo1, bits<5> bo,
                                bits<5> bi, bit lk, bits<6> opcode2, dag OOL,
                                dag IOL, string asmstr, InstrItinClass itin,
                                list<dag> pattern>
   : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> {
 
   bits<5>  RST;
-  bits<21> addr;
+  bits<5>  RA;
+  bits<16> D;
 
   let Pattern = pattern;
 
   let Inst{6-10} = bo;
   let Inst{11-15} = bi;
   let Inst{16-18} = 0;
   let Inst{19-20} = 0;  // Unused (BH)
   let Inst{21-30} = xo1;
   let Inst{31} = lk;
 
   let Inst{38-42} = RST;
-  let Inst{43-47} = addr{20-16};  // Base Register
-  let Inst{48-63} = addr{15-0};   // Displacement
+  let Inst{43-47} = RA;
+  let Inst{48-63} = D;
 }
 
 // 1.7.8 XFX-Form
 class XFXForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
                 InstrItinClass itin>
          : I<opcode, OOL, IOL, asmstr, itin> {
   bits<5>  RST;
   bits<10> SPR;

llvm/lib/Target/PowerPC/PPCInstrInfo.td

 def TCRETURNri : PPCEmitTimePseudo<(outs), (ins CTRRC:$dst, i32imm:$offset),
                  "#TC_RETURNr $dst $offset",
                  []>;
 
 let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1,
     Defs = [LR, R2], Uses = [CTR, RM], RST = 2 in {
   def BCTRL_LWZinto_toc:
     XLForm_2_ext_and_DForm_1<19, 528, 20, 0, 1, 32, (outs),
-     (ins memri:$addr), "bctrl\n\tlwz 2, $addr", IIC_BrB,
+     (ins (memri $D, $RA):$addr), "bctrl\n\tlwz 2, $addr", IIC_BrB,
      [(PPCbctrl_load_toc iaddr:$addr)]>, Requires<[In32BitMode]>;
 
 }
 
 let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1,
     Defs = [LR, R2, RM], Uses = [CTR, RM], RST = 2 in {
   def BCTRL_LWZinto_toc_RM:
     XLForm_2_ext_and_DForm_1<19, 528, 20, 0, 1, 32, (outs),
-     (ins memri:$addr), "bctrl\n\tlwz 2, $addr", IIC_BrB,
+     (ins (memri $D, $RA):$addr), "bctrl\n\tlwz 2, $addr", IIC_BrB,
      [(PPCbctrl_load_toc_rm iaddr:$addr)]>, Requires<[In32BitMode]>;
 
 }
 
 let isCodeGenOnly = 1, hasSideEffects = 0 in {
 
 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
     isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM]  in
def POPCNTB : XForm_11<31, 122, (outs gprc:$RA), (ins gprc:$RST),
                        [(set i32:$RA, (int_ppc_popcntb i32:$RST))]>;
 
 //===----------------------------------------------------------------------===//
 // PPC32 Load Instructions.
 //
 
 // Unindexed (r+i) Loads.
 let PPC970_Unit = 2 in {
-def LBZ : DForm_1<34, (outs gprc:$RST), (ins memri:$addr),
+def LBZ : DForm_1<34, (outs gprc:$RST), (ins (memri $D, $RA):$addr),
                   "lbz $RST, $addr", IIC_LdStLoad,
                   [(set i32:$RST, (zextloadi8 DForm:$addr))]>, ZExt32To64,
                   SExt32To64;
-def LHA : DForm_1<42, (outs gprc:$RST), (ins memri:$addr),
+def LHA : DForm_1<42, (outs gprc:$RST), (ins (memri $D, $RA):$addr),
                   "lha $RST, $addr", IIC_LdStLHA,
                   [(set i32:$RST, (sextloadi16 DForm:$addr))]>,
                   PPC970_DGroup_Cracked, SExt32To64;
-def LHZ : DForm_1<40, (outs gprc:$RST), (ins memri:$addr),
+def LHZ : DForm_1<40, (outs gprc:$RST), (ins (memri $D, $RA):$addr),
                   "lhz $RST, $addr", IIC_LdStLoad,
                   [(set i32:$RST, (zextloadi16 DForm:$addr))]>, ZExt32To64,
                   SExt32To64;
-def LWZ : DForm_1<32, (outs gprc:$RST), (ins memri:$addr),
+def LWZ : DForm_1<32, (outs gprc:$RST), (ins (memri $D, $RA):$addr),
                   "lwz $RST, $addr", IIC_LdStLoad,
                   [(set i32:$RST, (load DForm:$addr))]>, ZExt32To64;
 
 let Predicates = [HasFPU] in {
-def LFS : DForm_1<48, (outs f4rc:$RST), (ins memri:$addr),
+def LFS : DForm_1<48, (outs f4rc:$RST), (ins (memri $D, $RA):$addr),
                   "lfs $RST, $addr", IIC_LdStLFD,
                   [(set f32:$RST, (load DForm:$addr))]>;
-def LFD : DForm_1<50, (outs f8rc:$RST), (ins memri:$addr),
+def LFD : DForm_1<50, (outs f8rc:$RST), (ins (memri $D, $RA):$addr),
                   "lfd $RST, $addr", IIC_LdStLFD,
                   [(set f64:$RST, (load DForm:$addr))]>;
 }
 
 
 // Unindexed (r+i) Loads with Update (preinc).
 let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in {
-def LBZU : DForm_1<35, (outs gprc:$RST, ptr_rc_nor0:$ea_result), (ins memri:$addr),
+def LBZU : DForm_1<35, (outs gprc:$RST, ptr_rc_nor0:$ea_result), (ins (memri $D, $RA):$addr),
                    "lbzu $RST, $addr", IIC_LdStLoadUpd,
-                   []>, RegConstraint<"$addr.reg = $ea_result">,
-                   NoEncode<"$ea_result">;
+                   []>, RegConstraint<"$RA = $ea_result">;
 
-def LHAU : DForm_1<43, (outs gprc:$RST, ptr_rc_nor0:$ea_result), (ins memri:$addr),
+def LHAU : DForm_1<43, (outs gprc:$RST, ptr_rc_nor0:$ea_result), (ins (memri $D, $RA):$addr),
                    "lhau $RST, $addr", IIC_LdStLHAU,
                    []>, RegConstraint<"$addr.reg = $ea_result">,
                    NoEncode<"$ea_result">;
 
-def LHZU : DForm_1<41, (outs gprc:$RST, ptr_rc_nor0:$ea_result), (ins memri:$addr),
+def LHZU : DForm_1<41, (outs gprc:$RST, ptr_rc_nor0:$ea_result), (ins (memri $D, $RA):$addr),
                    "lhzu $RST, $addr", IIC_LdStLoadUpd,
                    []>, RegConstraint<"$addr.reg = $ea_result">,
                    NoEncode<"$ea_result">;
 
-def LWZU : DForm_1<33, (outs gprc:$RST, ptr_rc_nor0:$ea_result), (ins memri:$addr),
+def LWZU : DForm_1<33, (outs gprc:$RST, ptr_rc_nor0:$ea_result), (ins (memri $D, $RA):$addr),
                    "lwzu $RST, $addr", IIC_LdStLoadUpd,
                    []>, RegConstraint<"$addr.reg = $ea_result">,
                    NoEncode<"$ea_result">;
 
 let Predicates = [HasFPU] in {
-def LFSU : DForm_1<49, (outs f4rc:$RST, ptr_rc_nor0:$ea_result), (ins memri:$addr),
+def LFSU : DForm_1<49, (outs f4rc:$RST, ptr_rc_nor0:$ea_result), (ins (memri $D, $RA):$addr),
                   "lfsu $RST, $addr", IIC_LdStLFDU,
                   []>, RegConstraint<"$addr.reg = $ea_result">,
                    NoEncode<"$ea_result">;
 
-def LFDU : DForm_1<51, (outs f8rc:$RST, ptr_rc_nor0:$ea_result), (ins memri:$addr),
+def LFDU : DForm_1<51, (outs f8rc:$RST, ptr_rc_nor0:$ea_result), (ins (memri $D, $RA):$addr),
                   "lfdu $RST, $addr", IIC_LdStLFDU,
                   []>, RegConstraint<"$addr.reg = $ea_result">,
                    NoEncode<"$ea_result">;
 }
 
 
 // Indexed (r+r) Loads with Update (preinc).
 def LBZUX : XForm_1_memOp<31, 119, (outs gprc:$RST, ptr_rc_nor0:$ea_result),

 def LFIWZX : XForm_25_memOp<31, 887, (outs f8rc:$RST), (ins (memrr $RA, $RB):$addr),
                       "lfiwzx $RST, $addr", IIC_LdStLFD,
                       [(set f64:$RST, (PPClfiwzx ForceXForm:$addr))]>;
 }
 }
 
 // Load Multiple
 let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
-def LMW : DForm_1<46, (outs gprc:$RST), (ins memri:$src),
+def LMW : DForm_1<46, (outs gprc:$RST), (ins (memri $D, $RA):$src),
                   "lmw $RST, $src", IIC_LdStLMW, []>;
 
 //===----------------------------------------------------------------------===//
 // PPC32 Store Instructions.
 //
 
 // Unindexed (r+i) Stores.
 let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in {
-def STB  : DForm_1<38, (outs), (ins gprc:$RST, memri:$dst),
+def STB  : DForm_1<38, (outs), (ins gprc:$RST, (memri $D, $RA):$dst),
                    "stb $RST, $dst", IIC_LdStStore,
                    [(truncstorei8 i32:$RST, DForm:$dst)]>;
-def STH  : DForm_1<44, (outs), (ins gprc:$RST, memri:$dst),
+def STH  : DForm_1<44, (outs), (ins gprc:$RST, (memri $D, $RA):$dst),
                    "sth $RST, $dst", IIC_LdStStore,
                    [(truncstorei16 i32:$RST, DForm:$dst)]>;
-def STW  : DForm_1<36, (outs), (ins gprc:$RST, memri:$dst),
+def STW  : DForm_1<36, (outs), (ins gprc:$RST, (memri $D, $RA):$dst),
                    "stw $RST, $dst", IIC_LdStStore,
                    [(store i32:$RST, DForm:$dst)]>;
 let Predicates = [HasFPU] in {
-def STFS : DForm_1<52, (outs), (ins f4rc:$RST, memri:$dst),
+def STFS : DForm_1<52, (outs), (ins f4rc:$RST, (memri $D, $RA):$dst),
                    "stfs $RST, $dst", IIC_LdStSTFD,
                    [(store f32:$RST, DForm:$dst)]>;
-def STFD : DForm_1<54, (outs), (ins f8rc:$RST, memri:$dst),
+def STFD : DForm_1<54, (outs), (ins f8rc:$RST, (memri $D, $RA):$dst),
                    "stfd $RST, $dst", IIC_LdStSTFD,
                    [(store f64:$RST, DForm:$dst)]>;
 }
 }
 
 // Unindexed (r+i) Stores with Update (preinc).
 let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in {
-def STBU  : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins gprc:$RST, memri:$dst),
+def STBU  : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins gprc:$RST, (memri $D, $RA):$dst),
                     "stbu $RST, $dst", IIC_LdStSTU, []>,
                     RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
-def STHU  : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins gprc:$RST, memri:$dst),
+def STHU  : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins gprc:$RST, (memri $D, $RA):$dst),
                     "sthu $RST, $dst", IIC_LdStSTU, []>,
                     RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
-def STWU  : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins gprc:$RST, memri:$dst),
+def STWU  : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins gprc:$RST, (memri $D, $RA):$dst),
                     "stwu $RST, $dst", IIC_LdStSTU, []>,
                     RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
 let Predicates = [HasFPU] in {
-def STFSU : DForm_1<53, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$RST, memri:$dst),
+def STFSU : DForm_1<53, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$RST, (memri $D, $RA):$dst),
                     "stfsu $RST, $dst", IIC_LdStSTFDU, []>,
                     RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
-def STFDU : DForm_1<55, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$RST, memri:$dst),
+def STFDU : DForm_1<55, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$RST, (memri $D, $RA):$dst),
                     "stfdu $RST, $dst", IIC_LdStSTFDU, []>,
                     RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
 }
 }
 
 // Patterns to match the pre-inc stores.  We can't put the patterns on
 // the instruction definitions directly as ISel wants the address base
 // and offset to be separate operands, not a single complex operand.

 def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
           (STFSUX $rS, $ptrreg, $ptroff)>;
 def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
           (STFDUX $rS, $ptrreg, $ptroff)>;
 }
 
 // Store Multiple
 let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in
-def STMW : DForm_1<47, (outs), (ins gprc:$RST, memri:$dst),
+def STMW : DForm_1<47, (outs), (ins gprc:$RST, (memri $D, $RA):$dst),
                    "stmw $RST, $dst", IIC_LdStLMW, []>;
 
 def SYNC : XForm_24_sync<31, 598, (outs), (ins u2imm:$L),
                         "sync $L", IIC_LdStSync, []>;
 
 let isCodeGenOnly = 1 in {
   def MSYNC : XForm_24_sync<31, 598, (outs), (ins),
                            "msync", IIC_LdStSync, []> {
def DWBytes3210 {
   dag DWord =
     (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), Word, sub_32));
 }
 
 // These instructions store a hash computed from the value of the link register
 // and the value of the stack pointer.
 let mayStore = 1 in {
 def HASHST : XForm_XD6_RA5_RB5<31, 722, (outs),
-                               (ins gprc:$RB, memrihash:$D_RA_XD),
-                               "hashst $RB, $D_RA_XD", IIC_IntGeneral, []>;
+                               (ins gprc:$RB, (memrihash $D, $RA):$addr),
+                               "hashst $RB, $addr", IIC_IntGeneral, []>;
 def HASHSTP : XForm_XD6_RA5_RB5<31, 658, (outs),
-                                (ins gprc:$RB, memrihash:$D_RA_XD),
-                                "hashstp $RB, $D_RA_XD", IIC_IntGeneral, []>;
+                                (ins gprc:$RB, (memrihash $D, $RA):$addr),
+                                "hashstp $RB, $addr", IIC_IntGeneral, []>;
 }
 
 // These instructions check a hash computed from the value of the link register
 // and the value of the stack pointer. The hasSideEffects flag is needed as the
 // instruction may TRAP if the hash does not match the hash stored at the
 // specified address.
 let mayLoad = 1, hasSideEffects = 1 in {
 def HASHCHK : XForm_XD6_RA5_RB5<31, 754, (outs),
-                                (ins gprc:$RB, memrihash:$D_RA_XD),
-                                "hashchk $RB, $D_RA_XD", IIC_IntGeneral, []>;
+                                (ins gprc:$RB, (memrihash $D, $RA):$addr),
+                                "hashchk $RB, $addr", IIC_IntGeneral, []>;
 def HASHCHKP : XForm_XD6_RA5_RB5<31, 690, (outs),
-                                 (ins gprc:$RB, memrihash:$D_RA_XD),
-                                 "hashchkp $RB, $D_RA_XD", IIC_IntGeneral, []>;
+                                 (ins gprc:$RB, (memrihash $D, $RA):$addr),
+                                 "hashchkp $RB, $addr", IIC_IntGeneral, []>;
 }
 
 // Now both high word and low word are reversed, next
 // swap the high word and low word.
 def : Pat<(i64 (bitreverse i64:$A)),
   (OR8 (RLDICR DWBytes7654.DWord, 32, 31), DWBytes3210.DWord)>;
 
 def : Pat<(int_ppc_stwcx ForceXForm:$dst, gprc:$A),

llvm/lib/Target/PowerPC/PPCInstrP10.td

def _rec : VXForm_VTB5_RC<xo, R, OOL, IOL,
                                itin, []>, isRecordForm, RecFormRel;
   }
 }
 
 class MLS_DForm_R_SI34_RTA5_MEM<bits<6> opcode, dag OOL, dag IOL, string asmstr,
                                 InstrItinClass itin, list<dag> pattern>
   : PI<1, opcode, OOL, IOL, asmstr, itin> {
   bits<5> RST;
-  bits<39> D_RA;
+  bits<5> RA;
+  bits<34> D;
 
   let Pattern = pattern;
 
   // The prefix.
   let Inst{6-7} = 2;
   let Inst{8-10} = 0;
   let Inst{11} = PCRel;
   let Inst{12-13} = 0;
-  let Inst{14-31} = D_RA{33-16}; // d0
+  let Inst{14-31} = D{33-16}; // d0
 
   // The instruction.
   let Inst{38-42} = RST{4-0};
-  let Inst{43-47} = D_RA{38-34}; // RA
-  let Inst{48-63} = D_RA{15-0}; // d1
+  let Inst{43-47} = RA;
+  let Inst{48-63} = D{15-0}; // d1
 }
 
 class MLS_DForm_R_SI34_RTA5<bits<6> opcode, dag OOL, dag IOL, string asmstr,
                             InstrItinClass itin, list<dag> pattern>
   : PI<1, opcode, OOL, IOL, asmstr, itin> {
   bits<5> RT;
   bits<5> RA;
   bits<34> SI;
multiclass MLS_DForm_R_SI34_RTA5_p<bits<6> opcode, dag OOL, dag IOL,
   def pc : MLS_DForm_R_SI34_RTA5<opcode, OOL, PCRel_IOL,
                                  !strconcat(asmstr, ", 1"), itin, []>, isPCRel;
 }
 
 class 8LS_DForm_R_SI34_RTA5_MEM<bits<6> opcode, dag OOL, dag IOL, string asmstr,
                                 InstrItinClass itin, list<dag> pattern>
   : PI<1, opcode, OOL, IOL, asmstr, itin> {
   bits<5> RST;
-  bits<39> D_RA;
+  bits<5> RA;
+  bits<34> D;
 
   let Pattern = pattern;
 
   // The prefix.
   let Inst{6-10} = 0;
   let Inst{11} = PCRel;
   let Inst{12-13} = 0;
-  let Inst{14-31} = D_RA{33-16}; // d0
+  let Inst{14-31} = D{33-16}; // d0
 
   // The instruction.
   let Inst{38-42} = RST{4-0};
-  let Inst{43-47} = D_RA{38-34}; // RA
-  let Inst{48-63} = D_RA{15-0}; // d1
+  let Inst{43-47} = RA;
+  let Inst{48-63} = D{15-0}; // d1
 }
 
 // 8LS:D-Form: [ 1 0 0 // R // d0
 //               PO TX T RA d1 ]
 class 8LS_DForm_R_SI34_XT6_RA5_MEM<bits<5> opcode, dag OOL, dag IOL,
                                    string asmstr, InstrItinClass itin,
                                    list<dag> pattern>
   : PI<1, { opcode, ? }, OOL, IOL, asmstr, itin> {
   bits<6> XST;
-  bits<39> D_RA;
+  bits<5> RA;
+  bits<34> D;
 
   let Pattern = pattern;
 
   // The prefix.
   let Inst{6-7} = 0;
   let Inst{8} = 0;
   let Inst{9-10} = 0; // reserved
   let Inst{11} = PCRel;
   let Inst{12-13} = 0; // reserved
-  let Inst{14-31} = D_RA{33-16}; // d0
+  let Inst{14-31} = D{33-16}; // d0
 
   // The instruction.
   let Inst{37} = XST{5};
   let Inst{38-42} = XST{4-0};
-  let Inst{43-47} = D_RA{38-34}; // RA
-  let Inst{48-63} = D_RA{15-0}; // d1
+  let Inst{43-47} = RA;
+  let Inst{48-63} = D{15-0}; // d1
 }
 
 // X-Form: [PO T IMM VRB XO TX]
 class XForm_XT6_IMM5_VB5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
                          string asmstr, InstrItinClass itin, list<dag> pattern>
   : I<opcode, OOL, IOL, asmstr, itin> {
   bits<6> XT;
   bits<5> VRB;
let Predicates = [PrefixInstrs] in {
   let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
     def PLI : MLS_DForm_SI34_RT5<14, (outs gprc:$RT),
                                  (ins s34imm:$SI),
                                  "pli $RT, $SI", IIC_IntSimple, []>;
   }
 
   let mayLoad = 1, mayStore = 0 in {
     defm PLXV :
-      8LS_DForm_R_SI34_XT6_RA5_MEM_p<25, (outs vsrc:$XST), (ins memri34:$D_RA),
-                                     (ins memri34_pcrel:$D_RA),
-                                     "plxv $XST, $D_RA", IIC_LdStLFD>;
+      8LS_DForm_R_SI34_XT6_RA5_MEM_p<25, (outs vsrc:$XST), (ins (memri34 $D, $RA):$addr),
+                                     (ins (memri34_pcrel $D, $RA):$addr),
+                                     "plxv $XST, $addr", IIC_LdStLFD>;
     defm PLFS :
-      MLS_DForm_R_SI34_RTA5_MEM_p<48, (outs f4rc:$RST), (ins memri34:$D_RA),
-                                  (ins memri34_pcrel:$D_RA), "plfs $RST, $D_RA",
+      MLS_DForm_R_SI34_RTA5_MEM_p<48, (outs f4rc:$RST), (ins (memri34 $D, $RA):$addr),
+                                  (ins (memri34_pcrel $D, $RA):$addr), "plfs $RST, $addr",
                                   IIC_LdStLFD>;
     defm PLFD :
-      MLS_DForm_R_SI34_RTA5_MEM_p<50, (outs f8rc:$RST), (ins memri34:$D_RA),
-                                  (ins  memri34_pcrel:$D_RA), "plfd $RST, $D_RA",
+      MLS_DForm_R_SI34_RTA5_MEM_p<50, (outs f8rc:$RST), (ins (memri34 $D, $RA):$addr),
+                                  (ins  (memri34_pcrel $D, $RA):$addr), "plfd $RST, $addr",
                                   IIC_LdStLFD>;
     defm PLXSSP :
-      8LS_DForm_R_SI34_RTA5_MEM_p<43, (outs vfrc:$RST), (ins memri34:$D_RA),
-                                  (ins memri34_pcrel:$D_RA),
-                                  "plxssp $RST, $D_RA", IIC_LdStLFD>;
+      8LS_DForm_R_SI34_RTA5_MEM_p<43, (outs vfrc:$RST), (ins (memri34 $D, $RA):$addr),
+                                  (ins (memri34_pcrel $D, $RA):$addr),
+                                  "plxssp $RST, $addr", IIC_LdStLFD>;
     defm PLXSD :
-      8LS_DForm_R_SI34_RTA5_MEM_p<42, (outs vfrc:$RST), (ins memri34:$D_RA),
-                                  (ins memri34_pcrel:$D_RA),
-                                  "plxsd $RST, $D_RA", IIC_LdStLFD>;
+      8LS_DForm_R_SI34_RTA5_MEM_p<42, (outs vfrc:$RST), (ins (memri34 $D, $RA):$addr),
+                                  (ins (memri34_pcrel $D, $RA):$addr),
+                                  "plxsd $RST, $addr", IIC_LdStLFD>;
     let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
       defm PLBZ8 :
-        MLS_DForm_R_SI34_RTA5_MEM_p<34, (outs g8rc:$RST), (ins memri34:$D_RA),
-                                    (ins memri34_pcrel:$D_RA), "plbz $RST, $D_RA",
+        MLS_DForm_R_SI34_RTA5_MEM_p<34, (outs g8rc:$RST), (ins (memri34 $D, $RA):$addr),
+                                    (ins (memri34_pcrel $D, $RA):$addr), "plbz $RST, $addr",
                                     IIC_LdStLFD>;
       defm PLHZ8 :
-        MLS_DForm_R_SI34_RTA5_MEM_p<40, (outs g8rc:$RST), (ins memri34:$D_RA),
-                                    (ins memri34_pcrel:$D_RA), "plhz $RST, $D_RA",
+        MLS_DForm_R_SI34_RTA5_MEM_p<40, (outs g8rc:$RST), (ins (memri34 $D, $RA):$addr),
+                                    (ins (memri34_pcrel $D, $RA):$addr), "plhz $RST, $addr",
                                     IIC_LdStLFD>;
       defm PLHA8 :
-        MLS_DForm_R_SI34_RTA5_MEM_p<42, (outs g8rc:$RST), (ins memri34:$D_RA),
-                                    (ins memri34_pcrel:$D_RA), "plha $RST, $D_RA",
+        MLS_DForm_R_SI34_RTA5_MEM_p<42, (outs g8rc:$RST), (ins (memri34 $D, $RA):$addr),
+                                    (ins (memri34_pcrel $D, $RA):$addr), "plha $RST, $addr",
                                     IIC_LdStLFD>;
       defm PLWA8 :
-        8LS_DForm_R_SI34_RTA5_MEM_p<41, (outs g8rc:$RST), (ins memri34:$D_RA),
-                                    (ins memri34_pcrel:$D_RA),
-                                    "plwa $RST, $D_RA", IIC_LdStLFD>;
+        8LS_DForm_R_SI34_RTA5_MEM_p<41, (outs g8rc:$RST), (ins (memri34 $D, $RA):$addr),
+                                    (ins (memri34_pcrel $D, $RA):$addr),
+                                    "plwa $RST, $addr", IIC_LdStLFD>;
       defm PLWZ8 :
-        MLS_DForm_R_SI34_RTA5_MEM_p<32, (outs g8rc:$RST), (ins memri34:$D_RA),
-                                    (ins memri34_pcrel:$D_RA), "plwz $RST, $D_RA",
+        MLS_DForm_R_SI34_RTA5_MEM_p<32, (outs g8rc:$RST), (ins (memri34 $D, $RA):$addr),
+                                    (ins (memri34_pcrel $D, $RA):$addr), "plwz $RST, $addr",
                                     IIC_LdStLFD>;
     }
     defm PLBZ :
-      MLS_DForm_R_SI34_RTA5_MEM_p<34, (outs gprc:$RST), (ins memri34:$D_RA),
-                                  (ins memri34_pcrel:$D_RA), "plbz $RST, $D_RA",
+      MLS_DForm_R_SI34_RTA5_MEM_p<34, (outs gprc:$RST), (ins (memri34 $D, $RA):$addr),
+                                  (ins (memri34_pcrel $D, $RA):$addr), "plbz $RST, $addr",
                                   IIC_LdStLFD>;
     defm PLHZ :
-      MLS_DForm_R_SI34_RTA5_MEM_p<40, (outs gprc:$RST), (ins memri34:$D_RA),
-                                  (ins memri34_pcrel:$D_RA), "plhz $RST, $D_RA",
+      MLS_DForm_R_SI34_RTA5_MEM_p<40, (outs gprc:$RST), (ins (memri34 $D, $RA):$addr),
+                                  (ins (memri34_pcrel $D, $RA):$addr), "plhz $RST, $addr",
                                   IIC_LdStLFD>;
     defm PLHA :
-      MLS_DForm_R_SI34_RTA5_MEM_p<42, (outs gprc:$RST), (ins memri34:$D_RA),
-                                  (ins memri34_pcrel:$D_RA), "plha $RST, $D_RA",
+      MLS_DForm_R_SI34_RTA5_MEM_p<42, (outs gprc:$RST), (ins (memri34 $D, $RA):$addr),
+                                  (ins (memri34_pcrel $D, $RA):$addr), "plha $RST, $addr",
                                   IIC_LdStLFD>;
     defm PLWZ :
-      MLS_DForm_R_SI34_RTA5_MEM_p<32, (outs gprc:$RST), (ins memri34:$D_RA),
-                                  (ins memri34_pcrel:$D_RA), "plwz $RST, $D_RA",
+      MLS_DForm_R_SI34_RTA5_MEM_p<32, (outs gprc:$RST), (ins (memri34 $D, $RA):$addr),
+                                  (ins (memri34_pcrel $D, $RA):$addr), "plwz $RST, $addr",
                                   IIC_LdStLFD>;
     defm PLWA :
-      8LS_DForm_R_SI34_RTA5_MEM_p<41, (outs gprc:$RST), (ins memri34:$D_RA),
-                                  (ins memri34_pcrel:$D_RA), "plwa $RST, $D_RA",
+      8LS_DForm_R_SI34_RTA5_MEM_p<41, (outs gprc:$RST), (ins (memri34 $D, $RA):$addr),
+                                  (ins (memri34_pcrel $D, $RA):$addr), "plwa $RST, $addr",
                                   IIC_LdStLFD>;
     defm PLD :
-      8LS_DForm_R_SI34_RTA5_MEM_p<57, (outs g8rc:$RST), (ins memri34:$D_RA),
-                                  (ins memri34_pcrel:$D_RA), "pld $RST, $D_RA",
+      8LS_DForm_R_SI34_RTA5_MEM_p<57, (outs g8rc:$RST), (ins (memri34 $D, $RA):$addr),
+                                  (ins (memri34_pcrel $D, $RA):$addr), "pld $RST, $addr",
                                   IIC_LdStLFD>;
   }
 
   let mayStore = 1, mayLoad = 0 in {
     defm PSTXV :
-      8LS_DForm_R_SI34_XT6_RA5_MEM_p<27, (outs), (ins vsrc:$XST, memri34:$D_RA),
-                                     (ins vsrc:$XST, memri34_pcrel:$D_RA),
-                                     "pstxv $XST, $D_RA", IIC_LdStLFD>;
+      8LS_DForm_R_SI34_XT6_RA5_MEM_p<27, (outs), (ins vsrc:$XST, (memri34 $D, $RA):$addr),
+                                     (ins vsrc:$XST, (memri34_pcrel $D, $RA):$addr),
+                                     "pstxv $XST, $addr", IIC_LdStLFD>;
     defm PSTFS :
-      MLS_DForm_R_SI34_RTA5_MEM_p<52, (outs), (ins f4rc:$RST, memri34:$D_RA),
-                                  (ins f4rc:$RST, memri34_pcrel:$D_RA),
-                                  "pstfs $RST, $D_RA", IIC_LdStLFD>;
+      MLS_DForm_R_SI34_RTA5_MEM_p<52, (outs), (ins f4rc:$RST, (memri34 $D, $RA):$addr),
+                                  (ins f4rc:$RST, (memri34_pcrel $D, $RA):$addr),
+                                  "pstfs $RST, $addr", IIC_LdStLFD>;
     defm PSTFD :
-      MLS_DForm_R_SI34_RTA5_MEM_p<54, (outs), (ins f8rc:$RST, memri34:$D_RA),
-                                  (ins f8rc:$RST, memri34_pcrel:$D_RA),
-                                  "pstfd $RST, $D_RA", IIC_LdStLFD>;
+      MLS_DForm_R_SI34_RTA5_MEM_p<54, (outs), (ins f8rc:$RST, (memri34 $D, $RA):$addr),
+                                  (ins f8rc:$RST, (memri34_pcrel $D, $RA):$addr),
+                                  "pstfd $RST, $addr", IIC_LdStLFD>;
     defm PSTXSSP :
-      8LS_DForm_R_SI34_RTA5_MEM_p<47, (outs), (ins vfrc:$RST, memri34:$D_RA),
-                                  (ins vfrc:$RST, memri34_pcrel:$D_RA),
-                                  "pstxssp $RST, $D_RA", IIC_LdStLFD>;
+      8LS_DForm_R_SI34_RTA5_MEM_p<47, (outs), (ins vfrc:$RST, (memri34 $D, $RA):$addr),
+                                  (ins vfrc:$RST, (memri34_pcrel $D, $RA):$addr),
+                                  "pstxssp $RST, $addr", IIC_LdStLFD>;
     defm PSTXSD :
-      8LS_DForm_R_SI34_RTA5_MEM_p<46, (outs), (ins vfrc:$RST, memri34:$D_RA),
-                                  (ins vfrc:$RST, memri34_pcrel:$D_RA),
-                                  "pstxsd $RST, $D_RA", IIC_LdStLFD>;
+      8LS_DForm_R_SI34_RTA5_MEM_p<46, (outs), (ins vfrc:$RST, (memri34 $D, $RA):$addr),
+                                  (ins vfrc:$RST, (memri34_pcrel $D, $RA):$addr),
+                                  "pstxsd $RST, $addr", IIC_LdStLFD>;
     let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
       defm PSTB8 :
-        MLS_DForm_R_SI34_RTA5_MEM_p<38, (outs), (ins g8rc:$RST, memri34:$D_RA),
-                                    (ins g8rc:$RST, memri34_pcrel:$D_RA),
-                                    "pstb $RST, $D_RA", IIC_LdStLFD>;
+        MLS_DForm_R_SI34_RTA5_MEM_p<38, (outs), (ins g8rc:$RST, (memri34 $D, $RA):$addr),
+                                    (ins g8rc:$RST, (memri34_pcrel $D, $RA):$addr),
+                                    "pstb $RST, $addr", IIC_LdStLFD>;
       defm PSTH8 :
-        MLS_DForm_R_SI34_RTA5_MEM_p<44, (outs), (ins g8rc:$RST, memri34:$D_RA),
-                                    (ins g8rc:$RST, memri34_pcrel:$D_RA),
-                                    "psth $RST, $D_RA", IIC_LdStLFD>;
+        MLS_DForm_R_SI34_RTA5_MEM_p<44, (outs), (ins g8rc:$RST, (memri34 $D, $RA):$addr),
+                                    (ins g8rc:$RST, (memri34_pcrel $D, $RA):$addr),
+                                    "psth $RST, $addr", IIC_LdStLFD>;
       defm PSTW8 :
-        MLS_DForm_R_SI34_RTA5_MEM_p<36, (outs), (ins g8rc:$RST, memri34:$D_RA),
-                                    (ins g8rc:$RST, memri34_pcrel:$D_RA),
-                                    "pstw $RST, $D_RA", IIC_LdStLFD>;
+        MLS_DForm_R_SI34_RTA5_MEM_p<36, (outs), (ins g8rc:$RST, (memri34 $D, $RA):$addr),
+                                    (ins g8rc:$RST, (memri34_pcrel $D, $RA):$addr),
+                                    "pstw $RST, $addr", IIC_LdStLFD>;
     }
     defm PSTB :
-      MLS_DForm_R_SI34_RTA5_MEM_p<38, (outs), (ins gprc:$RST, memri34:$D_RA),
-                                  (ins gprc:$RST, memri34_pcrel:$D_RA),
-                                  "pstb $RST, $D_RA", IIC_LdStLFD>;
+      MLS_DForm_R_SI34_RTA5_MEM_p<38, (outs), (ins gprc:$RST, (memri34 $D, $RA):$addr),
+                                  (ins gprc:$RST, (memri34_pcrel $D, $RA):$addr),
+                                  "pstb $RST, $addr", IIC_LdStLFD>;
     defm PSTH :
-      MLS_DForm_R_SI34_RTA5_MEM_p<44, (outs), (ins gprc:$RST, memri34:$D_RA),
-                                  (ins gprc:$RST, memri34_pcrel:$D_RA),
-                                  "psth $RST, $D_RA", IIC_LdStLFD>;
+      MLS_DForm_R_SI34_RTA5_MEM_p<44, (outs), (ins gprc:$RST, (memri34 $D, $RA):$addr),
+                                  (ins gprc:$RST, (memri34_pcrel $D, $RA):$addr),
+                                  "psth $RST, $addr", IIC_LdStLFD>;
     defm PSTW :
-      MLS_DForm_R_SI34_RTA5_MEM_p<36, (outs), (ins gprc:$RST, memri34:$D_RA),
-                                  (ins gprc:$RST, memri34_pcrel:$D_RA),
-                                  "pstw $RST, $D_RA", IIC_LdStLFD>;
+      MLS_DForm_R_SI34_RTA5_MEM_p<36, (outs), (ins gprc:$RST, (memri34 $D, $RA):$addr),
+                                  (ins gprc:$RST, (memri34_pcrel $D, $RA):$addr),
+                                  "pstw $RST, $addr", IIC_LdStLFD>;
     defm PSTD :
-      8LS_DForm_R_SI34_RTA5_MEM_p<61, (outs), (ins g8rc:$RST, memri34:$D_RA),
-                                  (ins g8rc:$RST, memri34_pcrel:$D_RA),
-                                  "pstd $RST, $D_RA", IIC_LdStLFD>;
+      8LS_DForm_R_SI34_RTA5_MEM_p<61, (outs), (ins g8rc:$RST, (memri34 $D, $RA):$addr),
+                                  (ins g8rc:$RST, (memri34_pcrel $D, $RA):$addr),
+                                  "pstd $RST, $addr", IIC_LdStLFD>;
   }
 }
 
 class DQForm_XTp5_RA17_MEM<bits<6> opcode, bits<4> xo, dag OOL, dag IOL,
                            string asmstr, InstrItinClass itin, list<dag> pattern>
   : I<opcode, OOL, IOL, asmstr, itin> {
   bits<5> XTp;
-  bits<17> DQ_RA;
+  bits<5> RA;
+  bits<12> DQ;
+
   let Pattern = pattern;
 
   let Inst{6-9} = XTp{3-0};
   let Inst{10} = XTp{4};
-  let Inst{11-15} = DQ_RA{16-12};  // Register #
-  let Inst{16-27} = DQ_RA{11-0};   // Displacement.
+  let Inst{11-15} = RA;
+  let Inst{16-27} = DQ;
   let Inst{28-31} = xo;
 }
 
 class XForm_XTp5_XAB5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
                       string asmstr, InstrItinClass itin, list<dag> pattern>
   : I<opcode, OOL, IOL, asmstr, itin>, XFormMemOp {
   bits<5> XTp;
   bits<5> RA;
   bits<5> RB;
 
   let Pattern = pattern;
   let Inst{6-9} = XTp{3-0};
   let Inst{10} = XTp{4};
   let Inst{11-15} = RA;
   let Inst{16-20} = RB;
   let Inst{21-30} = xo;
   let Inst{31} = 0;
 }
 
 class 8LS_DForm_R_XTp5_SI34_MEM<bits<6> opcode, dag OOL, dag IOL, string asmstr,
                                 InstrItinClass itin, list<dag> pattern>
   : PI<1, opcode, OOL, IOL, asmstr, itin> {
   bits<5> XTp;
-  bits<39> D_RA;
+  bits<5> RA;
+  bits<34> D;
 
   let Pattern = pattern;
 
   // The prefix.
   let Inst{6-10} = 0;
   let Inst{11} = PCRel;
   let Inst{12-13} = 0;
-  let Inst{14-31} = D_RA{33-16}; // Imm18
+  let Inst{14-31} = D{33-16}; // Imm18
 
   // The instruction.
   let Inst{38-41} = XTp{3-0};
   let Inst{42}    = XTp{4};
-  let Inst{43-47} = D_RA{38-34};   // Register #
-  let Inst{48-63} = D_RA{15-0};    // D
+  let Inst{43-47} = RA;
+  let Inst{48-63} = D{15-0};
 }
 
 multiclass 8LS_DForm_R_XTp5_SI34_MEM_p<bits<6> opcode, dag OOL,
                                        dag IOL, dag PCRel_IOL,
                                        string asmstr, InstrItinClass itin> {
   def NAME : 8LS_DForm_R_XTp5_SI34_MEM<opcode, OOL, IOL,
                                        !strconcat(asmstr, ", 0"), itin, []>;
   def pc : 8LS_DForm_R_XTp5_SI34_MEM<opcode, OOL, PCRel_IOL,
let Predicates = [PairedVectorMemops] in {
   def : Pat<(v4i32 (PPCPairExtractVsx vsrpevenrc:$v, 0)),
             (v4i32 (EXTRACT_SUBREG $v, sub_vsx0))>;
   def : Pat<(v4i32 (PPCPairExtractVsx vsrpevenrc:$v, 1)),
             (v4i32 (EXTRACT_SUBREG $v, sub_vsx1))>;
 }
 
 let mayLoad = 1, mayStore = 0, Predicates = [PairedVectorMemops] in {
   def LXVP : DQForm_XTp5_RA17_MEM<6, 0, (outs vsrprc:$XTp),
-                                  (ins memrix16:$DQ_RA), "lxvp $XTp, $DQ_RA",
+                                  (ins (memrix16 $DQ, $RA):$addr), "lxvp $XTp, $addr",
                                   IIC_LdStLFD, []>;
   def LXVPX : XForm_XTp5_XAB5<31, 333, (outs vsrprc:$XTp), (ins (memrr $RA, $RB):$addr),
                               "lxvpx $XTp, $addr", IIC_LdStLFD,
                               []>;
 }
 
 let mayLoad = 0, mayStore = 1, Predicates = [PairedVectorMemops] in {
   def STXVP : DQForm_XTp5_RA17_MEM<6, 1, (outs), (ins vsrprc:$XTp,
-                                   memrix16:$DQ_RA), "stxvp $XTp, $DQ_RA",
+                                   (memrix16 $DQ, $RA):$addr), "stxvp $XTp, $addr",
                                    IIC_LdStLFD, []>;
   def STXVPX : XForm_XTp5_XAB5<31, 461, (outs), (ins vsrprc:$XTp, (memrr $RA, $RB):$addr),
                                "stxvpx $XTp, $addr", IIC_LdStLFD,
                                []>;
 }
 
 let mayLoad = 1, mayStore = 0, Predicates = [PairedVectorMemops, PrefixInstrs] in {
   defm PLXVP :
-    8LS_DForm_R_XTp5_SI34_MEM_p<58, (outs vsrprc:$XTp), (ins memri34:$D_RA),
-                                (ins memri34_pcrel:$D_RA), "plxvp $XTp, $D_RA",
+    8LS_DForm_R_XTp5_SI34_MEM_p<58, (outs vsrprc:$XTp), (ins (memri34 $D, $RA):$addr),
+                                (ins (memri34_pcrel $D, $RA):$addr), "plxvp $XTp, $addr",
                                 IIC_LdStLFD>;
 }
 
 let mayLoad = 0, mayStore = 1, Predicates = [PairedVectorMemops, PrefixInstrs] in {
   defm PSTXVP :
-    8LS_DForm_R_XTp5_SI34_MEM_p<62, (outs), (ins vsrprc:$XTp, memri34:$D_RA),
-                                (ins vsrprc:$XTp, memri34_pcrel:$D_RA),
-                                "pstxvp $XTp, $D_RA", IIC_LdStLFD>;
+    8LS_DForm_R_XTp5_SI34_MEM_p<62, (outs), (ins vsrprc:$XTp, (memri34 $D, $RA):$addr),
+                                (ins vsrprc:$XTp, (memri34_pcrel $D, $RA):$addr),
+                                "pstxvp $XTp, $addr", IIC_LdStLFD>;
 }
 
 let Predicates = [PairedVectorMemops] in {
   // Intrinsics for Paired Vector Loads.
   def : Pat<(v256i1 (int_ppc_vsx_lxvp DQForm:$src)), (LXVP memrix16:$src)>;
   def : Pat<(v256i1 (int_ppc_vsx_lxvp XForm:$src)), (LXVPX XForm:$src)>;
   let Predicates = [PairedVectorMemops, PrefixInstrs] in {
     def : Pat<(v256i1 (int_ppc_vsx_lxvp PDForm:$src)), (PLXVP memri34:$src)>;

llvm/lib/Target/PowerPC/PPCInstrSPE.td

class EVXForm_4<bits<8> xo, dag OOL, dag IOL, string asmstr,
   let Inst{21-28} = xo;
   let Inst{29-31} = crD;
 }
 
 class EVXForm_D<bits<11> xo, dag OOL, dag IOL, string asmstr,
                InstrItinClass itin, list<dag> pattern> :
                I<4, OOL, IOL, asmstr, itin> {
   bits<5> RT;
-  // FIXME: bogus names, to force positional matching for the moment.
-  bits<21> dst_foo;
+  bits<5> RA;
+  bits<5> D;
 
   let Pattern = pattern;
 
   let Inst{6-10}  = RT;
-  let Inst{11-20} = dst_foo{0-9};
+  let Inst{11-15} = RA;
+  let Inst{16-20} = D;
   let Inst{21-31} = xo;
 }
 
 let DecoderNamespace = "SPE", Predicates = [HasSPE] in {
 
 def BRINC          : EVXForm_1<527, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB),
                                "brinc $RT, $RA, $RB", IIC_IntSimple, []>;
 

 def EVFSTSTEQ       : EVXForm_3<670, (outs crrc:$crD), (ins sperc:$RA, sperc:$RB),
                                "evfststeq $crD, $RA, $RB", IIC_VecGeneral, []>;
 def EVFSTSTGT       : EVXForm_3<668, (outs crrc:$crD), (ins sperc:$RA, sperc:$RB),
                                "evfststgt $crD, $RA, $RB", IIC_VecGeneral, []>;
 def EVFSTSTLT       : EVXForm_3<669, (outs crrc:$crD), (ins sperc:$RA, sperc:$RB),
                                "evfststlt $crD, $RA, $RB", IIC_VecGeneral, []>;
 }
 
-def EVLDD          : EVXForm_D<769, (outs sperc:$RT), (ins spe8dis:$dst),
+def EVLDD          : EVXForm_D<769, (outs sperc:$RT), (ins (spe8dis $D, $RA):$dst),
                                "evldd $RT, $dst", IIC_LdStLoad,
                                [(set f64:$RT, (load iaddr:$dst))]>;
 def EVLDDX         : EVXForm_1<768, (outs sperc:$RT), (ins (memrr $RA, $RB):$src),
                                "evlddx $RT, $src", IIC_LdStLoad,
                                [(set f64:$RT, (load xaddr:$src))]>;
-def EVLDH          : EVXForm_D<773, (outs sperc:$RT), (ins spe8dis:$dst),
+def EVLDH          : EVXForm_D<773, (outs sperc:$RT), (ins (spe8dis $D, $RA):$dst),
                                "evldh $RT, $dst", IIC_LdStLoad, []>;
 def EVLDHX         : EVXForm_1<772, (outs sperc:$RT), (ins (memrr $RA, $RB):$src),
                                "evldhx $RT, $src", IIC_LdStLoad, []>;
-def EVLDW          : EVXForm_D<771, (outs sperc:$RT), (ins spe8dis:$dst),
+def EVLDW          : EVXForm_D<771, (outs sperc:$RT), (ins (spe8dis $D, $RA):$dst),
                                "evldw $RT, $dst", IIC_LdStLoad,
                                []>;
 def EVLDWX         : EVXForm_1<770, (outs sperc:$RT), (ins (memrr $RA, $RB):$src),
                                "evldwx $RT, $src", IIC_LdStLoad,
                                []>;
-def EVLHHESPLAT    : EVXForm_D<777, (outs sperc:$RT), (ins spe2dis:$dst),
+def EVLHHESPLAT    : EVXForm_D<777, (outs sperc:$RT), (ins (spe2dis $D, $RA):$dst),
                                "evlhhesplat $RT, $dst", IIC_LdStLoad, []>;
 def EVLHHESPLATX   : EVXForm_1<776, (outs sperc:$RT), (ins (memrr $RA, $RB):$src),
                                "evlhhesplatx $RT, $src", IIC_LdStLoad, []>;
-def EVLHHOUSPLAT   : EVXForm_D<781, (outs sperc:$RT), (ins spe2dis:$dst),
+def EVLHHOUSPLAT   : EVXForm_D<781, (outs sperc:$RT), (ins (spe2dis $D, $RA):$dst),
                                "evlhhousplat $RT, $dst", IIC_LdStLoad, []>;
 def EVLHHOUSPLATX  : EVXForm_1<780, (outs sperc:$RT), (ins (memrr $RA, $RB):$src),
                                "evlhhousplatx $RT, $src", IIC_LdStLoad, []>;
-def EVLHHOSSPLAT   : EVXForm_D<783, (outs sperc:$RT), (ins spe2dis:$dst),
+def EVLHHOSSPLAT   : EVXForm_D<783, (outs sperc:$RT), (ins (spe2dis $D, $RA):$dst),
                                "evlhhossplat $RT, $dst", IIC_LdStLoad, []>;
 def EVLHHOSSPLATX  : EVXForm_1<782, (outs sperc:$RT), (ins (memrr $RA, $RB):$src),
                                "evlhhossplatx $RT, $src", IIC_LdStLoad, []>;
-def EVLWHE         : EVXForm_D<785, (outs sperc:$RT), (ins spe4dis:$dst),
+def EVLWHE         : EVXForm_D<785, (outs sperc:$RT), (ins (spe4dis $D, $RA):$dst),
                                "evlwhe $RT, $dst", IIC_LdStLoad, []>;
 def EVLWHEX        : EVXForm_1<784, (outs sperc:$RT), (ins (memrr $RA, $RB):$src),
                                "evlwhex $RT, $src", IIC_LdStLoad, []>;
-def EVLWHOS        : EVXForm_D<791, (outs sperc:$RT), (ins spe4dis:$dst),
+def EVLWHOS        : EVXForm_D<791, (outs sperc:$RT), (ins (spe4dis $D, $RA):$dst),
                                "evlwhos $RT, $dst", IIC_LdStLoad, []>;
 def EVLWHOSX       : EVXForm_1<790, (outs sperc:$RT), (ins (memrr $RA, $RB):$src),
                                "evlwhosx $RT, $src", IIC_LdStLoad, []>;
-def EVLWHOU        : EVXForm_D<789, (outs sperc:$RT), (ins spe4dis:$dst),
+def EVLWHOU        : EVXForm_D<789, (outs sperc:$RT), (ins (spe4dis $D, $RA):$dst),
                                "evlwhou $RT, $dst", IIC_LdStLoad, []>;
 def EVLWHOUX       : EVXForm_1<788, (outs sperc:$RT), (ins (memrr $RA, $RB):$src),
                                "evlwhoux $RT, $src", IIC_LdStLoad, []>;
-def EVLWHSPLAT     : EVXForm_D<797, (outs sperc:$RT), (ins spe4dis:$dst),
+def EVLWHSPLAT     : EVXForm_D<797, (outs sperc:$RT), (ins (spe4dis $D, $RA):$dst),
                                "evlwhsplat $RT, $dst", IIC_LdStLoad, []>;
 def EVLWHSPLATX    : EVXForm_1<796, (outs sperc:$RT), (ins (memrr $RA, $RB):$src),
                                "evlwhsplatx $RT, $src", IIC_LdStLoad, []>;
-def EVLWWSPLAT     : EVXForm_D<793, (outs sperc:$RT), (ins spe4dis:$dst),
+def EVLWWSPLAT     : EVXForm_D<793, (outs sperc:$RT), (ins (spe4dis $D, $RA):$dst),
                                "evlwwsplat $RT, $dst", IIC_LdStLoad, []>;
 def EVLWWSPLATX    : EVXForm_1<792, (outs sperc:$RT), (ins (memrr $RA, $RB):$src),
                                "evlwwsplatx $RT, $src", IIC_LdStLoad, []>;
 
 def EVMERGEHI      : EVXForm_1<556, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
                                "evmergehi $RT, $RA, $RB", IIC_VecGeneral, []>;
 def EVMERGELO      : EVXForm_1<557, (outs sperc:$RT), (ins gprc:$RA, gprc:$RB),
                                "evmergelo $RT, $RA, $RB", IIC_VecGeneral, []>;
def EVSRWIU        : EVXForm_1<546, (outs sperc:$RT), (ins sperc:$RA, u5imm:$RB),
                                "evsrwiu $RT, $RA, $RB", IIC_VecGeneral, []>;
 def EVSRWS         : EVXForm_1<545, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
                                "evsrws $RT, $RA, $RB", IIC_VecGeneral,
                                []>;
 def EVSRWU         : EVXForm_1<544, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
                                "evsrwu $RT, $RA, $RB", IIC_VecGeneral,
                                []>;
 
-def EVSTDD         : EVXForm_D<801, (outs), (ins sperc:$RT, spe8dis:$dst),
+def EVSTDD         : EVXForm_D<801, (outs), (ins sperc:$RT, (spe8dis $D, $RA):$dst),
                                "evstdd $RT, $dst", IIC_LdStStore,
                                [(store f64:$RT, iaddr:$dst)]>;
 def EVSTDDX        : EVXForm_1<800, (outs), (ins sperc:$RT, (memrr $RA, $RB):$dst),
                                "evstddx $RT, $dst", IIC_LdStStore,
                                [(store f64:$RT, xaddr:$dst)]>;
-def EVSTDH         : EVXForm_D<805, (outs), (ins sperc:$RT, spe8dis:$dst),
+def EVSTDH         : EVXForm_D<805, (outs), (ins sperc:$RT, (spe8dis $D, $RA):$dst),
                                "evstdh $RT, $dst", IIC_LdStStore, []>;
 def EVSTDHX        : EVXForm_1<804, (outs), (ins sperc:$RT, (memrr $RA, $RB):$dst),
                                "evstdhx $RT, $dst", IIC_LdStStore, []>;
-def EVSTDW         : EVXForm_D<803, (outs), (ins sperc:$RT, spe8dis:$dst),
+def EVSTDW         : EVXForm_D<803, (outs), (ins sperc:$RT, (spe8dis $D, $RA):$dst),
                                "evstdw $RT, $dst", IIC_LdStStore,
                                []>;
 def EVSTDWX        : EVXForm_1<802, (outs), (ins sperc:$RT, (memrr $RA, $RB):$dst),
                                "evstdwx $RT, $dst", IIC_LdStStore,
                                []>;
-def EVSTWHE        : EVXForm_D<817, (outs), (ins sperc:$RT, spe4dis:$dst),
+def EVSTWHE        : EVXForm_D<817, (outs), (ins sperc:$RT, (spe4dis $D, $RA):$dst),
                                "evstwhe $RT, $dst", IIC_LdStStore, []>;
 def EVSTWHEX       : EVXForm_1<816, (outs), (ins sperc:$RT, (memrr $RA, $RB):$dst),
                                "evstwhex $RT, $dst", IIC_LdStStore, []>;
-def EVSTWHO        : EVXForm_D<821, (outs), (ins sperc:$RT, spe4dis:$dst),
+def EVSTWHO        : EVXForm_D<821, (outs), (ins sperc:$RT, (spe4dis $D, $RA):$dst),
                                "evstwho $RT, $dst", IIC_LdStStore, []>;
 def EVSTWHOX       : EVXForm_1<820, (outs), (ins sperc:$RT, (memrr $RA, $RB):$dst),
                                "evstwhox $RT, $dst", IIC_LdStStore, []>;
-def EVSTWWE        : EVXForm_D<825, (outs), (ins sperc:$RT, spe4dis:$dst),
+def EVSTWWE        : EVXForm_D<825, (outs), (ins sperc:$RT, (spe4dis $D, $RA):$dst),
                                "evstwwe $RT, $dst", IIC_LdStStore, []>;
 def EVSTWWEX       : EVXForm_1<824, (outs), (ins sperc:$RT, (memrr $RA, $RB):$dst),
                                "evstwwex $RT, $dst", IIC_LdStStore, []>;
-def EVSTWWO        : EVXForm_D<829, (outs), (ins sperc:$RT, spe4dis:$dst),
+def EVSTWWO        : EVXForm_D<829, (outs), (ins sperc:$RT, (spe4dis $D, $RA):$dst),
                                "evstwwo $RT, $dst", IIC_LdStStore, []>;
 def EVSTWWOX       : EVXForm_1<828, (outs), (ins sperc:$RT, (memrr $RA, $RB):$dst),
                                "evstwwox $RT, $dst", IIC_LdStStore, []>;
 
 def EVSUBFSSIAAW   : EVXForm_2<1219, (outs sperc:$RT), (ins sperc:$RA),
                                "evsubfssiaaw $RT, $RA", IIC_VecComplex, []>;
 def EVSUBFSMIAAW   : EVXForm_2<1227, (outs sperc:$RT), (ins sperc:$RA),
                                "evsubfsmiaaw $RT, $RA", IIC_VecComplex, []>;
 def EVSUBFUMIAAW   : EVXForm_2<1226, (outs sperc:$RT), (ins sperc:$RA),
                                "evsubfumiaaw $RT, $RA", IIC_VecComplex, []>;
 def EVSUBFUSIAAW   : EVXForm_2<1218, (outs sperc:$RT), (ins sperc:$RA),
                                "evsubfusiaaw $RT, $RA", IIC_VecComplex, []>;
 def EVSUBFW        : EVXForm_1<516, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
                                "evsubfw $RT, $RA, $RB", IIC_VecGeneral,
                                []>;
 def EVSUBIFW       : EVXForm_1<518, (outs sperc:$RT), (ins u5imm:$RA, sperc:$RB),
                                "evsubifw $RT, $RA, $RB", IIC_VecGeneral, []>;
 def EVXOR          : EVXForm_1<534, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
                                "evxor $RT, $RA, $RB", IIC_VecGeneral,
                                []>;
 
 let isAsmParserOnly = 1 in {
 // Identical to the integer Load/Stores, but to handle floats
-def SPELWZ        : DForm_1<32, (outs spe4rc:$RST), (ins memri:$addr),
+def SPELWZ        : DForm_1<32, (outs spe4rc:$RST), (ins (memri $D, $RA):$addr),
                             "lwz $RST, $addr", IIC_LdStLoad,
                             [(set f32:$RST, (load iaddr:$addr))]>;
 def SPELWZX       : XForm_1<31,  23, (outs spe4rc:$RST), (ins (memrr $RA, $RB):$addr),
                             "lwzx $RST, $addr", IIC_LdStLoad,
                             [(set f32:$RST, (load xaddr:$addr))]>;
-def SPESTW        : DForm_1<36, (outs), (ins spe4rc:$RST, memri:$addr),
+def SPESTW        : DForm_1<36, (outs), (ins spe4rc:$RST, (memri $D, $RA):$addr),
                             "stw $RST, $addr", IIC_LdStStore,
                             [(store f32:$RST, iaddr:$addr)]>;
 def SPESTWX       : XForm_8<31, 151, (outs), (ins spe4rc:$RST, (memrr $RA, $RB):$addr),
                            "stwx $RST, $addr", IIC_LdStStore,
                            [(store f32:$RST, xaddr:$addr)]>;
 }
 
 } // HasSPE

llvm/lib/Target/PowerPC/PPCInstrVSX.td

let Predicates = [HasVSX, HasP9Vector] in {
   let hasSideEffects = 1 in
   def XXSPLTIB : X_RD6_IMM8<60, 360, (outs vsrc:$XT), (ins u8imm:$IMM8),
                             "xxspltib $XT, $IMM8", IIC_VecPerm, []>;
 
   // When adding new D-Form loads/stores, be sure to update the ImmToIdxMap in
   // PPCRegisterInfo::PPCRegisterInfo and maybe save yourself some debugging.
   let mayLoad = 1, mayStore = 0 in {
   // Load Vector
-  def LXV : DQ_RD6_RS5_DQ12<61, 1, (outs vsrc:$XT), (ins memrix16:$addr),
+  def LXV : DQ_RD6_RS5_DQ12<61, 1, (outs vsrc:$XT), (ins (memrix16 $DQ, $RA):$addr),
                             "lxv $XT, $addr", IIC_LdStLFD, []>;
   // Load DWord
-  def LXSD  : DSForm_1<57, 2, (outs vfrc:$RST), (ins memrix:$addr),
+  def LXSD  : DSForm_1<57, 2, (outs vfrc:$RST), (ins (memrix $D, $RA):$addr),
                        "lxsd $RST, $addr", IIC_LdStLFD, []>;
   // Load SP from src, convert it to DP, and place in dword[0]
-  def LXSSP : DSForm_1<57, 3, (outs vfrc:$RST), (ins memrix:$addr),
+  def LXSSP : DSForm_1<57, 3, (outs vfrc:$RST), (ins (memrix $D, $RA):$addr),
                        "lxssp $RST, $addr", IIC_LdStLFD, []>;
 
   // Load as Integer Byte/Halfword & Zero Indexed
   def LXSIBZX : X_XT6_RA5_RB5<31, 781, "lxsibzx", vsfrc,
                               [(set f64:$XT, (PPClxsizx ForceXForm:$addr, 1))]>;
   def LXSIHZX : X_XT6_RA5_RB5<31, 813, "lxsihzx", vsfrc,
                               [(set f64:$XT, (PPClxsizx ForceXForm:$addr, 2))]>;
 
let Predicates = [HasVSX, HasP9Vector] in {
   // Load Vector Word & Splat Indexed
   def LXVWSX  : X_XT6_RA5_RB5<31, 364, "lxvwsx" , vsrc, []>;
   } // mayLoad
 
   // When adding new D-Form loads/stores, be sure to update the ImmToIdxMap in
   // PPCRegisterInfo::PPCRegisterInfo and maybe save yourself some debugging.
   let mayStore = 1, mayLoad = 0 in {
   // Store Vector
-  def STXV : DQ_RD6_RS5_DQ12<61, 5, (outs), (ins vsrc:$XT, memrix16:$addr),
+  def STXV : DQ_RD6_RS5_DQ12<61, 5, (outs), (ins vsrc:$XT, (memrix16 $DQ, $RA):$addr),
                              "stxv $XT, $addr", IIC_LdStSTFD, []>;
   // Store DWord
-  def STXSD  : DSForm_1<61, 2, (outs), (ins vfrc:$RST, memrix:$addr),
+  def STXSD  : DSForm_1<61, 2, (outs), (ins vfrc:$RST, (memrix $D, $RA):$addr),
                         "stxsd $RST, $addr", IIC_LdStSTFD, []>;
   // Convert DP of dword[0] to SP, and Store to dst
-  def STXSSP : DSForm_1<61, 3, (outs), (ins vfrc:$RST, memrix:$addr),
+  def STXSSP : DSForm_1<61, 3, (outs), (ins vfrc:$RST, (memrix $D, $RA):$addr),
                         "stxssp $RST, $addr", IIC_LdStSTFD, []>;
 
   // Store as Integer Byte/Halfword Indexed
   def STXSIBX  : X_XS6_RA5_RB5<31,  909, "stxsibx" , vsfrc,
                                [(PPCstxsix f64:$XT, ForceXForm:$addr, 1)]>;
   def STXSIHX  : X_XS6_RA5_RB5<31,  941, "stxsihx" , vsfrc,
                                [(PPCstxsix f64:$XT, ForceXForm:$addr, 2)]>;
   let isCodeGenOnly = 1 in {

llvm/lib/Target/PowerPC/PPCRegisterInfo.td

 
 // New addressing modes with 34 bit immediates.
 def PPCDispRI34Operand : AsmOperandClass {
   let Name = "DispRI34"; let PredicateMethod = "isS34Imm";
   let RenderMethod = "addImmOperands";
 }
 def dispRI34 : Operand<iPTR> {
   let ParserMatchClass = PPCDispRI34Operand;
+  let EncoderMethod = "getDispRI34Encoding";
+  let DecoderMethod = "decodeSImmOperand<34>";
+}
+def dispRI34_pcrel : Operand<iPTR> {
+  let ParserMatchClass = PPCDispRI34Operand;
+  let EncoderMethod = "getDispRI34PCRelEncoding";
+  let DecoderMethod = "decodeSImmOperand<34>";
 }
 def memri34 : Operand<iPTR> { // memri, imm is a 34-bit value.
   let PrintMethod = "printMemRegImm34";
   let MIOperandInfo = (ops dispRI34:$imm, ptr_rc_nor0:$reg);
-  let EncoderMethod = "getMemRI34Encoding";
-  let DecoderMethod = "decodeMemRI34Operands";
 }
 // memri, imm is a 34-bit value for pc-relative instructions where
 // base register is set to zero.
 def memri34_pcrel : Operand<iPTR> { // memri, imm is a 34-bit value.
   let PrintMethod = "printMemRegImm34PCRel";
-  let MIOperandInfo = (ops dispRI34:$imm, immZero:$reg);
-  let EncoderMethod = "getMemRI34PCRelEncoding";
-  let DecoderMethod = "decodeMemRI34PCRelOperands";
+  let MIOperandInfo = (ops dispRI34_pcrel:$imm, immZero:$reg);
 }
 
 // A version of ptr_rc usable with the asm parser.
 def PPCRegGxRCOperand : AsmOperandClass {
   let Name = "RegGxRC"; let PredicateMethod = "isRegNumber";
 }
 def ptr_rc_idx : Operand<iPTR>, PointerLikeRegClass<0> {
   let ParserMatchClass = PPCRegGxRCOperand;
 }
 
 def PPCDispRIOperand : AsmOperandClass {
  let Name = "DispRI"; let PredicateMethod = "isS16Imm";
  let RenderMethod = "addS16ImmOperands";
 }
 def dispRI : Operand<iPTR> {
   let ParserMatchClass = PPCDispRIOperand;
+  let EncoderMethod = "getDispRIEncoding";
 }
 def PPCDispRIXOperand : AsmOperandClass {
  let Name = "DispRIX"; let PredicateMethod = "isS16ImmX4";
  let RenderMethod = "addS16ImmOperands";
 }
 def dispRIX : Operand<iPTR> {
   let ParserMatchClass = PPCDispRIXOperand;
+  let EncoderMethod = "getDispRIXEncoding";
+  let DecoderMethod = "decodeDispRIXOperand";
 }
 def PPCDispRIHashOperand : AsmOperandClass {
   let Name = "DispRIHash"; let PredicateMethod = "isHashImmX8";
   let RenderMethod = "addImmOperands";
 }
 def dispRIHash : Operand<iPTR> {
   let ParserMatchClass = PPCDispRIHashOperand;
+  let EncoderMethod = "getDispRIHashEncoding";
+  let DecoderMethod = "decodeDispRIHashOperand";
 }
 def PPCDispRIX16Operand : AsmOperandClass {
  let Name = "DispRIX16"; let PredicateMethod = "isS16ImmX16";
  let RenderMethod = "addS16ImmOperands";
 }
 def dispRIX16 : Operand<iPTR> {
   let ParserMatchClass = PPCDispRIX16Operand;
+  let EncoderMethod = "getDispRIX16Encoding";
+  let DecoderMethod = "decodeDispRIX16Operand";
+
 }
 def PPCDispSPE8Operand : AsmOperandClass {
  let Name = "DispSPE8"; let PredicateMethod = "isU8ImmX8";
  let RenderMethod = "addImmOperands";
 }
 def dispSPE8 : Operand<iPTR> {
   let ParserMatchClass = PPCDispSPE8Operand;
+  let DecoderMethod = "decodeDispSPE8Operand";
+  let EncoderMethod = "getDispSPE8Encoding";
 }
 def PPCDispSPE4Operand : AsmOperandClass {
  let Name = "DispSPE4"; let PredicateMethod = "isU7ImmX4";
  let RenderMethod = "addImmOperands";
 }
 def dispSPE4 : Operand<iPTR> {
   let ParserMatchClass = PPCDispSPE4Operand;
+  let DecoderMethod = "decodeDispSPE4Operand";
+  let EncoderMethod = "getDispSPE4Encoding";
 }
 def PPCDispSPE2Operand : AsmOperandClass {
  let Name = "DispSPE2"; let PredicateMethod = "isU6ImmX2";
  let RenderMethod = "addImmOperands";
 }
 def dispSPE2 : Operand<iPTR> {
   let ParserMatchClass = PPCDispSPE2Operand;
+  let DecoderMethod = "decodeDispSPE2Operand";
+  let EncoderMethod = "getDispSPE2Encoding";
 }
 
-// FIXME: Remove the functions like getMemRIEncoding and decodeMemRIOperands,
-// and adjust the instruction definitions. There's no need to artificially merge
-// the values into a single field anymore, now that sub-operands can be named in
-// instruction definitions.
 def memri : Operand<iPTR> {
   let PrintMethod = "printMemRegImm";
   let MIOperandInfo = (ops dispRI:$imm, ptr_rc_nor0:$reg);
-  let EncoderMethod = "getMemRIEncoding";
-  let DecoderMethod = "decodeMemRIOperands";
   let OperandType = "OPERAND_MEMORY";
 }
 def memrr : Operand<iPTR> {
   let PrintMethod = "printMemRegReg";
   let MIOperandInfo = (ops ptr_rc_nor0:$ptrreg, ptr_rc_idx:$offreg);
   let OperandType = "OPERAND_MEMORY";
 }
 def memrix : Operand<iPTR> {   // memri where the imm is 4-aligned.
   let PrintMethod = "printMemRegImm";
   let MIOperandInfo = (ops dispRIX:$imm, ptr_rc_nor0:$reg);
-  let EncoderMethod = "getMemRIXEncoding";
-  let DecoderMethod = "decodeMemRIXOperands";
   let OperandType = "OPERAND_MEMORY";
 }
 def memrihash : Operand<iPTR> {
   // memrihash 8-aligned for ROP Protection Instructions.
   let PrintMethod = "printMemRegImmHash";
   let MIOperandInfo = (ops dispRIHash:$imm, ptr_rc_nor0:$reg);
-  let EncoderMethod = "getMemRIHashEncoding";
-  let DecoderMethod = "decodeMemRIHashOperands";
   let OperandType = "OPERAND_MEMORY";
 }
 def memrix16 : Operand<iPTR> { // memri, imm is 16-aligned, 12-bit, Inst{16:27}
   let PrintMethod = "printMemRegImm";
   let MIOperandInfo = (ops dispRIX16:$imm, ptr_rc_nor0:$reg);
-  let EncoderMethod = "getMemRIX16Encoding";
-  let DecoderMethod = "decodeMemRIX16Operands";
   let OperandType = "OPERAND_MEMORY";
 }
 def spe8dis : Operand<iPTR> {   // SPE displacement where the imm is 8-aligned.
   let PrintMethod = "printMemRegImm";
   let MIOperandInfo = (ops dispSPE8:$imm, ptr_rc_nor0:$reg);
-  let EncoderMethod = "getSPE8DisEncoding";
-  let DecoderMethod = "decodeSPE8Operands";
   let OperandType = "OPERAND_MEMORY";
 }
 def spe4dis : Operand<iPTR> {   // SPE displacement where the imm is 4-aligned.
   let PrintMethod = "printMemRegImm";
   let MIOperandInfo = (ops dispSPE4:$imm, ptr_rc_nor0:$reg);
-  let EncoderMethod = "getSPE4DisEncoding";
-  let DecoderMethod = "decodeSPE4Operands";
   let OperandType = "OPERAND_MEMORY";
 }
 def spe2dis : Operand<iPTR> {   // SPE displacement where the imm is 2-aligned.
   let PrintMethod = "printMemRegImm";
   let MIOperandInfo = (ops dispSPE2:$imm, ptr_rc_nor0:$reg);
-  let EncoderMethod = "getSPE2DisEncoding";
-  let DecoderMethod = "decodeSPE2Operands";
   let OperandType = "OPERAND_MEMORY";
 }
 
 // A single-register address. This is used with the SjLj
 // pseudo-instructions which translates to LD/LWZ.  These instructions requires
 // G8RC_NOX0 registers.
 def memr : Operand<iPTR> {
   let MIOperandInfo = (ops ptr_rc_nor0:$ptrreg);