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Differential D137575

[AMDGPU][MC] Disable SGPRs as src operands of VOP3 VINTRP instructions
ClosedPublic

Authored by dp on Nov 7 2022, 10:45 AM.

Details

Reviewers
foad
Joe_Nash
rampitec
Commits
rG05baf681a3c2: [AMDGPU][MC] Disable SGPRs as src operands of VOP3 VINTRP instructions
Summary

See this bug.

Diff Detail

Event Timeline

dp created this revision.Nov 7 2022, 10:45 AM
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Herald added subscribers: kosarev, kerbowa, hiraditya and 6 others. · View Herald Transcript
dp requested review of this revision.Nov 7 2022, 10:45 AM
Herald added a project: Restricted Project. · View Herald TranscriptNov 7 2022, 10:45 AM
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Harbormaster completed remote builds in B196539: Diff 473744.Nov 7 2022, 1:02 PM
Joe_Nash accepted this revision.Nov 10 2022, 7:07 AM

LGTM

This revision is now accepted and ready to land.Nov 10 2022, 7:07 AM
This revision was landed with ongoing or failed builds.Nov 11 2022, 2:21 AM
Closed by commit rG05baf681a3c2: [AMDGPU][MC] Disable SGPRs as src operands of VOP3 VINTRP instructions (authored by dp). · Explain Why
This revision was automatically updated to reflect the committed changes.
dp added a commit: rG05baf681a3c2: [AMDGPU][MC] Disable SGPRs as src operands of VOP3 VINTRP instructions.

Revision Contents

PathSize
llvm/
lib/
Target/
AMDGPU/
4 lines
test/
MC/
AMDGPU/
45 lines

Diff 474700

llvm/lib/Target/AMDGPU/VOP3Instructions.td

Show First 20 Lines • Show All 53 Lines • ▼ Show 20 Lines
class VOP3Interp<string OpName, VOPProfile P, list<dag> pattern = []> : class VOP3Interp<string OpName, VOPProfile P, list<dag> pattern = []> :
VOP3_Pseudo<OpName, P, pattern> { VOP3_Pseudo<OpName, P, pattern> {
let AsmMatchConverter = "cvtVOP3Interp"; let AsmMatchConverter = "cvtVOP3Interp";
let mayRaiseFPException = 0; let mayRaiseFPException = 0;
} }
def VOP3_INTERP : VOPProfile<[f32, f32, i32, untyped]> { def VOP3_INTERP : VOPProfile<[f32, f32, i32, untyped]> {
let Src0Mod = FPVRegInputMods;
let Ins64 = (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0, let Ins64 = (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0,
Attr:$attr, AttrChan:$attrchan, Attr:$attr, AttrChan:$attrchan,
clampmod0:$clamp, omod0:$omod); clampmod0:$clamp, omod0:$omod);
let Asm64 = "$vdst, $src0_modifiers, $attr$attrchan$clamp$omod"; let Asm64 = "$vdst, $src0_modifiers, $attr$attrchan$clamp$omod";
} }
def VOP3_INTERP_MOV : VOPProfile<[f32, i32, i32, untyped]> { def VOP3_INTERP_MOV : VOPProfile<[f32, i32, i32, untyped]> {
Show All 33 Lines dag ret = !if(HasSrc2,
); );
} }
class VOP3_INTERP16 <list<ValueType> ArgVT> : VOPProfile<ArgVT> { class VOP3_INTERP16 <list<ValueType> ArgVT> : VOPProfile<ArgVT> {
let HasOMod = !ne(DstVT.Value, f16.Value); let HasOMod = !ne(DstVT.Value, f16.Value);
let HasHigh = 1; let HasHigh = 1;
let Src0Mod = FPVRegInputMods;
let Src2Mod = FPVRegInputMods;
let Outs64 = (outs DstRC.RegClass:$vdst); let Outs64 = (outs DstRC.RegClass:$vdst);
let Ins64 = getInterp16Ins<HasSrc2, HasOMod, Src0Mod, Src2Mod>.ret; let Ins64 = getInterp16Ins<HasSrc2, HasOMod, Src0Mod, Src2Mod>.ret;
let Asm64 = getInterp16Asm<HasSrc2, HasOMod>.ret; let Asm64 = getInterp16Asm<HasSrc2, HasOMod>.ret;
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// VOP3 Instructions // VOP3 Instructions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
▲ Show 20 Lines • Show All 1,312 Lines • Show Last 20 Lines

llvm/test/MC/AMDGPU/vintrp-e64-err.s

  • This file was added.
// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga %s 2>&1 | FileCheck %s --implicit-check-not=error:
// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 %s 2>&1 | FileCheck %s --implicit-check-not=error:
// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 %s 2>&1 | FileCheck %s --implicit-check-not=error:
v_interp_p1_f32_e64 v5, 0.5, attr0.w
// CHECK: error: invalid operand for instruction
v_interp_p1_f32_e64 v5, s1, attr0.w
// CHECK: error: invalid operand for instruction
v_interp_p1ll_f16 v5, 0.5, attr0.w
// CHECK: error: invalid operand for instruction
v_interp_p1ll_f16 v5, s1, attr0.w
// CHECK: error: invalid operand for instruction
v_interp_p1lv_f16 v5, 0.5, attr0.w, v3
// CHECK: error: invalid operand for instruction
v_interp_p1lv_f16 v5, s1, attr0.w, v3
// CHECK: error: invalid operand for instruction
v_interp_p1lv_f16 v5, v1, attr31.w, 0.5
// CHECK: error: invalid operand for instruction
v_interp_p1lv_f16 v5, v1, attr31.w, s1
// CHECK: error: invalid operand for instruction
v_interp_p2_f16 v5, 0.5, attr0.w, v3
// CHECK: error: invalid operand for instruction
v_interp_p2_f16 v5, s1, attr0.w, v3
// CHECK: error: invalid operand for instruction
v_interp_p2_f16 v5, v1, attr1.w, 0.5
// CHECK: error: invalid operand for instruction
v_interp_p2_f16 v5, v1, attr1.w, s1
// CHECK: error: invalid operand for instruction
v_interp_p2_f32_e64 v5, 0.5, attr31.w
// CHECK: error: invalid operand for instruction
v_interp_p2_f32_e64 v5, s1, attr31.w
// CHECK: error: invalid operand for instruction