[LangRef][LoongArch] Update inline asm constraint code and operand modifier

[XiaodongLoong]

Summary

According to:
https://reviews.llvm.org/D134157
https://reviews.llvm.org/D136841
https://reviews.llvm.org/D136835

[SixWeining]

LGTM but I'm not sure if we should add/wait reviewers relevant to doc changes.

[xen0n]

In D137528#3911304, @SixWeining wrote:

LGTM but I'm not sure if we should add/wait reviewers relevant to doc changes.

I think so.

And I believe some of the recently added constraints are missing, such as J. They should be synced here as well.

[XiaodongLoong]

Add 'J' constraint code.

[XiaodongLoong]

As shown in the patch https://github.com/llvm/llvm-project/commit/ee3aef93b73646ef98f0241498d807a4fb68b78c, I think we can add other constraint code or operand modifier in other patches.
The reviewers who accepted the patch above concentrate on RISCV backend. Maybe, we can commit this patch directly.

llvm/docs/LangRef.rst

 - ``h``: A high GPR register (``r0-r7``).
 - ``w``: A 32, 64, or 128-bit floating-point/SIMD register in the ranges
   ``s0-s31``, ``d0-d31``, or ``q0-q15``, respectively.
 - ``t``: A 32, 64, or 128-bit floating-point/SIMD register in the ranges
   ``s0-s31``, ``d0-d15``, or ``q0-q7``, respectively.
 - ``x``: A 32, 64, or 128-bit floating-point/SIMD register in the ranges
   ``s0-s15``, ``d0-d7``, or ``q0-q3``, respectively.
 
-
 Hexagon:
 
 - ``o``, ``v``: A memory address operand, treated the same as constraint ``m``,
   at the moment.
 - ``r``: A 32 or 64-bit register.
 
+LoongArch:
+
+- ``f``: A floating-point register (if available).
+- ``k``: A memory operand whose address is formed by a base register and
+  (optionally scaled) index register.
+- ``l``: A signed 16-bit constant.
+- ``m``: A memory operand whose address is formed by a base register and
+  offset that is suitable for use in instructions with the same addressing
+  mode as st.w and ld.w.
+- ``I``: A signed 12-bit constant (for arithmetic instructions).
+- ``J``: An immediate integer zero.
+- ``K``: An unsigned 12-bit constant (for logic instructions).
+- ``ZB``: An address that is held in a general-purpose register. The offset
+  is zero.
+- ``ZC``: A memory operand whose address is formed by a base register and
+  offset that is suitable for use in instructions with the same addressing
+  mode as ll.w and sc.w.
+
 MSP430:
 
 - ``r``: An 8 or 16-bit register.
 
 MIPS:
 
 - ``I``: An immediate signed 16-bit integer.
 - ``J``: An immediate integer zero.
- ``L``: Print the second register of a two-register operand. Requires that it
   has been allocated consecutively to the first.
 
   .. FIXME: why is it restricted to consecutive ones? And there's
      nothing that ensures that happens, is there?
 
 - ``I``: Print the letter 'i' if the operand is an integer constant, otherwise
   nothing. Used to print 'addi' vs 'add' instructions.
 
+LoongArch:
+
+- ``z``: Print $zero register if operand is zero, otherwise print it normally.
+
 MSP430:
 
 No additional modifiers.
 
 MIPS:
 
 - ``X``: Print an immediate integer as hexadecimal
 - ``x``: Print the low 16 bits of an immediate integer as hexadecimal.