[Clang][LoongArch] Support inline asm constraint 'J'

[SixWeining]

Summary

'J' is defined in GCC [1] but not documented [2] while Linux [3] has
already used it in LoongArch port.

[1]: https://github.com/gcc-mirror/gcc/blob/master/gcc/config/loongarch/constraints.md#L61
[2]: https://gcc.gnu.org/onlinedocs/gccint/Machine-Constraints.html
[3]: https://github.com/torvalds/linux/blob/master/arch/loongarch/include/asm/cmpxchg.h#L19

[SixWeining]

Add missing comment.

clang/lib/Basic/Targets/LoongArch.cpp

bool LoongArchTargetInfo::validateAsmConstraint(
   case 'l':
     // A signed 16-bit constant.
     Info.setRequiresImmediate(-32768, 32767);
     return true;
   case 'I':
     // A signed 12-bit constant (for arithmetic instructions).
     Info.setRequiresImmediate(-2048, 2047);
     return true;
+  case 'J':
+    // Integer zero.
+    Info.setRequiresImmediate(0);
+    return true;
   case 'K':
     // An unsigned 12-bit constant (for logic instructions).
     Info.setRequiresImmediate(0, 4095);
     return true;
   case 'Z':
     // ZB: An address that is held in a general-purpose register. The offset is
     //     zero.
     // ZC: A memory operand whose address is formed by a base register

clang/test/CodeGen/LoongArch/inline-asm-constraints.c

 void test_I(void) {
 // CHECK-LABEL: define{{.*}} void @test_I()
 // CHECK: call void asm sideeffect "", "I"(i32 2047)
   asm volatile ("" :: "I"(2047));
 // CHECK: call void asm sideeffect "", "I"(i32 -2048)
   asm volatile ("" :: "I"(-2048));
 }
 
+void test_J(void) {
+// CHECK-LABEL: define{{.*}} void @test_J()
+// CHECK: call void asm sideeffect "", "J"(i32 0)
+  asm volatile ("" :: "J"(0));
+}
+
 void test_K(void) {
 // CHECK-LABEL: define{{.*}} void @test_K()
 // CHECK: call void asm sideeffect "", "K"(i32 4095)
   asm volatile ("" :: "K"(4095));
 // CHECK: call void asm sideeffect "", "K"(i32 0)
   asm volatile ("" :: "K"(0));
 }
 

llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp

LoongArchTargetLowering::getConstraintType(StringRef Constraint) const {
   // 'f':  A floating-point register (if available).
   // 'k':  A memory operand whose address is formed by a base register and
   //       (optionally scaled) index register.
   // 'l':  A signed 16-bit constant.
   // 'm':  A memory operand whose address is formed by a base register and
   //       offset that is suitable for use in instructions with the same
   //       addressing mode as st.w and ld.w.
   // 'I':  A signed 12-bit constant (for arithmetic instructions).
+  // 'J':  Integer zero.
   // 'K':  An unsigned 12-bit constant (for logic instructions).
   // "ZB": An address that is held in a general-purpose register. The offset is
   //       zero.
   // "ZC": A memory operand whose address is formed by a base register and
   //       offset that is suitable for use in instructions with the same
   //       addressing mode as ll.w and sc.w.
   if (Constraint.size() == 1) {
     switch (Constraint[0]) {
     default:
       break;
     case 'f':
       return C_RegisterClass;
     case 'l':
     case 'I':
+    case 'J':
     case 'K':
       return C_Immediate;
     case 'k':
       return C_Memory;
     }
   }
 
   if (Constraint == "ZC" || Constraint == "ZB")
case 'I':
       // Validate & create a 12-bit signed immediate operand.
       if (auto *C = dyn_cast<ConstantSDNode>(Op)) {
         uint64_t CVal = C->getSExtValue();
         if (isInt<12>(CVal))
           Ops.push_back(
               DAG.getTargetConstant(CVal, SDLoc(Op), Subtarget.getGRLenVT()));
       }
       return;
+    case 'J':
+      // Validate & create an integer zero operand.
+      if (auto *C = dyn_cast<ConstantSDNode>(Op))
+        if (C->getZExtValue() == 0)
+          Ops.push_back(
+              DAG.getTargetConstant(0, SDLoc(Op), Subtarget.getGRLenVT()));
+      return;
     case 'K':
       // Validate & create a 12-bit unsigned immediate operand.
       if (auto *C = dyn_cast<ConstantSDNode>(Op)) {
         uint64_t CVal = C->getZExtValue();
         if (isUInt<12>(CVal))
           Ops.push_back(
               DAG.getTargetConstant(CVal, SDLoc(Op), Subtarget.getGRLenVT()));
       }
       return;
     default:
       break;
     }
   }
   TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
 }

llvm/test/CodeGen/LoongArch/inline-asm-constraint-error.ll

 define void @constraint_I() {
 ; CHECK: error: value out of range for constraint 'I'
   tail call void asm sideeffect "addi.w $$a0, $$a0, $0", "I"(i32 2048)
 ; CHECK: error: value out of range for constraint 'I'
   tail call void asm sideeffect "addi.w $$a0, $$a0, $0", "I"(i32 -2049)
   ret void
 }
 
+define void @constraint_J() {
+; CHECK: error: value out of range for constraint 'J'
+  tail call void asm sideeffect "addi.w $$a0, $$a0, $$0", "J"(i32 1)
+  ret void
+}
+
 define void @constraint_K() {
 ; CHECK: error: value out of range for constraint 'K'
   tail call void asm sideeffect "andi.w $$a0, $$a0, $0", "K"(i32 4096)
 ; CHECK: error: value out of range for constraint 'K'
   tail call void asm sideeffect "andi.w $$a0, $$a0, $0", "K"(i32 -1)
   ret void
 }
 

llvm/test/CodeGen/LoongArch/inline-asm-constraint.ll

 ; CHECK-NEXT:    addi.w $a0, $a0, -2048
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:    ret
   tail call void asm sideeffect "addi.w $$a0, $$a0, $0", "I"(i32 2047)
   tail call void asm sideeffect "addi.w $$a0, $$a0, $0", "I"(i32 -2048)
   ret void
 }
 
+define void @constraint_J() nounwind {
+; CHECK-LABEL: constraint_J:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    addi.w $a0, $a0, 0
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    ret
+  tail call void asm sideeffect "addi.w $$a0, $$a0, $0", "J"(i32 0)
+  ret void
+}
+
 define void @constraint_K() nounwind {
 ; CHECK-LABEL: constraint_K:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    andi $a0, $a0, 4095
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    andi $a0, $a0, 0