[AArch64]Combine BFXIL to ORR with right shift for ISD::OR instruction selection

[mingmingl]

Summary

• This extends the existing helper function 'isWorthFoldingIntoOrrWithLeftShift' into 'isWorthFoldingIntoOrrWithShift', and encode right-shift imm (the encoding of left-shift imm is no-op).

[dmgreen]

LGTM

[mingmingl]

thanks! run a post-approval clang-format and going to submit this.

[mingmingl]

run a post-approval 'clang-format'

llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp

static bool tryBitfieldInsertOpFromOrAndImm(SDNode *N, SelectionDAG *CurDAG) {
   SDValue Ops[] = {And.getOperand(0), SDValue(MOVI, 0),
                    CurDAG->getTargetConstant(ImmR, DL, VT),
                    CurDAG->getTargetConstant(ImmS, DL, VT)};
   unsigned Opc = (VT == MVT::i32) ? AArch64::BFMWri : AArch64::BFMXri;
   CurDAG->SelectNodeTo(N, Opc, VT, Ops);
   return true;
 }
 
-static bool isWorthFoldingIntoOrrWithLeftShift(SDValue Dst,
-                                               SelectionDAG *CurDAG,
-                                               SDValue &LeftShiftedOperand,
-                                               uint64_t &LeftShiftAmount) {
-  // Avoid folding Dst into ORR-with-left-shift if Dst has other uses than ORR.
+static bool isWorthFoldingIntoOrrWithShift(SDValue Dst, SelectionDAG *CurDAG,
+                                           SDValue &ShiftedOperand,
+                                           uint64_t &ShiftAmount) {
+  // Avoid folding Dst into ORR-with-shift if Dst has other uses than ORR.
   if (!Dst.hasOneUse())
     return false;
 
   EVT VT = Dst.getValueType();
   assert((VT == MVT::i32 || VT == MVT::i64) &&
          "Caller should guarantee that VT is one of i32 or i64");
   const unsigned SizeInBits = VT.getSizeInBits();
 
if (isOpcWithIntImmediate(DstOp0.getNode(), ISD::SRL, SrlImm)) {
         unsigned UBFMOpc =
             (VT == MVT::i32) ? AArch64::UBFMWri : AArch64::UBFMXri;
         SDNode *UBFMNode = CurDAG->getMachineNode(
             UBFMOpc, DL, VT, DstOp0.getOperand(0),
             CurDAG->getTargetConstant(SrlImm + NumTrailingZeroInShiftedMask, DL,
                                       VT),
             CurDAG->getTargetConstant(
                 SrlImm + NumTrailingZeroInShiftedMask + MaskWidth - 1, DL, VT));
-        LeftShiftedOperand = SDValue(UBFMNode, 0);
-        LeftShiftAmount = NumTrailingZeroInShiftedMask;
+        ShiftedOperand = SDValue(UBFMNode, 0);
+        ShiftAmount = NumTrailingZeroInShiftedMask;
         return true;
       }
     }
-  } else if (isOpcWithIntImmediate(Dst.getNode(), ISD::SHL, ShlImm)) {
-    LeftShiftedOperand = Dst.getOperand(0);
-    LeftShiftAmount = ShlImm;
+    return false;
+  }
+
+  if (isOpcWithIntImmediate(Dst.getNode(), ISD::SHL, ShlImm)) {
+    ShiftedOperand = Dst.getOperand(0);
+    ShiftAmount = ShlImm;
+    return true;
+  }
+
+  uint64_t SrlImm;
+  if (isOpcWithIntImmediate(Dst.getNode(), ISD::SRL, SrlImm)) {
+    ShiftedOperand = Dst.getOperand(0);
+    ShiftAmount = AArch64_AM::getShifterImm(AArch64_AM::LSR, SrlImm);
     return true;
   }
-  // FIXME: Extend the implementation to optimize if Dst is an SRL node.
   return false;
 }
 
-static bool tryOrrWithLeftShift(SDNode *N, SDValue OrOpd0, SDValue OrOpd1,
-                                SDValue Src, SDValue Dst, SelectionDAG *CurDAG,
-                                const bool BiggerPattern) {
+static bool tryOrrWithShift(SDNode *N, SDValue OrOpd0, SDValue OrOpd1,
   EVT VT = N->getValueType(0);
   assert((VT == MVT::i32 || VT == MVT::i64) &&
          "Expect result type to be i32 or i64 since N is combinable to BFM");
   SDLoc DL(N);
 
   // Bail out if BFM simplifies away one node in BFM Dst.
   if (OrOpd1 != Dst)
     return false;
 
   // For "BFM Rd, Rn, #immr, #imms", it's known that BFM simplifies away fewer
   // nodes from Rn (or inserts additional shift node) if BiggerPattern is true.
   if (BiggerPattern) {
     uint64_t SrcAndImm;
     if (isOpcWithIntImmediate(OrOpd0.getNode(), ISD::AND, SrcAndImm) &&
         isMask_64(SrcAndImm) && OrOpd0.getOperand(0) == Src) {
       // OrOpd0 = AND Src, #Mask
       // So BFM simplifies away one AND node from Src and doesn't simplify away
       // nodes from Dst. If ORR with left-shifted operand also simplifies away
       // one node (from Rd), ORR is better since it has higher throughput and
       // smaller latency than BFM on many AArch64 processors (and for the rest
       // ORR is at least as good as BFM).
-      SDValue LeftShiftedOperand;
-      uint64_t LeftShiftAmount;
-      if (isWorthFoldingIntoOrrWithLeftShift(Dst, CurDAG, LeftShiftedOperand,
-                                             LeftShiftAmount)) {
+      SDValue ShiftedOperand;
+      uint64_t ShiftAmount;
+      if (isWorthFoldingIntoOrrWithShift(Dst, CurDAG, ShiftedOperand,
+                                         ShiftAmount)) {
         unsigned OrrOpc = (VT == MVT::i32) ? AArch64::ORRWrs : AArch64::ORRXrs;
-        SDValue Ops[] = {OrOpd0, LeftShiftedOperand,
-                         CurDAG->getTargetConstant(LeftShiftAmount, DL, VT)};
+        SDValue Ops[] = {OrOpd0, ShiftedOperand,
+                         CurDAG->getTargetConstant(ShiftAmount, DL, VT)};
         CurDAG->SelectNodeTo(N, OrrOpc, VT, Ops);
         return true;
       }
     }
     return false;
   }
 
   assert((!BiggerPattern) && "BiggerPattern should be handled above");
 
   uint64_t ShlImm;
-  // FIXME: Extend the implementation if OrOpd0 is an SRL node.
   if (isOpcWithIntImmediate(OrOpd0.getNode(), ISD::SHL, ShlImm) &&
       OrOpd0.getOperand(0) == Src && OrOpd0.hasOneUse()) {
     unsigned OrrOpc = (VT == MVT::i32) ? AArch64::ORRWrs : AArch64::ORRXrs;
     SDValue Ops[] = {Dst, Src, CurDAG->getTargetConstant(ShlImm, DL, VT)};
     CurDAG->SelectNodeTo(N, OrrOpc, VT, Ops);
     return true;
   }
 
if (isOpcWithIntImmediate(OrOpd1, ISD::AND, Imm) &&
       // In that case, we can eliminate the AND
       Dst = OrOpd1->getOperand(0);
     else
       // Maybe the AND has been removed by simplify-demanded-bits
       // or is useful because it discards more bits
       Dst = OrOpd1Val;
 
     // Before selecting ISD::OR node to AArch64::BFM, see if an AArch64::ORR
-    // with left-shifted operand is more efficient.
-    // FIXME: Extend this to compare AArch64::BFM and AArch64::ORR with
-    // right-shifted operand as well.
-    if (tryOrrWithLeftShift(N, OrOpd0Val, OrOpd1Val, Src, Dst, CurDAG,
-                            BiggerPattern))
+    // with shifted operand is more efficient.
+    if (tryOrrWithShift(N, OrOpd0Val, OrOpd1Val, Src, Dst, CurDAG,
       return true;
 
     // both parts match
     SDLoc DL(N);
     SDValue Ops[] = {Dst, Src, CurDAG->getTargetConstant(ImmR, DL, VT),
                      CurDAG->getTargetConstant(ImmS, DL, VT)};
     unsigned Opc = (VT == MVT::i32) ? AArch64::BFMWri : AArch64::BFMXri;
     CurDAG->SelectNodeTo(N, Opc, VT, Ops);

llvm/test/CodeGen/AArch64/fcopysign.ll

 ; CHECK-NEXT:    adrp x8, val_fp128
 ; CHECK-NEXT:    ldr q0, [x8, :lo12:val_fp128]
 ; CHECK-NEXT:    adrp x8, val_float
 ; CHECK-NEXT:    str q0, [sp, #-16]!
 ; CHECK-NEXT:    .cfi_def_cfa_offset 16
 ; CHECK-NEXT:    ldr w8, [x8, :lo12:val_float]
 ; CHECK-NEXT:    ldrb w9, [sp, #15]
 ; CHECK-NEXT:    and w8, w8, #0x80000000
-; CHECK-NEXT:    lsr w8, w8, #24
-; CHECK-NEXT:    bfxil w8, w9, #0, #7
+; CHECK-NEXT:    and w9, w9, #0x7f
+; CHECK-NEXT:    orr w8, w9, w8, lsr #24
 ; CHECK-NEXT:    strb w8, [sp, #15]
 ; CHECK-NEXT:    ldr q0, [sp], #16
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-NONEON-LABEL: copysign1:
 ; CHECK-NONEON:       // %bb.0: // %entry
 ; CHECK-NONEON-NEXT:    adrp x8, val_fp128
 ; CHECK-NONEON-NEXT:    ldr q0, [x8, :lo12:val_fp128]
 ; CHECK-NONEON-NEXT:    adrp x8, val_float
 ; CHECK-NONEON-NEXT:    str q0, [sp, #-16]!
 ; CHECK-NONEON-NEXT:    .cfi_def_cfa_offset 16
 ; CHECK-NONEON-NEXT:    ldr w8, [x8, :lo12:val_float]
 ; CHECK-NONEON-NEXT:    ldrb w9, [sp, #15]
 ; CHECK-NONEON-NEXT:    and w8, w8, #0x80000000
-; CHECK-NONEON-NEXT:    lsr w8, w8, #24
-; CHECK-NONEON-NEXT:    bfxil w8, w9, #0, #7
+; CHECK-NONEON-NEXT:    and w9, w9, #0x7f
+; CHECK-NONEON-NEXT:    orr w8, w9, w8, lsr #24
 ; CHECK-NONEON-NEXT:    strb w8, [sp, #15]
 ; CHECK-NONEON-NEXT:    ldr q0, [sp], #16
 ; CHECK-NONEON-NEXT:    ret
 entry:
   %v0 = load fp128, fp128* @val_fp128, align 16
   %v1 = load float, float* @val_float, align 4
   %conv = fpext float %v1 to fp128
   %call = tail call fp128 @llvm.copysign.f128(fp128 %v0, fp128 %conv)