[AMDGPU][MC][GFX11][NFC] Correct VINTERP src operands

[dp]

Summary

VINTERP src operands must be VGPRs, but assembler accepts SGPRs as well.

[Joe_Nash]

llvm/lib/Target/AMDGPU/VINTERPInstructions.td

67

I think setting the src operand type to VGPR_32 here is slightly wrong. The comment in SIRegisterInfo.td says use VRegSrc for operands that take only VGPRs and have enum{9} (are 9 bits in the encoding). The encoding for VINTERP has 9 bit fields. Functionally, it does not appear to make a difference.

[dp]

Revert unnecessary (and incorrect) operand type changes as Joe suggested.

[Joe_Nash]

LGTM

llvm/lib/Target/AMDGPU/VINTERPInstructions.td

class VINTERP_Real <VOP_Pseudo ps, int EncodingFamily> :
   VOP3_Real <ps, EncodingFamily> {
   let VINTERP = 1;
 }
 
 def VOP3_VINTERP_F32 : VOPProfile<[f32, f32, f32, f32]> {
   let HasOpSel = 0;
   let HasModifiers = 1;
 
+  let Src0Mod = FPVRegInputMods;
+  let Src1Mod = FPVRegInputMods;
+  let Src2Mod = FPVRegInputMods;
+
   let Outs64 = (outs VGPR_32:$vdst);
-  let Ins64 = (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0,
-                   Src1Mod:$src1_modifiers, VRegSrc_32:$src1,
-                   Src2Mod:$src2_modifiers, VRegSrc_32:$src2,
+  let Ins64 = (ins Src0Mod:$src0_modifiers, VGPR_32:$src0,
+                   Src1Mod:$src1_modifiers, VGPR_32:$src1,
+                   Src2Mod:$src2_modifiers, VGPR_32:$src2,
                    clampmod:$clamp,
                    wait_exp:$waitexp);
 
   let Asm64 = " $vdst, $src0_modifiers, $src1_modifiers, $src2_modifiers$clamp$waitexp";
 }
 
 class VOP3_VINTERP_F16 <list<ValueType> ArgVT> : VOPProfile<ArgVT> {
   let HasOpSel = 1;
   let HasModifiers = 1;
 
+  let Src0Mod = FPVRegInputMods;
+  let Src1Mod = FPVRegInputMods;
+  let Src2Mod = FPVRegInputMods;
+
   let Outs64 = (outs VGPR_32:$vdst);
-  let Ins64 = (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0,
-                   Src1Mod:$src1_modifiers, VRegSrc_32:$src1,
-                   Src2Mod:$src2_modifiers, VRegSrc_32:$src2,
+  let Ins64 = (ins Src0Mod:$src0_modifiers, VGPR_32:$src0,
+                   Src1Mod:$src1_modifiers, VGPR_32:$src1,
+                   Src2Mod:$src2_modifiers, VGPR_32:$src2,
                    clampmod:$clamp, op_sel0:$op_sel,
                    wait_exp:$waitexp);
 
   let Asm64 = " $vdst, $src0_modifiers, $src1_modifiers, $src2_modifiers$clamp$op_sel$waitexp";
 }
 
 //===----------------------------------------------------------------------===//
 // VINTERP Pseudo Instructions

llvm/test/MC/AMDGPU/gfx11_asm_vinterp_errs.s

+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 %s 2>&1 | FileCheck %s -check-prefix=GFX11-ERR --implicit-check-not=error: --strict-whitespace
+
+//===----------------------------------------------------------------------===//
+// VINTERP src operands must be VGPRs.
+// Check that other operand kinds are rejected by assembler.
+//===----------------------------------------------------------------------===//
+
+v_interp_p10_f32 v0, s1, v2, v3
+// GFX11-ERR: error: invalid operand for instruction
+
+v_interp_p10_f32 v0, v1, s2, v3
+// GFX11-ERR: error: invalid operand for instruction
+
+v_interp_p10_f32 v0, v1, v2, s3
+// GFX11-ERR: error: invalid operand for instruction
+
+v_interp_p2_f32 v0, 1, v2, v3
+// GFX11-ERR: error: invalid operand for instruction
+
+v_interp_p2_f32 v0, v1, 2, v3
+// GFX11-ERR: error: invalid operand for instruction
+
+v_interp_p2_f32 v0, v1, v2, 3
+// GFX11-ERR: error: invalid operand for instruction
+
+v_interp_p10_f16_f32 v0, s1, v2, v3
+// GFX11-ERR: error: invalid operand for instruction
+
+v_interp_p10_f16_f32 v0, v1, s2, v3
+// GFX11-ERR: error: invalid operand for instruction
+
+v_interp_p10_f16_f32 v0, v1, v2, s3
+// GFX11-ERR: error: invalid operand for instruction
+
+v_interp_p2_f16_f32 v0, 1, v2, v3
+// GFX11-ERR: error: invalid operand for instruction
+
+v_interp_p2_f16_f32 v0, v1, 2, v3
+// GFX11-ERR: error: invalid operand for instruction
+
+v_interp_p2_f16_f32 v0, v1, v2, 3
+// GFX11-ERR: error: invalid operand for instruction