[LLDB] Optimize lldb build time and memory consumption.

[Emmmer]

Summary

After land D136362, we found that:

On Loongarch, g++ is killed by the OOM-killer due to using too many resources, while clang++ is not.

I suspect the cause is that g++ tries to instantiate these generic lambdas inside std::visit(), which consumes N^2 the size memory when there's nested-std::visit()

It could cause a potential build error since the RISCVInst contains more and more Insts. (It means N will increase.)

So I tried to overload operator== to replace use std::visit(), here are my codes and results.

[seehearfeel]

Thank you for your patch.
It seems there is a new problem with this patch.

You can test it on x86_64 like this:
https://reviews.llvm.org/D136362#3895385

[DavidSpickett]

Please mention the tools version in the commit somewhere "memory consumption when using gcc 13". If one of you could file a bug at https://gcc.gnu.org/bugzilla/, then you can reference that also.

13 is not released yet so there is a chance to get it fixed before now, if that doesn't happen, having the release number in the commit will explain why things are done the way they are.

[seehearfeel]

c++: fatal error: Killed signal terminated program cc1plus due to out of memory
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107483

@SixWeining, @xry111, @xen0n
please take a look if you are intrested.

[xen0n]

Thanks for the heads-up @seehearfeel!

For now I believe it's more beneficial to fix the problem in gcc-13. Not only because it's shown to be a memory usage regression from gcc-12 by @seehearfeel in the GCC bug, but also fixing it there benefits more projects than LLVM/LLDB alone.

Let's wait for resolution of the gcc bug then revisit this; the refactoring here may prove useful independent of the gcc bug worked around here.

lldb/source/Plugins/Instruction/RISCV/RISCVInstructions.h

 struct Rs {
   uint32_t rs;
   llvm::Optional<uint64_t> Read(EmulateInstructionRISCV &emulator);
   llvm::Optional<int32_t> ReadI32(EmulateInstructionRISCV &emulator);
   llvm::Optional<int64_t> ReadI64(EmulateInstructionRISCV &emulator);
   llvm::Optional<uint32_t> ReadU32(EmulateInstructionRISCV &emulator);
 };
 
+#define DERIVE_EQ(NAME)                                                        \
+  bool operator==(const NAME &r) const {                                       \
+    return std::memcmp(this, &r, sizeof(NAME)) == 0;                           \
+  }
+
 #define I_TYPE_INST(NAME)                                                      \
   struct NAME {                                                                \
     Rd rd;                                                                     \
     Rs rs1;                                                                    \
     uint32_t imm;                                                              \
+    DERIVE_EQ(NAME);                                                           \
   }
 #define S_TYPE_INST(NAME)                                                      \
   struct NAME {                                                                \
     Rs rs1;                                                                    \
     Rs rs2;                                                                    \
     uint32_t imm;                                                              \
+    DERIVE_EQ(NAME);                                                           \
   }
 #define U_TYPE_INST(NAME)                                                      \
   struct NAME {                                                                \
     Rd rd;                                                                     \
     uint32_t imm;                                                              \
+    DERIVE_EQ(NAME);                                                           \
   }
 /// The memory layout are the same in our code.
 #define J_TYPE_INST(NAME) U_TYPE_INST(NAME)
 #define R_TYPE_INST(NAME)                                                      \
   struct NAME {                                                                \
     Rd rd;                                                                     \
     Rs rs1;                                                                    \
     Rs rs2;                                                                    \
+    DERIVE_EQ(NAME);                                                           \
   }
 #define R_SHAMT_TYPE_INST(NAME)                                                \
   struct NAME {                                                                \
     Rd rd;                                                                     \
     Rs rs1;                                                                    \
     uint32_t shamt;                                                            \
+    DERIVE_EQ(NAME);                                                           \
   }
 #define R_RS1_TYPE_INST(NAME)                                                  \
   struct NAME {                                                                \
     Rd rd;                                                                     \
     Rs rs1;                                                                    \
+    DERIVE_EQ(NAME);                                                           \
   }
 /// The `inst` fields are used for debugging.
 #define INVALID_INST(NAME)                                                     \
   struct NAME {                                                                \
     uint32_t inst;                                                             \
+    DERIVE_EQ(NAME);                                                           \
   }
 
 // RV32I instructions (The base integer ISA)
 struct B {
   Rs rs1;
   Rs rs2;
   uint32_t imm;
   uint32_t funct3;
+  DERIVE_EQ(B);
 };
 U_TYPE_INST(LUI);
 U_TYPE_INST(AUIPC);
 J_TYPE_INST(JAL);
 I_TYPE_INST(JALR);
 I_TYPE_INST(LB);
 I_TYPE_INST(LH);
 I_TYPE_INST(LW);
struct DecodeResult {
   bool is_rvc;
   InstrPattern pattern;
 };
 
 constexpr uint32_t DecodeRD(uint32_t inst) { return (inst & 0xF80) >> 7; }
 constexpr uint32_t DecodeRS1(uint32_t inst) { return (inst & 0xF8000) >> 15; }
 constexpr uint32_t DecodeRS2(uint32_t inst) { return (inst & 0x1F00000) >> 20; }
 
+#undef R_TYPE_INST
+#undef R_SHAMT_TYPE_INST
+#undef R_RS1_TYPE_INST
+#undef I_TYPE_INST
+#undef S_TYPE_INST
+#undef B_TYPE_INST
+#undef U_TYPE_INST
+#undef J_TYPE_INST
+#undef INVALID_INST
+#undef DERIVE_EQ
+
 } // namespace lldb_private
 #endif // LLDB_SOURCE_PLUGINS_INSTRUCTION_RISCV_RISCVINSTRUCTION_H

lldb/unittests/Instruction/RISCV/TestRISCVEmulator.cpp

TEST_F(RISCVEmulatorTester, TestAtomicSequence) {
   ASSERT_EQ(this->gpr.gpr[0], uint64_t(16));
 }
 
 struct TestDecode {
   uint32_t inst;
   RISCVInst inst_type;
 };
 
-bool compareInst(const RISCVInst &lhs, const RISCVInst &rhs) {
-  if (lhs.index() != rhs.index())
-    return false;
-  return std::visit(
-      [&](auto &&L) {
-        return std::visit(
-            [&](auto &&R) {
-              // guaranteed by
-              // 1. lhs.index() == rhs.index()
-              // (they are the same instruction type)
-              // 2. all instruction representations are plain data objects
-              // consisting of primitive types.
-              return std::memcmp(&L, &R, sizeof(L)) == 0;
-            },
-            rhs);
-      },
-      lhs);
-}
-
 TEST_F(RISCVEmulatorTester, TestCDecode) {
   std::vector<TestDecode> tests = {
       {0x0000, INVALID{0x0000}},
       {0x0010, RESERVED{0x0010}},
       // ADDI4SPN here, decode as ADDI
       {0x0024, ADDI{Rd{9}, Rs{2}, 8}},
       {0x4488, LW{Rd{10}, Rs{9}, 8}},
       {0x6488, LD{Rd{10}, Rs{9}, 8}},
std::vector<TestDecode> tests = {
       {0xC006, SW{Rs{2}, Rs{1}, 0}},
       // C.SDSP here, decoded as SD
       {0xE006, SD{Rs{2}, Rs{1}, 0}},
   };
 
   for (auto i : tests) {
     auto decode = this->Decode(i.inst);
     ASSERT_TRUE(decode.has_value());
-    ASSERT_TRUE(compareInst(decode->decoded, i.inst_type));
+    ASSERT_EQ(decode->decoded, i.inst_type);
   }
 }
 
 // GEN_BRANCH_TEST(opcode, imm1, imm2, imm3):
 // It should branch for instruction `opcode imm1, imm2`
 // It should do nothing for instruction `opcode imm1, imm3`
 GEN_BRANCH_TEST(BEQ, 1, 1, 0)
 GEN_BRANCH_TEST(BNE, 1, 0, 1)