[AMDGPU] Fix GCNDownwardRPTracker::advanceBeforeNext at the end of MBB

[vpykhtin]

Summary

The problem with GCNDownwardRPTracker::advanceBeforeNext is that it doesn't allow to get register pressure
after the last instruction in a MBB.

However when we track RP through the boundary of a MBB we need the state that is after the last instruction
of the MBB and before the first instruction of the successor MBB. Currently we stop traking RP in the state
'at' the last instruction of the MBB which is incorrect.

This patch fixes 27 lit tests with EXPENSIVE_CHECKS enabled.

[vpykhtin]

updated comment

[rampitec]

llvm/lib/Target/AMDGPU/GCNRegPressure.cpp

329

I think you still need to skip debug instructions.

[vpykhtin]

restored bool return value for advanceBeforeNext, added debug instr skipping

[vpykhtin]

llvm/lib/Target/AMDGPU/GCNRegPressure.cpp

329

NextMI is already skipped debug instructions either in reset or advanceToNext. I just using slot index before NextMI to skip debug instruction during liveness test.

[arsenm]

llvm/lib/Target/AMDGPU/GCNRegPressure.cpp

329

Maybe add an assert it's not a debug instruction

[vpykhtin]

added assert !isDebugInstr

[vpykhtin]

rebase

llvm/lib/Target/AMDGPU/GCNRegPressure.h

public:
 
   MachineBasicBlock::const_iterator getNext() const { return NextMI; }
 
   // Reset tracker to the point before the MI
   // filling live regs upon this point using LIS.
   // Returns false if block is empty except debug values.
   bool reset(const MachineInstr &MI, const LiveRegSet *LiveRegs = nullptr);
 
-  // Move to the state right before the next MI. Returns false if reached
-  // end of the block.
+  // Move to the state right before the next MI or after the end of MBB.
+  // Returns false if reached end of the block.
   bool advanceBeforeNext();
 
   // Move to the state at the MI, advanceBeforeNext has to be called first.
   void advanceToNext();
 
   // Move to the state at the next MI. Returns false if reached end of block.
   bool advance();
 

llvm/lib/Target/AMDGPU/GCNRegPressure.cpp

bool GCNDownwardRPTracker::reset(const MachineInstr &MI,
   if (NextMI == MBBEnd)
     return false;
   GCNRPTracker::reset(*NextMI, LiveRegsCopy, false);
   return true;
 }
 
 bool GCNDownwardRPTracker::advanceBeforeNext() {
   assert(MRI && "call reset first");
+  if (!LastTrackedMI)
+    return NextMI == MBBEnd;
 
-  NextMI = skipDebugInstructionsForward(NextMI, MBBEnd);
-  if (NextMI == MBBEnd)
-    return false;
+  assert(NextMI == MBBEnd || !NextMI->isDebugInstr());
 
-  SlotIndex SI = LIS.getInstructionIndex(*NextMI).getBaseIndex();
+  SlotIndex SI = NextMI == MBBEnd
+                     ? LIS.getInstructionIndex(*LastTrackedMI).getDeadSlot()
+                     : LIS.getInstructionIndex(*NextMI).getBaseIndex();
   assert(SI.isValid());
 
   // Remove dead registers or mask bits.
   for (auto &It : LiveRegs) {
     const LiveInterval &LI = LIS.getInterval(It.first);
     if (LI.hasSubRanges()) {
       for (const auto &S : LI.subranges()) {
         if (!S.liveAt(SI)) {
           auto PrevMask = It.second;
           It.second &= ~S.LaneMask;
           CurPressure.inc(It.first, PrevMask, It.second, *MRI);
         }
       }
     } else if (!LI.liveAt(SI)) {
       auto PrevMask = It.second;
       It.second = LaneBitmask::getNone();
       CurPressure.inc(It.first, PrevMask, It.second, *MRI);
     }
     if (It.second.none())
       LiveRegs.erase(It.first);
   }
 
   MaxPressure = max(MaxPressure, CurPressure);
 
-  return true;
+  LastTrackedMI = nullptr;
+
+  return NextMI == MBBEnd;
 }
 
 void GCNDownwardRPTracker::advanceToNext() {
   LastTrackedMI = &*NextMI++;
   NextMI = skipDebugInstructionsForward(NextMI, MBBEnd);
 
   // Add new registers or mask bits.
   for (const auto &MO : LastTrackedMI->operands()) {
     if (!MO.isReg() || !MO.isDef())
       continue;
     Register Reg = MO.getReg();
     if (!Reg.isVirtual())
       continue;
     auto &LiveMask = LiveRegs[Reg];
     auto PrevMask = LiveMask;
     LiveMask |= getDefRegMask(MO, *MRI);
     CurPressure.inc(Reg, PrevMask, LiveMask, *MRI);
   }
 
   MaxPressure = max(MaxPressure, CurPressure);
 }
 
 bool GCNDownwardRPTracker::advance() {
-  // If we have just called reset live set is actual.
-  if ((NextMI == MBBEnd) || (LastTrackedMI && !advanceBeforeNext()))
+  if (NextMI == MBBEnd)
     return false;
+  advanceBeforeNext();
   advanceToNext();
   return true;
 }
 
 bool GCNDownwardRPTracker::advance(MachineBasicBlock::const_iterator End) {
   while (NextMI != End)
     if (!advance()) return false;
   return true;

llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp

for (;;) {
     RPTracker.advanceBeforeNext();
   }
 
   if (OnlySucc) {
     if (I != MBB->end()) {
       RPTracker.advanceToNext();
       RPTracker.advance(MBB->end());
     }
-    RPTracker.reset(*OnlySucc->begin(), &RPTracker.getLiveRegs());
     RPTracker.advanceBeforeNext();
     MBBLiveIns[OnlySucc] = RPTracker.moveLiveRegs();
   }
 }
 
 DenseMap<MachineInstr *, GCNRPTracker::LiveRegSet>
 GCNScheduleDAGMILive::getBBLiveInMap() const {
   assert(!Regions.empty());