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[InstCombine] improve demanded bits for Sub operand 0
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Authored by spatel on Oct 26 2022, 1:49 PM.

Details

Summary

This is copying the code that was added for add with D130075. (That patch removed a fallthrough in the cases, but we can probably still share at least some code again as a follow-up cleanup, but I didn't want to risk it here.)

The reasoning is similar to the carry propagation for add: if we don't demand low bits of the subtraction and the subtrahend (aka RHS or operand 1) is known zero in those low bits, then there can't be any borrowing required from the higher bits of operand 0, so they don't matter.

Also, the no-wrap flags can be propagated (and I think that should be true for add too).

Here's an attempt to prove that in Alive2:
https://alive2.llvm.org/ce/z/xqh7Pa
(can add nsw or nuw from src and tgt, and it should still pass)

Diff Detail

Event Timeline

spatel created this revision.Oct 26 2022, 1:49 PM
Herald added a project: Restricted Project. · View Herald TranscriptOct 26 2022, 1:49 PM
spatel requested review of this revision.Oct 26 2022, 1:49 PM
Herald added a project: Restricted Project. · View Herald TranscriptOct 26 2022, 1:49 PM
bcl5980 accepted this revision.Oct 26 2022, 8:45 PM

LGTM

This revision is now accepted and ready to land.Oct 26 2022, 8:45 PM
foad accepted this revision.Oct 27 2022, 1:08 AM
This revision was landed with ongoing or failed builds.Oct 27 2022, 7:19 AM
This revision was automatically updated to reflect the committed changes.