[GlobalISel] Add Predicates to GICombineRule

[Pierre-vh]

Summary

Small QoL change to allow Predicates to be used in GICombineRule.
Currently only one combine in the AMDGPU backend makes use of it.

The implementation is pretty simple to get started but of course we can expand this later on and optimize predicate checking better if needed.

[Pierre-vh]

Add missing test

[Pierre-vh]

Oops, newline at EOF.

[Pierre-vh]

Fix predicate

[dsanders]

LGTM, ideally as you say this ought to be part of the partitioning so the generated can code efficiently get to the relevant leaves more directly but this is fine for now

[foad]

In D136681#3883037, @dsanders wrote:

LGTM, ideally as you say this ought to be part of the partitioning so the generated can code efficiently get to the relevant leaves more directly but this is fine for now

Maybe leave a TODO in the code to that effect?

llvm/include/llvm/Target/GlobalISel/Combine.td

class GICombineRule<dag defs, dag match, dag apply> : GICombine {
   /// Defines the things which must be true for the pattern to match
   /// See GIMatchKind for details.
   dag Match = match;
 
   /// Defines the things which happen after the decision is made to apply a
   /// combine rule.
   /// See GIApplyKind for details.
   dag Apply = apply;
+
+  /// Defines the predicates that are checked before the match function
+  /// is called. Targets can use this to, for instance, check Subtarget
+  /// features.
+  list<Predicate> Predicates = [];
 }
 
 /// The operator at the root of a GICombineRule.Defs dag.
 def defs;
 
 /// All arguments of the defs operator must be subclasses of GIDefKind or
 /// sub-dags whose operator is GIDefKindWithArgs.
 class GIDefKind;

llvm/lib/Target/AMDGPU/AMDGPU.td

 def NotHasTrue16BitInsts : Predicate<"!Subtarget->hasTrue16BitInsts()">;
 
 def HasVOP3PInsts : Predicate<"Subtarget->hasVOP3PInsts()">,
   AssemblerPredicate<(all_of FeatureVOP3P)>;
 
 def HasMinMaxDenormModes : Predicate<"Subtarget->supportsMinMaxDenormModes()">;
 def NotHasMinMaxDenormModes : Predicate<"!Subtarget->supportsMinMaxDenormModes()">;
 
+def HasFminFmaxLegacy : Predicate<"Subtarget->hasFminFmaxLegacy()">;
+
 def HasSDWA : Predicate<"Subtarget->hasSDWA()">,
   AssemblerPredicate<(all_of FeatureSDWA, FeatureVolcanicIslands)>;
 
 def HasSDWA9 :
   Predicate<"Subtarget->hasSDWA()">,
   AssemblerPredicate<(all_of FeatureGCN3Encoding, FeatureGFX9Insts,FeatureSDWA)>;
 
 def HasSDWA10 :

llvm/lib/Target/AMDGPU/AMDGPUCombine.td

 //=- AMDGPUCombine.td - Define AMDGPU Combine Rules ----------*- tablegen -*-=//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 include "llvm/Target/GlobalISel/Combine.td"
 
 // TODO: This really belongs after legalization after scalarization.
-// TODO: GICombineRules should accept subtarget predicates
 
 def fmin_fmax_legacy_matchdata : GIDefMatchData<"AMDGPUPostLegalizerCombinerHelper::FMinFMaxLegacyInfo">;
 
+let Predicates = [HasFminFmaxLegacy] in
 def fcmp_select_to_fmin_fmax_legacy : GICombineRule<
   (defs root:$select, fmin_fmax_legacy_matchdata:$matchinfo),
   (match (wip_match_opcode G_SELECT):$select,
          [{ return PostLegalizerHelper.matchFMinFMaxLegacy(*${select}, ${matchinfo}); }]),
   (apply [{ PostLegalizerHelper.applySelectFCmpToFMinToFMaxLegacy(*${select}, ${matchinfo}); }])>;
 
 
 def uchar_to_float : GICombineRule<

llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp

public:
   void applyCvtF32UByteN(MachineInstr &MI,
                          const CvtF32UByteMatchInfo &MatchInfo);
 
   bool matchRemoveFcanonicalize(MachineInstr &MI, Register &Reg);
 };
 
 bool AMDGPUPostLegalizerCombinerHelper::matchFMinFMaxLegacy(
     MachineInstr &MI, FMinFMaxLegacyInfo &Info) {
-  // FIXME: Combines should have subtarget predicates, and we shouldn't need
-  // this here.
-  if (!MF.getSubtarget<GCNSubtarget>().hasFminFmaxLegacy())
-    return false;
-
   // FIXME: Type predicate on pattern
   if (MRI.getType(MI.getOperand(0).getReg()) != LLT::scalar(32))
     return false;
 
   Register Cond = MI.getOperand(1).getReg();
   if (!MRI.hasOneNonDBGUse(Cond) ||
       !mi_match(Cond, MRI,
                 m_GFCmp(m_Pred(Info.Pred), m_Reg(Info.LHS), m_Reg(Info.RHS))))
bool AMDGPUPostLegalizerCombinerHelper::matchRemoveFcanonicalize(
   return TLI->isCanonicalized(Reg, MF);
 }
 
 class AMDGPUPostLegalizerCombinerHelperState {
 protected:
   AMDGPUCombinerHelper &Helper;
   AMDGPUPostLegalizerCombinerHelper &PostLegalizerHelper;
 
+  // Note: pointer is necessary because Target Predicates use
+  //   "Subtarget->"
+  const GCNSubtarget *Subtarget;
+
 public:
   AMDGPUPostLegalizerCombinerHelperState(
       AMDGPUCombinerHelper &Helper,
-      AMDGPUPostLegalizerCombinerHelper &PostLegalizerHelper)
-      : Helper(Helper), PostLegalizerHelper(PostLegalizerHelper) {}
+      AMDGPUPostLegalizerCombinerHelper &PostLegalizerHelper,
+      const GCNSubtarget &Subtarget)
+      : Helper(Helper), PostLegalizerHelper(PostLegalizerHelper),
+        Subtarget(&Subtarget) {}
 };
 
 #define AMDGPUPOSTLEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_DEPS
 #include "AMDGPUGenPostLegalizeGICombiner.inc"
 #undef AMDGPUPOSTLEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_DEPS
 
 namespace {
 #define AMDGPUPOSTLEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_H
 #include "AMDGPUGenPostLegalizeGICombiner.inc"
 #undef AMDGPUPOSTLEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_H
 
 class AMDGPUPostLegalizerCombinerInfo final : public CombinerInfo {
   GISelKnownBits *KB;
   MachineDominatorTree *MDT;
+  const GCNSubtarget &Subtarget;
 
 public:
   AMDGPUGenPostLegalizerCombinerHelperRuleConfig GeneratedRuleCfg;
 
-  AMDGPUPostLegalizerCombinerInfo(bool EnableOpt, bool OptSize, bool MinSize,
+  AMDGPUPostLegalizerCombinerInfo(const GCNSubtarget &Subtarget, bool EnableOpt,
+                                  bool OptSize, bool MinSize,
                                   const AMDGPULegalizerInfo *LI,
                                   GISelKnownBits *KB, MachineDominatorTree *MDT)
       : CombinerInfo(/*AllowIllegalOps*/ false, /*ShouldLegalizeIllegal*/ true,
                      /*LegalizerInfo*/ LI, EnableOpt, OptSize, MinSize),
-        KB(KB), MDT(MDT) {
+        KB(KB), MDT(MDT), Subtarget(Subtarget) {
     if (!GeneratedRuleCfg.parseCommandLineOption())
       report_fatal_error("Invalid rule identifier");
   }
 
   bool combine(GISelChangeObserver &Observer, MachineInstr &MI,
                MachineIRBuilder &B) const override;
 };
 
 bool AMDGPUPostLegalizerCombinerInfo::combine(GISelChangeObserver &Observer,
                                               MachineInstr &MI,
                                               MachineIRBuilder &B) const {
   AMDGPUCombinerHelper Helper(Observer, B, /*IsPreLegalize*/ false, KB, MDT,
                               LInfo);
   AMDGPUPostLegalizerCombinerHelper PostLegalizerHelper(B, Helper);
-  AMDGPUGenPostLegalizerCombinerHelper Generated(GeneratedRuleCfg, Helper,
-                                                 PostLegalizerHelper);
+  AMDGPUGenPostLegalizerCombinerHelper Generated(
+      GeneratedRuleCfg, Helper, PostLegalizerHelper, Subtarget);
 
   if (Generated.tryCombineAll(Observer, MI, B))
     return true;
 
   switch (MI.getOpcode()) {
   case TargetOpcode::G_SHL:
   case TargetOpcode::G_LSHR:
   case TargetOpcode::G_ASHR:
bool AMDGPUPostLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) {
 
   const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
   const AMDGPULegalizerInfo *LI
     = static_cast<const AMDGPULegalizerInfo *>(ST.getLegalizerInfo());
 
   GISelKnownBits *KB = &getAnalysis<GISelKnownBitsAnalysis>().get(MF);
   MachineDominatorTree *MDT =
       IsOptNone ? nullptr : &getAnalysis<MachineDominatorTree>();
-  AMDGPUPostLegalizerCombinerInfo PCInfo(EnableOpt, F.hasOptSize(),
+  AMDGPUPostLegalizerCombinerInfo PCInfo(ST, EnableOpt, F.hasOptSize(),
                                          F.hasMinSize(), LI, KB, MDT);
   Combiner C(PCInfo, TPC);
   return C.combineMachineInstrs(MF, /*CSEInfo*/ nullptr);
 }
 
 char AMDGPUPostLegalizerCombiner::ID = 0;
 INITIALIZE_PASS_BEGIN(AMDGPUPostLegalizerCombiner, DEBUG_TYPE,
                       "Combine AMDGPU machine instrs after legalization",

llvm/test/TableGen/GICombinerEmitter/match-tree.td

 def ADD : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2), []>;
 def SUB : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2), []>;
 def MUL : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2), []>;
 def TRUNC : I<(outs GPR32:$dst), (ins GPR32:$src1), []>;
 def SEXT : I<(outs GPR32:$dst), (ins GPR32:$src1), []>;
 def ZEXT : I<(outs GPR32:$dst), (ins GPR32:$src1), []>;
 def ICMP : I<(outs GPR32:$dst), (ins GPR32:$tst, GPR32:$src1, GPR32:$src2), []>;
 
+def HasFoo : Predicate<"Subtarget->hasFoo()">;
+def HasAnswerToEverything : Predicate<"Subtarget->getAnswerToUniverse() == 42 && Subtarget->getAnswerToLife() == 42">;
+
 def Rule0 : GICombineRule<
   (defs root:$d),
   (match (MUL $t, $s1, $s2),
          (SUB $d, $t, $s3)),
   (apply [{ APPLY }])>;
 
 def Rule1 : GICombineRule<
   (defs root:$d),
(match (MUL $t, $s1, $s2),
          (ADD $d, $t, $s3), [{ A }]),
   (apply [{ APPLY }])>;
 
 def Rule4 : GICombineRule<
   (defs root:$d),
   (match (ADD $d, $s1, $s2)),
   (apply [{ APPLY }])>;
 
+let Predicates = [HasFoo] in
 def Rule5 : GICombineRule<
   (defs root:$d),
   (match (SUB $d, $s1, $s2)),
   (apply [{ APPLY }])>;
 
+let Predicates = [HasFoo, HasAnswerToEverything] in
 def Rule6 : GICombineRule<
   (defs root:$d),
   (match (SEXT $t, $s1),
          (TRUNC $d, $t)),
   (apply [{ APPLY }])>;
 
 def Rule7 : GICombineRule<
   (defs root:$d),

 // CODE-NEXT:) {
 // CODE-NEXT:            APPLY
 // CODE-NEXT:            return true;
 // CODE-NEXT:          }
 // CODE-NEXT:        }
 // CODE-NEXT:        llvm_unreachable("Combine rule elision was incorrect");
 // CODE-NEXT:        return false;
 // CODE-NEXT:     }
- 
 // Check that the other rule involving SUB (Rule5) is run otherwise.
 
 // CODE-NEXT:      if (Partition == 1 /* * or nullptr */) {
 // CODE-NEXT:        // Leaf name: Rule5
 // CODE-NEXT:        // Rule: Rule5
 // CODE-NEXT:        if (!RuleConfig->isRuleDisabled(5)) {
 // CODE-NEXT:          if (1
+// CODE-NEXT:               && (
+// CODE-NEXT:               // Predicate: HasFoo
+// CODE-NEXT:               Subtarget->hasFoo()
+// CODE-NEXT:               )
 // CODE-NEXT:) {
 // CODE-NEXT:            APPLY
 // CODE-NEXT:            return true;
 // CODE-NEXT:          }
 // CODE-NEXT:        }
 // CODE-NEXT:        llvm_unreachable("Combine rule elision was incorrect");
 // CODE-NEXT:        return false;
 // CODE-NEXT:      }
 // CODE-NEXT:    }
 
 // Check that Rule5 is run if operand 1 is not MUL.
 
 // CODE-NEXT:    if (Partition == 1 /* false */) {
 // CODE-NEXT:      // Leaf name: Rule5
 // CODE-NEXT:      // Rule: Rule5
 // CODE-NEXT:      if (!RuleConfig->isRuleDisabled(5)) {
 // CODE-NEXT:        if (1
-// CODE-NEXT:) {
+// CODE-NEXT:             && (
+// CODE-NEXT:             // Predicate: HasFoo
+// CODE-NEXT:             Subtarget->hasFoo()
+// CODE-NEXT:             )
+// CODE-NEXT:      ) {
 // CODE-NEXT:          APPLY
 // CODE-NEXT:          return true;
 // CODE-NEXT:        }
 // CODE-NEXT:      }
 // CODE-NEXT:      llvm_unreachable("Combine rule elision was incorrect");
 // CODE-NEXT:      return false;
 // CODE-NEXT:    }
 // CODE-NEXT:  }
 
+
+// Check multiple predicates are correctly emitted
+
+// CODE:      // Leaf name: Rule6
+// CODE-NEXT: // Rule: Rule6
+// CODE-NEXT: if (!RuleConfig->isRuleDisabled(6)) {
+// CODE-NEXT:   if (1
+// CODE-NEXT:       && (
+// CODE-NEXT:            // Predicate: HasFoo
+// CODE-NEXT:            Subtarget->hasFoo()
+// CODE-NEXT:          )
+// CODE-NEXT:       && (
+// CODE-NEXT:            // Predicate: HasAnswerToEverything
+// CODE-NEXT:            Subtarget->getAnswerToUniverse() == 42 && Subtarget->getAnswerToLife() == 42
+// CODE-NEXT:          )
+// CODE-NEXT:      ) {
+// CODE-NEXT:     APPLY
+// CODE-NEXT:     return true;
+// CODE-NEXT:   }
+// CODE-NEXT: }

llvm/utils/TableGen/GICombinerEmitter.cpp

for (const auto &Leaf : Tree.possible_leaves()) {
     if (Applyer->getOperatorAsDef(RuleDef.getLoc())->getName() !=
         "apply") {
       PrintError(RuleDef.getLoc(), "Expected 'apply' operator in Apply DAG");
       return;
     }
 
     OS << Indent << "  if (1\n";
 
+    // Emit code for C++ Predicates.
+    if (RuleDef.getValue("Predicates")) {
+      ListInit *Preds = RuleDef.getValueAsListInit("Predicates");
+      for (Init *I : Preds->getValues()) {
+        if (DefInit *Pred = dyn_cast<DefInit>(I)) {
+          Record *Def = Pred->getDef();
+          if (!Def->isSubClassOf("Predicate")) {
+            PrintError(Def->getLoc(), "Unknown 'Predicate' Type");
+            return;
+          }
+
+          StringRef CondString = Def->getValueAsString("CondString");
+          if (CondString.empty())
+            continue;
+
+          OS << Indent << "      && (\n"
+             << Indent << "           // Predicate: " << Def->getName() << "\n"
+             << Indent << "           " << CondString << "\n"
+             << Indent << "         )\n";
+        }
+      }
+    }
+
     // Attempt to emit code for any untested predicates left over. Note that
     // isFullyTested() will remain false even if we succeed here and therefore
     // combine rule elision will not be performed. This is because we do not
     // know if there's any connection between the predicates for each leaf and
     // therefore can't tell if one makes another unreachable. Ideally, the
     // partitioner(s) would be sufficiently complete to prevent us from having
     // untested predicates left over.
     for (const GIMatchDagPredicate *Predicate : Leaf.untested_predicates()) {
if (Rule->getMatchingFixupCode() &&
       OS << Indent << "      && [&]() {\n"
          << Indent << "      "
          << CodeExpander(Rule->getMatchingFixupCode()->getValue(), Expansions,
                          RuleDef.getLoc(), ShowExpansions)
          << "\n"
          << Indent << "      return true;\n"
          << Indent << "  }()";
     }
-    OS << ") {\n" << Indent << "   ";
+    OS << Indent << "     ) {\n" << Indent << "   ";
 
     if (const StringInit *Code = dyn_cast<StringInit>(Applyer->getArg(0))) {
       OS << CodeExpander(Code->getAsUnquotedString(), Expansions,
                          RuleDef.getLoc(), ShowExpansions)
          << "\n"
          << Indent << "    return true;\n"
          << Indent << "  }\n";
     } else {