This is an archive of the discontinued LLVM Phabricator instance.

[Verifier] Relieve intrinsics parameter alignment size constrain
ClosedPublic

Authored by LuoYuanke on Oct 20 2022, 3:10 AM.

Details

Summary

In D121898 we restrict parameter alignment size in IR since DAGISel
only have 4 bits to hold the alignment value. However intrinsics
won't be lowered to call instruction, so we can remove the constrain
for intrinsics.

Diff Detail

Event Timeline

LuoYuanke created this revision.Oct 20 2022, 3:10 AM
Herald added a project: Restricted Project. · View Herald TranscriptOct 20 2022, 3:10 AM
Herald added a subscriber: hiraditya. · View Herald Transcript
LuoYuanke requested review of this revision.Oct 20 2022, 3:10 AM
Herald added a project: Restricted Project. · View Herald TranscriptOct 20 2022, 3:10 AM
LuoYuanke added reviewers: pengfei, skan.

Thanks for the patch. Could it use a simpler intrinsic for the test? Maybe a llvm.fshr.v8192i32?

LuoYuanke updated this revision to Diff 469388.Oct 20 2022, 4:08 PM

Address @dmgreen's comments

skan added inline comments.Oct 20 2022, 6:47 PM
llvm/lib/IR/Verifier.cpp
3228–3230

Why do we need this check? Is there a LIT test for it?

LuoYuanke added inline comments.Oct 20 2022, 7:06 PM
llvm/lib/IR/Verifier.cpp
3228–3230

This is the original code, and I just move it above VerifyTypeAlign check. See the left line 3240 ~ 3245.

skan accepted this revision.Oct 20 2022, 11:28 PM

LGTM

This revision is now accepted and ready to land.Oct 20 2022, 11:28 PM
dmgreen accepted this revision.Oct 21 2022, 12:01 AM

Thanks for the update. LGTM.