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Differential D135719

[GlobalISel] Allow vectors in redundant or + add combines
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Authored by paquette on Oct 11 2022, 3:20 PM.

Details

Reviewers
aemerson
arsenm
mbrkusanin
Commits
rG0f1a51e17353: [GlobalISel] Allow vectors in redundant or + add combines
Summary

We support KnownBits for vectors, so we can enable these.

https://godbolt.org/z/r9a9W4Gj1

Diff Detail

Event Timeline

paquette created this revision.Oct 11 2022, 3:20 PM
Herald added a project: Restricted Project. · View Herald TranscriptOct 11 2022, 3:20 PM
Herald added subscribers: kosarev, kerbowa, hiraditya and 2 others. · View Herald Transcript
paquette requested review of this revision.Oct 11 2022, 3:20 PM
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arsenm accepted this revision.Oct 11 2022, 3:26 PM
This revision is now accepted and ready to land.Oct 11 2022, 3:26 PM
This revision was landed with ongoing or failed builds.Oct 11 2022, 3:31 PM
Closed by commit rG0f1a51e17353: [GlobalISel] Allow vectors in redundant or + add combines (authored by paquette). · Explain Why
This revision was automatically updated to reflect the committed changes.
paquette added a commit: rG0f1a51e17353: [GlobalISel] Allow vectors in redundant or + add combines.
Harbormaster completed remote builds in B191594: Diff 466940.Oct 11 2022, 4:07 PM

Revision Contents

PathSize
llvm/
lib/
CodeGen/
GlobalISel/
12 lines
test/
CodeGen/
AMDGPU/
GlobalISel/
60 lines
61 lines

Diff 466949

llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp

Show First 20 Lines • Show All 2,818 Lines • ▼ Show 20 Linesbool CombinerHelper::matchRedundantAnd(MachineInstr &MI,
// %and:_(s32) = G_AND %cmp, %one // %and:_(s32) = G_AND %cmp, %one
// //
// In this case, G_ICMP only produces a single bit, so x & 1 == x. // In this case, G_ICMP only produces a single bit, so x & 1 == x.
assert(MI.getOpcode() == TargetOpcode::G_AND); assert(MI.getOpcode() == TargetOpcode::G_AND);
if (!KB) if (!KB)
return false; return false;
Register AndDst = MI.getOperand(0).getReg(); Register AndDst = MI.getOperand(0).getReg();
LLT DstTy = MRI.getType(AndDst);
// FIXME: This should be removed once GISelKnownBits supports vectors.
if (DstTy.isVector())
return false;
Register LHS = MI.getOperand(1).getReg(); Register LHS = MI.getOperand(1).getReg();
Register RHS = MI.getOperand(2).getReg(); Register RHS = MI.getOperand(2).getReg();
KnownBits LHSBits = KB->getKnownBits(LHS); KnownBits LHSBits = KB->getKnownBits(LHS);
KnownBits RHSBits = KB->getKnownBits(RHS); KnownBits RHSBits = KB->getKnownBits(RHS);
// Check that x & Mask == x. // Check that x & Mask == x.
// x & 1 == x, always // x & 1 == x, always
// x & 0 == x, only if x is also 0 // x & 0 == x, only if x is also 0
Show All 24 Linesbool CombinerHelper::matchRedundantOr(MachineInstr &MI, Register &Replacement) {
// %res:_(sN) = G_OR %x, %y // %res:_(sN) = G_OR %x, %y
// //
// Eliminate the G_OR when it is known that x | y == x or x | y == y. // Eliminate the G_OR when it is known that x | y == x or x | y == y.
assert(MI.getOpcode() == TargetOpcode::G_OR); assert(MI.getOpcode() == TargetOpcode::G_OR);
if (!KB) if (!KB)
return false; return false;
Register OrDst = MI.getOperand(0).getReg(); Register OrDst = MI.getOperand(0).getReg();
LLT DstTy = MRI.getType(OrDst);
// FIXME: This should be removed once GISelKnownBits supports vectors.
if (DstTy.isVector())
return false;
Register LHS = MI.getOperand(1).getReg(); Register LHS = MI.getOperand(1).getReg();
Register RHS = MI.getOperand(2).getReg(); Register RHS = MI.getOperand(2).getReg();
KnownBits LHSBits = KB->getKnownBits(LHS); KnownBits LHSBits = KB->getKnownBits(LHS);
KnownBits RHSBits = KB->getKnownBits(RHS); KnownBits RHSBits = KB->getKnownBits(RHS);
// Check that x | Mask == x. // Check that x | Mask == x.
// x | 0 == x, always // x | 0 == x, always
// x | 1 == x, only if x is also 1 // x | 1 == x, only if x is also 1
▲ Show 20 Lines • Show All 3,218 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/combine-or-redundant.mir

Show First 20 Lines • Show All 152 Lines • ▼ Show 20 Lines bb.0:
%4:_(s32) = G_CONSTANT i32 4294901760 %4:_(s32) = G_CONSTANT i32 4294901760
%5:_(s32) = G_LSHR %0, %2(s32) %5:_(s32) = G_LSHR %0, %2(s32)
%6:_(s32) = G_XOR %5, %3(s32) %6:_(s32) = G_XOR %5, %3(s32)
%7:_(s32) = G_AND %1, %4(s32) %7:_(s32) = G_AND %1, %4(s32)
%8:_(s32) = G_OR %6, %7 %8:_(s32) = G_OR %6, %7
$sgpr0 = COPY %8(s32) $sgpr0 = COPY %8(s32)
SI_RETURN_TO_EPILOG implicit $sgpr0 SI_RETURN_TO_EPILOG implicit $sgpr0
... ...
---
name: vector_const_splat_const_splat
tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: vector_const_splat_const_splat
; CHECK: %mask:_(s16) = G_CONSTANT i16 255
; CHECK-NEXT: %c2:_(<2 x s16>) = G_BUILD_VECTOR %mask(s16), %mask(s16)
; CHECK-NEXT: $vgpr0 = COPY %c2(<2 x s16>)
; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0
%mask:_(s16) = G_CONSTANT i16 255
%fifteen:_(s16) = G_CONSTANT i16 15
%c1:_(<2 x s16>) = G_BUILD_VECTOR %fifteen, %fifteen
%c2:_(<2 x s16>) = G_BUILD_VECTOR %mask, %mask
%and:_(<2 x s16>) = G_OR %c1(<2 x s16>), %c2(<2 x s16>)
$vgpr0 = COPY %and(<2 x s16>)
SI_RETURN_TO_EPILOG implicit $vgpr0
...
---
name: vector_const_valid_not_splat
tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: vector_const_valid_not_splat
; CHECK: %mask:_(s16) = G_CONSTANT i16 255
; CHECK-NEXT: %c2:_(<2 x s16>) = G_BUILD_VECTOR %mask(s16), %mask(s16)
; CHECK-NEXT: $vgpr0 = COPY %c2(<2 x s16>)
; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0
%fifteen:_(s16) = G_CONSTANT i16 15
%sixteen:_(s16) = G_CONSTANT i16 16
%mask:_(s16) = G_CONSTANT i16 255
%c1:_(<2 x s16>) = G_BUILD_VECTOR %fifteen, %sixteen
%c2:_(<2 x s16>) = G_BUILD_VECTOR %mask, %mask
%and:_(<2 x s16>) = G_OR %c1(<2 x s16>), %c2(<2 x s16>)
$vgpr0 = COPY %and(<2 x s16>)
SI_RETURN_TO_EPILOG implicit $vgpr0
...
---
name: vector_dont_combine_const_too_wide
tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: vector_dont_combine_const_too_wide
; CHECK: %fifteen:_(s16) = G_CONSTANT i16 15
; CHECK-NEXT: %too_wide:_(s16) = G_CONSTANT i16 257
; CHECK-NEXT: %mask:_(s16) = G_CONSTANT i16 255
; CHECK-NEXT: %c1:_(<2 x s16>) = G_BUILD_VECTOR %fifteen(s16), %too_wide(s16)
; CHECK-NEXT: %c2:_(<2 x s16>) = G_BUILD_VECTOR %mask(s16), %mask(s16)
; CHECK-NEXT: %and:_(<2 x s16>) = G_OR %c1, %c2
; CHECK-NEXT: $vgpr0 = COPY %and(<2 x s16>)
; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0
%fifteen:_(s16) = G_CONSTANT i16 15
%too_wide:_(s16) = G_CONSTANT i16 257
%mask:_(s16) = G_CONSTANT i16 255
%c1:_(<2 x s16>) = G_BUILD_VECTOR %fifteen, %too_wide
%c2:_(<2 x s16>) = G_BUILD_VECTOR %mask, %mask
%and:_(<2 x s16>) = G_OR %c1(<2 x s16>), %c2(<2 x s16>)
$vgpr0 = COPY %and(<2 x s16>)
SI_RETURN_TO_EPILOG implicit $vgpr0
...

llvm/test/CodeGen/AMDGPU/GlobalISel/combine-redundant-and.mir

Show First 20 Lines • Show All 161 Lines • ▼ Show 20 Lines bb.0:
; Sext from the 4th bit -> 111 ... 1011 = -5 ; Sext from the 4th bit -> 111 ... 1011 = -5
%sext_inreg_11:_(s32) = G_SEXT_INREG %cst_11, 4 %sext_inreg_11:_(s32) = G_SEXT_INREG %cst_11, 4
%and:_(s32) = G_AND %cst_1(s32), %sext_inreg_11(s32) %and:_(s32) = G_AND %cst_1(s32), %sext_inreg_11(s32)
$sgpr0 = COPY %and(s32) $sgpr0 = COPY %and(s32)
SI_RETURN_TO_EPILOG implicit $sgpr0 SI_RETURN_TO_EPILOG implicit $sgpr0
... ...
---
name: vector_const_splat_const_splat
tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: vector_const_splat_const_splat
; CHECK: %fifteen:_(s16) = G_CONSTANT i16 15
; CHECK-NEXT: %c1:_(<2 x s16>) = G_BUILD_VECTOR %fifteen(s16), %fifteen(s16)
; CHECK-NEXT: $vgpr0 = COPY %c1(<2 x s16>)
; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0
%fifteen:_(s16) = G_CONSTANT i16 15
%mask:_(s16) = G_CONSTANT i16 255
%c1:_(<2 x s16>) = G_BUILD_VECTOR %fifteen, %fifteen
%c2:_(<2 x s16>) = G_BUILD_VECTOR %mask, %mask
%and:_(<2 x s16>) = G_AND %c1(<2 x s16>), %c2(<2 x s16>)
$vgpr0 = COPY %and(<2 x s16>)
SI_RETURN_TO_EPILOG implicit $vgpr0
...
---
name: vector_const_valid_not_splat
tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: vector_const_valid_not_splat
; CHECK: %fifteen:_(s16) = G_CONSTANT i16 15
; CHECK-NEXT: %sixteen:_(s16) = G_CONSTANT i16 16
; CHECK-NEXT: %c1:_(<2 x s16>) = G_BUILD_VECTOR %fifteen(s16), %sixteen(s16)
; CHECK-NEXT: $vgpr0 = COPY %c1(<2 x s16>)
; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0
%fifteen:_(s16) = G_CONSTANT i16 15
%sixteen:_(s16) = G_CONSTANT i16 16
%mask:_(s16) = G_CONSTANT i16 255
%c1:_(<2 x s16>) = G_BUILD_VECTOR %fifteen, %sixteen
%c2:_(<2 x s16>) = G_BUILD_VECTOR %mask, %mask
%and:_(<2 x s16>) = G_AND %c1(<2 x s16>), %c2(<2 x s16>)
$vgpr0 = COPY %and(<2 x s16>)
SI_RETURN_TO_EPILOG implicit $vgpr0
...
---
name: vector_dont_combine_const_too_wide
tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: vector_dont_combine_const_too_wide
; CHECK: %fifteen:_(s16) = G_CONSTANT i16 15
; CHECK-NEXT: %too_wide:_(s16) = G_CONSTANT i16 257
; CHECK-NEXT: %mask:_(s16) = G_CONSTANT i16 255
; CHECK-NEXT: %c1:_(<2 x s16>) = G_BUILD_VECTOR %fifteen(s16), %too_wide(s16)
; CHECK-NEXT: %c2:_(<2 x s16>) = G_BUILD_VECTOR %mask(s16), %mask(s16)
; CHECK-NEXT: %and:_(<2 x s16>) = G_AND %c1, %c2
; CHECK-NEXT: $vgpr0 = COPY %and(<2 x s16>)
; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0
%fifteen:_(s16) = G_CONSTANT i16 15
%too_wide:_(s16) = G_CONSTANT i16 257
%mask:_(s16) = G_CONSTANT i16 255
%c1:_(<2 x s16>) = G_BUILD_VECTOR %fifteen, %too_wide
%c2:_(<2 x s16>) = G_BUILD_VECTOR %mask, %mask
%and:_(<2 x s16>) = G_AND %c1(<2 x s16>), %c2(<2 x s16>)
$vgpr0 = COPY %and(<2 x s16>)
SI_RETURN_TO_EPILOG implicit $vgpr0
...