[GlobalISel] Combine things like (z = x <= 0 ? z = x : z = 0) -> x & (x >> bw-1)

[paquette]

Summary

If we have a signed comparison like this:

%cmp = icmp sge i32 %x, 0
%select = select i1 %cmp, i32 %x, i32 0
ret i32 %select

We can represent it using an and + a right shift.

On AArch64, this allows us to do the cmp + select in a single instruction.

This also works with signed less-than operators, but instead we compliment the
shift first.

Saves 0.12% code size on CTMark/lencod @ -Os for AArch64. Other minor code size
savings as well with no regressions.

https://godbolt.org/z/7E4vYWah6

[arsenm]

llvm/include/llvm/CodeGen/TargetLowering.h

724–731 ↗

(On Diff #466676)

Wouldn't the target just not add this combine if it didn't want it?

llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp

6087–6090

These assignments on the right aren't part of the pattern and confusing

6101

I guess this is complicated by this sub-variant, which would probably be uglier to split into a separate combine

llvm/test/CodeGen/AArch64/combine-select-to-and-shift.mir

264

Vector case? Even if it's not directly legal I would expect this to combine to the vector for later scalarization if needed

[HsiangKai]

llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp

6106

You can use the captured NeedsNot here.

[paquette]

• simplify comment
• use captured NeedsNot
• support vector case + add test

[aemerson]

llvm/include/llvm/CodeGen/TargetLowering.h

724–731 ↗

(On Diff #466676)

@paquette Echoing Matt's question: is this hook actually needed?

[paquette]

Split into two combines to avoid the hook. The "and-not" combine is now opt-in by the target.

[arsenm]

In D135633#3856846, @paquette wrote:

Split into two combines to avoid the hook. The "and-not" combine is now opt-in by the target.

If someone needed different behavior per type, it would still need a hook (or some other mechanism to parameterize combines by type)

[paquette]

In D135633#3856871, @arsenm wrote:

In D135633#3856846, @paquette wrote:

Split into two combines to avoid the hook. The "and-not" combine is now opt-in by the target.

If someone needed different behavior per type, it would still need a hook (or some other mechanism to parameterize combines by type)

Should I add the hook back in then?

llvm/include/llvm/CodeGen/TargetLowering.h

724–731 ↗

(On Diff #466676)

yeah I can drop it

[arsenm]

In D135633#3866585, @paquette wrote:

In D135633#3856871, @arsenm wrote:

In D135633#3856846, @paquette wrote:

Split into two combines to avoid the hook. The "and-not" combine is now opt-in by the target.

If someone needed different behavior per type, it would still need a hook (or some other mechanism to parameterize combines by type)

Should I add the hook back in then?

No, not without a real reason to. But some general type control would be helpful

[arsenm]

LGTM

[arsenm]

reverse ping

llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h

public:
   ///   (X + Y) == X -> Y == 0
   ///   (X - Y) == X -> Y == 0
   ///   (X ^ Y) == X -> Y == 0
   ///   (X + Y) != X -> Y != 0
   ///   (X - Y) != X -> Y != 0
   ///   (X ^ Y) != X -> Y != 0
   bool matchRedundantBinOpInEquality(MachineInstr &MI, BuildFnTy &MatchInfo);
 
+  /// Transform:
+  /// Given bw = bitwidth of the type:
+  ///   select (icmp slt x, 0), x, 0 --> x & (x >> bw-1)
+  ///   select (icmp sle x, 0), x, 0 --> x & (x >> bw-1)
+  bool matchSimplifySelectToAndShift(MachineInstr &MI, BuildFnTy &MatchInfo);
+  /// Transform:
+  /// Given bw = bitwidth of the type:
+  ///   select (icmp sgt x, 0), x, 0 --> x & ((~x) >> bw-1)
+  ///   select (icmp sge x, 0), x, 0 --> x & ((~x) >> bw-1)
+  /// \note Should only be used by targets which have a single-instruction
+  /// representation of and-not.
+  bool matchSimplifySelectToAndNotShift(MachineInstr &MI, BuildFnTy &MatchInfo);
+
 private:
   /// Given a non-indexed load or store instruction \p MI, find an offset that
   /// can be usefully and legally folded into it as a post-indexing operation.
   ///
   /// \returns true if a candidate is found.
   bool findPostIndexCandidate(MachineInstr &MI, Register &Addr, Register &Base,
                               Register &Offset);
 

llvm/include/llvm/Target/GlobalISel/Combine.td

def bitcast_bitcast_fold : GICombineRule<
   (apply [{ Helper.replaceSingleDefInstWithReg(*${op}, ${src0}.getReg()); }])>;
 
 def select_to_minmax: GICombineRule<
   (defs root:$root, build_fn_matchinfo:$info),
   (match (wip_match_opcode G_SELECT):$root,
          [{ return Helper.matchSimplifySelectToMinMax(*${root}, ${info}); }]),
   (apply [{ Helper.applyBuildFn(*${root}, ${info}); }])>;
 
+def select_to_and_shift: GICombineRule<
+  (defs root:$root, build_fn_matchinfo:$info),
+  (match (wip_match_opcode G_SELECT):$root,
+         [{ return Helper.matchSimplifySelectToAndShift(*${root}, ${info}); }]),
+  (apply [{ Helper.applyBuildFn(*${root}, ${info}); }])>;
+
+// Only add if target supports a single-instruction "and-not".
+def select_to_and_not_shift: GICombineRule<
+  (defs root:$root, build_fn_matchinfo:$info),
+  (match (wip_match_opcode G_SELECT):$root,
+         [{ return Helper.matchSimplifySelectToAndNotShift(*${root}, ${info}); }]),
+  (apply [{ Helper.applyBuildFn(*${root}, ${info}); }])>;
+
 // FIXME: These should use the custom predicate feature once it lands.
 def undef_combines : GICombineGroup<[undef_to_fp_zero, undef_to_int_zero,
                                      undef_to_negative_one,
                                      binop_left_undef_to_zero,
                                      binop_right_undef_to_undef,
                                      unary_undef_to_zero,
                                      propagate_undef_any_op,
                                      propagate_undef_all_ops,
def known_bits_simplifications : GICombineGroup<[
   zext_trunc_fold, icmp_to_true_false_known_bits, icmp_to_lhs_known_bits]>;
 
 def width_reduction_combines : GICombineGroup<[reduce_shl_of_extend,
                                                narrow_binop_feeding_and]>;
 
 def phi_combines : GICombineGroup<[extend_through_phis]>;
 
 def select_combines : GICombineGroup<[select_undef_cmp, select_constant_cmp,
-                                      select_to_logical]>;
+                                      select_to_logical, select_to_and_shift]>;
 
 def trivial_combines : GICombineGroup<[copy_prop, mul_to_shl, add_p2i_to_ptradd,
                                        mul_by_neg_one]>;
 
 def fma_combines : GICombineGroup<[combine_fadd_fmul_to_fmad_or_fma,
   combine_fadd_fpext_fmul_to_fmad_or_fma, combine_fadd_fma_fmul_to_fmad_or_fma,
   combine_fadd_fpext_fma_fmul_to_fmad_or_fma, combine_fsub_fmul_to_fmad_or_fma,
   combine_fsub_fneg_fmul_to_fmad_or_fma, combine_fsub_fpext_fmul_to_fmad_or_fma,

llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp

bool CombinerHelper::matchRedundantBinOpInEquality(MachineInstr &MI,
   }
   MatchInfo = [=](MachineIRBuilder &B) {
     auto Zero = B.buildConstant(MRI.getType(Y), 0);
     B.buildICmp(Pred, Dst, Y, Zero);
   };
   return CmpInst::isEquality(Pred) && Y.isValid();
 }
 
+bool CombinerHelper::matchSimplifySelectToAndShift(MachineInstr &MI,
+                                                   BuildFnTy &MatchInfo) {
+  assert(MI.getOpcode() == TargetOpcode::G_SELECT);
+  // Given bw = bitwidth of the type:
+  // select (icmp slt x, 0), x, 0 --> x & (x >> bw-1)
+  // select (icmp sle x, 0), x, 0 --> x & (x >> bw-1)
+  Register Dst = MI.getOperand(0).getReg();
+  CmpInst::Predicate Pred;
+  Register X1, X2;
+  if (!mi_match(Dst, MRI,
+                m_GISelect(m_c_GICmp(m_Pred(Pred), m_Reg(X1),
+                                     m_SpecificICstOrSplat(0)),
+                           m_Reg(X2), m_SpecificICstOrSplat(0))) ||
+      X1 != X2)
+    return false;
+  if (Pred != ICmpInst::ICMP_SLT && Pred != ICmpInst::ICMP_SLE)
+    return false;
+  LLT Ty = MRI.getType(Dst);
+  MatchInfo = [=](MachineIRBuilder &B) {
+    auto BW = B.buildConstant(Ty, Ty.getScalarSizeInBits() - 1);
+    auto Shift = B.buildAShr(Ty, X1, BW);
+    B.buildAnd(Dst, X1, Shift);
+  };
+  return true;
+}
+
+bool CombinerHelper::matchSimplifySelectToAndNotShift(MachineInstr &MI,
+                                                      BuildFnTy &MatchInfo) {
+  // This combine should only be used by targets which have a single-instruction
+  // representation of "and-not".
+  assert(MI.getOpcode() == TargetOpcode::G_SELECT);
+  // Given bw = bitwidth of the type:
+  // select (icmp sgt x, 0), x, 0 --> x & ((~x) >> bw-1)
+  // select (icmp sge x, 0), x, 0 --> x & ((~x) >> bw-1)
+  Register Dst = MI.getOperand(0).getReg();
+  CmpInst::Predicate Pred;
+  Register X1, X2;
+  if (!mi_match(Dst, MRI,
+                m_GISelect(m_c_GICmp(m_Pred(Pred), m_Reg(X1),
+                                     m_SpecificICstOrSplat(0)),
+                           m_Reg(X2), m_SpecificICstOrSplat(0))) ||
+      X1 != X2 || !ICmpInst::isSigned(Pred))
+    return false;
+  if (Pred != ICmpInst::ICMP_SGT && Pred != ICmpInst::ICMP_SGE)
+    return false;
+  LLT Ty = MRI.getType(Dst);
+  MatchInfo = [=](MachineIRBuilder &B) {
+    auto BW = B.buildConstant(Ty, Ty.getScalarSizeInBits() - 1);
+    auto Shift = B.buildAShr(Ty, X1, BW);
+    Shift = B.buildNot(Ty, Shift);
+    B.buildAnd(Dst, X1, Shift);
+  };
+  return true;
+}
+
 bool CombinerHelper::tryCombine(MachineInstr &MI) {
   if (tryCombineCopy(MI))
     return true;
   if (tryCombineExtendingLoads(MI))
     return true;
   if (tryCombineIndexedLoadStore(MI))
     return true;
   return false;
 }

llvm/lib/Target/AArch64/AArch64Combine.td

def fold_global_offset : GICombineRule<
   (defs root:$root, fold_global_offset_matchdata:$matchinfo),
   (match (wip_match_opcode G_GLOBAL_VALUE):$root,
           [{ return matchFoldGlobalOffset(*${root}, MRI, ${matchinfo}); }]),
   (apply [{  return applyFoldGlobalOffset(*${root}, MRI, B, Observer, ${matchinfo});}])
 >;
 
 def AArch64PreLegalizerCombinerHelper: GICombinerHelper<
   "AArch64GenPreLegalizerCombinerHelper", [all_combines,
+                                           select_to_and_not_shift,
                                            fconstant_to_constant,
                                            icmp_redundant_trunc,
                                            fold_global_offset]> {
   let DisableRuleOption = "aarch64prelegalizercombiner-disable-rule";
   let StateClass = "AArch64PreLegalizerCombinerHelperState";
   let AdditionalArguments = [];
 }
 
: GICombinerHelper<"AArch64GenPostLegalizerCombinerHelper",
                        [copy_prop, combines_for_extload,
                         sext_trunc_sextload, mutate_anyext_to_zext,
                         hoist_logic_op_with_same_opcode_hands,
                         redundant_and, xor_of_and_with_same_reg,
                         extractvecelt_pairwise_add, redundant_or,
                         mul_const, redundant_sext_inreg,
                         form_bitfield_extract, rotate_out_of_range,
                         icmp_to_true_false_known_bits, merge_unmerge,
-                        select_combines, fold_merge_to_zext,
-                        constant_fold, identity_combines,
+                        select_combines, select_to_and_not_shift,
+                        fold_merge_to_zext, constant_fold, identity_combines,
                         ptr_add_immed_chain, overlapping_and,
                         split_store_zero_128, undef_combines,
                         select_to_minmax]> {
   let DisableRuleOption = "aarch64postlegalizercombiner-disable-rule";
 }

llvm/test/CodeGen/AArch64/combine-select-to-and-shift.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -o - -mtriple=aarch64-unknown-unknown -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s | FileCheck %s
+
+# (z = x <= 0 ? z = x : z = 0) -> x & (x >> bw-1)
+# (z = x >= 0 ? z = x : z = 0) -> x & ((!x) >> bw-1)
+
+...
+---
+name:            sgt
+alignment:       4
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $w0
+    ; CHECK-LABEL: name: sgt
+    ; CHECK: liveins: $w0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: %x:_(s32) = COPY $w0
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
+    ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR %x, [[C]](s32)
+    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+    ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[ASHR]], [[C1]]
+    ; CHECK-NEXT: %select:_(s32) = G_AND %x, [[XOR]]
+    ; CHECK-NEXT: $w0 = COPY %select(s32)
+    ; CHECK-NEXT: RET_ReallyLR implicit $w0
+    %x:_(s32) = COPY $w0
+    %zero:_(s32) = G_CONSTANT i32 0
+    %cmp:_(s1) = G_ICMP intpred(sgt), %x(s32), %zero
+    %select:_(s32) = G_SELECT %cmp(s1), %x, %zero
+    $w0 = COPY %select(s32)
+    RET_ReallyLR implicit $w0
+...
+---
+name:            sgt_commuted
+alignment:       4
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $w0
+    ; CHECK-LABEL: name: sgt_commuted
+    ; CHECK: liveins: $w0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: %x:_(s32) = COPY $w0
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
+    ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR %x, [[C]](s32)
+    ; CHECK-NEXT: %select:_(s32) = G_AND %x, [[ASHR]]
+    ; CHECK-NEXT: $w0 = COPY %select(s32)
+    ; CHECK-NEXT: RET_ReallyLR implicit $w0
+    %x:_(s32) = COPY $w0
+    %zero:_(s32) = G_CONSTANT i32 0
+    %cmp:_(s1) = G_ICMP intpred(sgt), %zero(s32), %x
+    %select:_(s32) = G_SELECT %cmp(s1), %x, %zero
+    $w0 = COPY %select(s32)
+    RET_ReallyLR implicit $w0
+...
+---
+name:            sgt_vector
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $q0
+    ; CHECK-LABEL: name: sgt_vector
+    ; CHECK: liveins: $q0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: %x:_(<4 x s32>) = COPY $q0
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
+    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)
+    ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(<4 x s32>) = G_ASHR %x, [[BUILD_VECTOR]](<4 x s32>)
+    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+    ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C1]](s32), [[C1]](s32), [[C1]](s32), [[C1]](s32)
+    ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<4 x s32>) = G_XOR [[ASHR]], [[BUILD_VECTOR1]]
+    ; CHECK-NEXT: %select:_(<4 x s32>) = G_AND %x, [[XOR]]
+    ; CHECK-NEXT: $q0 = COPY %select(<4 x s32>)
+    ; CHECK-NEXT: RET_ReallyLR implicit $q0
+    %x:_(<4 x s32>) = COPY $q0
+    %zero:_(s32) = G_CONSTANT i32 0
+    %bv_zero:_(<4 x s32>) = G_BUILD_VECTOR %zero(s32), %zero(s32), %zero(s32), %zero(s32)
+    %cmp:_(<4 x s1>) = G_ICMP intpred(sgt), %x(<4 x s32>), %bv_zero
+    %select:_(<4 x s32>) = G_SELECT %cmp(<4 x s1>), %x, %bv_zero
+    $q0 = COPY %select(<4 x s32>)
+    RET_ReallyLR implicit $q0
+...
+---
+name:            sge
+alignment:       4
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $w0
+    ; CHECK-LABEL: name: sge
+    ; CHECK: liveins: $w0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: %x:_(s32) = COPY $w0
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
+    ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR %x, [[C]](s32)
+    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+    ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[ASHR]], [[C1]]
+    ; CHECK-NEXT: %select:_(s32) = G_AND %x, [[XOR]]
+    ; CHECK-NEXT: $w0 = COPY %select(s32)
+    ; CHECK-NEXT: RET_ReallyLR implicit $w0
+    %x:_(s32) = COPY $w0
+    %zero:_(s32) = G_CONSTANT i32 0
+    %cmp:_(s1) = G_ICMP intpred(sge), %x(s32), %zero
+    %select:_(s32) = G_SELECT %cmp(s1), %x, %zero
+    $w0 = COPY %select(s32)
+    RET_ReallyLR implicit $w0
+...
+---
+name:            sge_commuted
+alignment:       4
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $w0
+    ; CHECK-LABEL: name: sge_commuted
+    ; CHECK: liveins: $w0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: %x:_(s32) = COPY $w0
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
+    ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR %x, [[C]](s32)
+    ; CHECK-NEXT: %select:_(s32) = G_AND %x, [[ASHR]]
+    ; CHECK-NEXT: $w0 = COPY %select(s32)
+    ; CHECK-NEXT: RET_ReallyLR implicit $w0
+    %x:_(s32) = COPY $w0
+    %zero:_(s32) = G_CONSTANT i32 0
+    %cmp:_(s1) = G_ICMP intpred(sge), %zero(s32), %x
+    %select:_(s32) = G_SELECT %cmp(s1), %x, %zero
+    $w0 = COPY %select(s32)
+    RET_ReallyLR implicit $w0
+...
+---
+name:            slt
+alignment:       4
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $w0
+    ; CHECK-LABEL: name: slt
+    ; CHECK: liveins: $w0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: %x:_(s32) = COPY $w0
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
+    ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR %x, [[C]](s32)
+    ; CHECK-NEXT: %select:_(s32) = G_AND %x, [[ASHR]]
+    ; CHECK-NEXT: $w0 = COPY %select(s32)
+    ; CHECK-NEXT: RET_ReallyLR implicit $w0
+    %x:_(s32) = COPY $w0
+    %zero:_(s32) = G_CONSTANT i32 0
+    %cmp:_(s1) = G_ICMP intpred(slt), %x(s32), %zero
+    %select:_(s32) = G_SELECT %cmp(s1), %x, %zero
+    $w0 = COPY %select(s32)
+    RET_ReallyLR implicit $w0
+...
+---
+name:            slt_commuted
+alignment:       4
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $w0
+    ; CHECK-LABEL: name: slt_commuted
+    ; CHECK: liveins: $w0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: %x:_(s32) = COPY $w0
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
+    ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR %x, [[C]](s32)
+    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+    ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[ASHR]], [[C1]]
+    ; CHECK-NEXT: %select:_(s32) = G_AND %x, [[XOR]]
+    ; CHECK-NEXT: $w0 = COPY %select(s32)
+    ; CHECK-NEXT: RET_ReallyLR implicit $w0
+    %x:_(s32) = COPY $w0
+    %zero:_(s32) = G_CONSTANT i32 0
+    %cmp:_(s1) = G_ICMP intpred(slt), %zero(s32), %x
+    %select:_(s32) = G_SELECT %cmp(s1), %x, %zero
+    $w0 = COPY %select(s32)
+    RET_ReallyLR implicit $w0
+...
+---
+name:            sle
+alignment:       4
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $w0
+    ; CHECK-LABEL: name: sle
+    ; CHECK: liveins: $w0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: %x:_(s32) = COPY $w0
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
+    ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR %x, [[C]](s32)
+    ; CHECK-NEXT: %select:_(s32) = G_AND %x, [[ASHR]]
+    ; CHECK-NEXT: $w0 = COPY %select(s32)
+    ; CHECK-NEXT: RET_ReallyLR implicit $w0
+    %x:_(s32) = COPY $w0
+    %zero:_(s32) = G_CONSTANT i32 0
+    %cmp:_(s1) = G_ICMP intpred(sle), %x(s32), %zero
+    %select:_(s32) = G_SELECT %cmp(s1), %x, %zero
+    $w0 = COPY %select(s32)
+    RET_ReallyLR implicit $w0
+...
+---
+name:            sle_commuted
+alignment:       4
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $w0
+    ; CHECK-LABEL: name: sle_commuted
+    ; CHECK: liveins: $w0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: %x:_(s32) = COPY $w0
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
+    ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR %x, [[C]](s32)
+    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+    ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[ASHR]], [[C1]]
+    ; CHECK-NEXT: %select:_(s32) = G_AND %x, [[XOR]]
+    ; CHECK-NEXT: $w0 = COPY %select(s32)
+    ; CHECK-NEXT: RET_ReallyLR implicit $w0
+    %x:_(s32) = COPY $w0
+    %zero:_(s32) = G_CONSTANT i32 0
+    %cmp:_(s1) = G_ICMP intpred(sle), %zero(s32), %x
+    %select:_(s32) = G_SELECT %cmp(s1), %x, %zero
+    $w0 = COPY %select(s32)
+    RET_ReallyLR implicit $w0
+...
+---
+name:            dont_combine_eq
+alignment:       4
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $w0
+    ; CHECK-LABEL: name: dont_combine_eq
+    ; CHECK: liveins: $w0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: %x:_(s32) = COPY $w0
+    ; CHECK-NEXT: %zero:_(s32) = G_CONSTANT i32 0
+    ; CHECK-NEXT: %cmp:_(s1) = G_ICMP intpred(eq), %x(s32), %zero
+    ; CHECK-NEXT: %select:_(s32) = G_SELECT %cmp(s1), %x, %zero
+    ; CHECK-NEXT: $w0 = COPY %select(s32)
+    ; CHECK-NEXT: RET_ReallyLR implicit $w0
+    %x:_(s32) = COPY $w0
+    %zero:_(s32) = G_CONSTANT i32 0
+    %cmp:_(s1) = G_ICMP intpred(eq), %x(s32), %zero
+    %select:_(s32) = G_SELECT %cmp(s1), %x, %zero
+    $w0 = COPY %select(s32)
+    RET_ReallyLR implicit $w0
+...
+---
+name:            dont_combine_unsigned
+alignment:       4
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $w0
+    ; CHECK-LABEL: name: dont_combine_unsigned
+    ; CHECK: liveins: $w0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: %x:_(s32) = COPY $w0
+    ; CHECK-NEXT: %zero:_(s32) = G_CONSTANT i32 0
+    ; CHECK-NEXT: %cmp:_(s1) = G_ICMP intpred(ugt), %x(s32), %zero
+    ; CHECK-NEXT: %select:_(s32) = G_SELECT %cmp(s1), %x, %zero
+    ; CHECK-NEXT: $w0 = COPY %select(s32)
+    %x:_(s32) = COPY $w0
+    %zero:_(s32) = G_CONSTANT i32 0
+    %cmp:_(s1) = G_ICMP intpred(ugt), %x(s32), %zero
+    %select:_(s32) = G_SELECT %cmp(s1), %x, %zero
+    $w0 = COPY %select(s32)
+...
+---
+name:            dont_combine_nonzero
+alignment:       4
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $w0
+    ; CHECK-LABEL: name: dont_combine_nonzero
+    ; CHECK: liveins: $w0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: %x:_(s32) = COPY $w0
+    ; CHECK-NEXT: %one:_(s32) = G_CONSTANT i32 1
+    ; CHECK-NEXT: %cmp:_(s1) = G_ICMP intpred(sgt), %x(s32), %one
+    ; CHECK-NEXT: %select:_(s32) = G_SELECT %cmp(s1), %x, %one
+    ; CHECK-NEXT: $w0 = COPY %select(s32)
+    %x:_(s32) = COPY $w0
+    %one:_(s32) = G_CONSTANT i32 1
+    %cmp:_(s1) = G_ICMP intpred(sgt), %x(s32), %one
+    %select:_(s32) = G_SELECT %cmp(s1), %x, %one
+    $w0 = COPY %select(s32)