[AMDGPU][MC] Correct image_gather4h

[dp]

Summary

Correct encoding of image_gather4h for GFX9; disable this instruction for SI, CI and VI.

See this issue.

[arsenm]

LGTM

llvm/lib/Target/AMDGPU/MIMGInstructions.td

 
 def MIMG {
   int NOP = -1;
 }
 
 class mimgopc <int gfx11, int gfx10m, int vi = gfx10m, int si = gfx10m> {
   field bits<8> GFX11 = gfx11;
   field bits<8> GFX10M = gfx10m; // GFX10minus for all but atomics
-  field bits<8> VI = vi; // VI is only used for atomic instructions
+  field bits<8> VI = vi; // VI is only used for atomic/sampler/gather instructions
   field bits<8> SI = si; // SI is only used for atomic instructions
   bit HAS_GFX11 = !ne(gfx11, MIMG.NOP);
   bit HAS_GFX10M = !ne(gfx10m, MIMG.NOP);
   bit HAS_VI = !ne(vi, MIMG.NOP);
   bit HAS_SI = !ne(si, MIMG.NOP);
 }
 
 class MIMGLZMapping<MIMGBaseOpcode l, MIMGBaseOpcode lz> {
let BaseOpcode = !cast<MIMGBaseOpcode>(NAME) in {
       let VDataDwords = !if(isCmpSwap, 4, 2) in
       defm _V2 : MIMG_Atomic_Addr_Helper_m <op, asm, !if(isCmpSwap, VReg_128, VReg_64), 0, isFP>;
     }
   } // End IsAtomicRet = 1
 }
 
 class MIMG_Sampler_Helper <mimgopc op, string asm, RegisterClass dst_rc,
                            RegisterClass src_rc, string dns="">
-  : MIMG_gfx6789 <op.GFX10M, (outs dst_rc:$vdata), dns> {
+  : MIMG_gfx6789 <op.VI, (outs dst_rc:$vdata), dns> {
   let InOperandList = !con((ins src_rc:$vaddr, SReg_256:$srsrc, SReg_128:$ssamp,
                                 DMask:$dmask, UNorm:$unorm, CPol:$cpol,
                                 R128A16:$r128, TFE:$tfe, LWE:$lwe, DA:$da),
                            !if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
   let AsmString = asm#" $vdata, $vaddr, $srsrc, $ssamp$dmask$unorm$cpol$r128$tfe$lwe$da"
                       #!if(BaseOpcode.HasD16, "$d16", "");
 }
 

 defm IMAGE_GATHER4_B_CL_O       : MIMG_Gather <mimgopc<MIMG.NOP, 0x56>, AMDGPUSample_b_cl_o>;
 defm IMAGE_GATHER4_LZ_O         : MIMG_Gather <mimgopc<0x36, 0x57>, AMDGPUSample_lz_o>;
 defm IMAGE_GATHER4_C_O          : MIMG_Gather_WQM <mimgopc<MIMG.NOP, 0x58>, AMDGPUSample_c_o>;
 defm IMAGE_GATHER4_C_CL_O       : MIMG_Gather_WQM <mimgopc<MIMG.NOP, 0x59>, AMDGPUSample_c_cl_o>;
 defm IMAGE_GATHER4_C_L_O        : MIMG_Gather <mimgopc<MIMG.NOP, 0x5c>, AMDGPUSample_c_l_o>;
 defm IMAGE_GATHER4_C_B_O        : MIMG_Gather_WQM <mimgopc<MIMG.NOP, 0x5d>, AMDGPUSample_c_b_o>;
 defm IMAGE_GATHER4_C_B_CL_O     : MIMG_Gather_WQM <mimgopc<MIMG.NOP, 0x5e>, AMDGPUSample_c_b_cl_o>;
 defm IMAGE_GATHER4_C_LZ_O       : MIMG_Gather <mimgopc<0x37, 0x5f>, AMDGPUSample_c_lz_o>;
-defm IMAGE_GATHER4H             : MIMG_Gather <mimgopc<0x90, 0x61>, AMDGPUSample, 1, "image_gather4h">;
+
+let SubtargetPredicate = isGFX9Plus in
+defm IMAGE_GATHER4H             : MIMG_Gather <mimgopc<0x90, 0x61, 0x42>, AMDGPUSample, 1, "image_gather4h">;
 
 defm IMAGE_GET_LOD              : MIMG_Sampler <mimgopc<0x38, 0x60>, AMDGPUSample, 1, 0, 1, "image_get_lod">;
 
 defm IMAGE_SAMPLE_CD            : MIMG_Sampler <mimgopc<MIMG.NOP, 0x68>, AMDGPUSample_cd>;
 defm IMAGE_SAMPLE_CD_CL         : MIMG_Sampler <mimgopc<MIMG.NOP, 0x69>, AMDGPUSample_cd_cl>;
 defm IMAGE_SAMPLE_C_CD          : MIMG_Sampler <mimgopc<MIMG.NOP, 0x6a>, AMDGPUSample_c_cd>;
 defm IMAGE_SAMPLE_C_CD_CL       : MIMG_Sampler <mimgopc<MIMG.NOP, 0x6b>, AMDGPUSample_c_cd_cl>;
 defm IMAGE_SAMPLE_CD_O          : MIMG_Sampler <mimgopc<MIMG.NOP, 0x6c>, AMDGPUSample_cd_o>;

llvm/test/MC/AMDGPU/gfx7_unsupported.s

 // CHECK: error: instruction not supported on this GPU
 
 image_sample_d_g16 v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x3
 // CHECK: error: instruction not supported on this GPU
 
 image_sample_d_o_g16 v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x3
 // CHECK: error: instruction not supported on this GPU
 
+image_gather4h v[251:254], v[1:2], s[8:15], s[12:15] dmask:0x1
+// CHECK: error: instruction not supported on this GPU
+
 v_interp_mov_f32_e64 v255, p10, attr0.x
 // CHECK: error: e64 variant of this instruction is not supported
 
 v_interp_p1_f32_e64 v255, v2, attr0.x
 // CHECK: error: e64 variant of this instruction is not supported
 
 v_interp_p2_f32_e64 v255, v2, attr0.x
 // CHECK: error: e64 variant of this instruction is not supported

llvm/test/MC/AMDGPU/gfx8_unsupported.s

 // CHECK: error: instruction not supported on this GPU
 
 image_sample_d_g16 v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x3
 // CHECK: error: instruction not supported on this GPU
 
 image_sample_d_o_g16 v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x3
 // CHECK: error: instruction not supported on this GPU
 
+image_gather4h v[251:254], v[1:2], s[8:15], s[12:15] dmask:0x1
+// CHECK: error: instruction not supported on this GPU
+
 buffer_atomic_add_f32 v255, off, s[8:11], s3 offset:4095
 // CHECK: error: instruction not supported on this GPU
 
 buffer_atomic_fcmpswap v[0:1], off, s[0:3], s0 offset:4095
 // CHECK: error: instruction not supported on this GPU
 
 buffer_atomic_fcmpswap_x2 v[0:3], off, s[0:3], s0 offset:4095
 // CHECK: error: instruction not supported on this GPU

llvm/test/MC/AMDGPU/gfx90a_err.s

 // GFX90A: error: instruction not supported on this GPU
 
 ds_write_src2_b64 v1
 // GFX90A: error: instruction not supported on this GPU
 
 image_gather4 v[5:8], v1, s[8:15], s[12:15]
 // GFX90A: error: instruction not supported on this GPU
 
+image_gather4h v[251:254], v[1:2], s[8:15], s[12:15] dmask:0x1
+// GFX90A: error: instruction not supported on this GPU
+
 image_get_lod v5, v1, s[8:15], s[12:15]
 // GFX90A: error: instruction not supported on this GPU
 
 v_mul_legacy_f32_e32 v5, v1, v2
 // GFX90A: error: e32 variant of this instruction is not supported
 
 v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
 // GFX90A: error: sdwa variant of this instruction is not supported

llvm/test/MC/AMDGPU/gfx9_asm_mimg.s

 // CHECK: [0x00,0x01,0x7e,0xf1,0x01,0x05,0x62,0x00]
 
 image_gather4_c_lz_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 da
 // CHECK: [0x00,0x41,0x7c,0xf1,0x01,0x05,0x62,0x00]
 
 image_gather4_c_lz_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x1 d16
 // CHECK: [0x00,0x01,0x7c,0xf1,0x01,0x05,0x62,0x80]
 
+image_gather4h v[5:8], v[1:2], s[8:15], s[12:15] dmask:0x1
+// CHECK: encoding: [0x00,0x01,0x08,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4h v[5:8], v[254:255], s[8:15], s[12:15] dmask:0x2
+// CHECK: encoding: [0x00,0x02,0x08,0xf1,0xfe,0x05,0x62,0x00]
+
+image_gather4h v[5:8], v1, s[8:15], s[12:15] dmask:0x4 a16
+// CHECK: [0x00,0x84,0x08,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4h v[5:8], v255, s[8:15], s[12:15] dmask:0x8 a16
+// CHECK: encoding: [0x00,0x88,0x08,0xf1,0xff,0x05,0x62,0x00]
+
+image_gather4h v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x08,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4h v[252:255], v[253:255], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x08,0xf1,0xfd,0xfc,0x62,0x00]
+
+image_gather4h v[5:6], v[1:2], s[92:99], s[96:99] dmask:0x4 a16 d16
+// CHECK: [0x00,0x84,0x08,0xf1,0x01,0x05,0x17,0x83]
+
+image_gather4h v[254:255], v[254:255], ttmp[8:15], ttmp[12:15] dmask:0x4 unorm glc slc a16 lwe da d16
+// CHECK: [0x00,0xf4,0x0a,0xf3,0xfe,0xfe,0xdd,0x83]
+
 image_get_lod v5, v1, s[8:15], s[12:15] dmask:0x1
 // CHECK: [0x00,0x01,0x80,0xf1,0x01,0x05,0x62,0x00]
 
 image_get_lod v252, v1, s[8:15], s[12:15] dmask:0x1
 // CHECK: [0x00,0x01,0x80,0xf1,0x01,0xfc,0x62,0x00]
 
 image_get_lod v5, v253, s[8:15], s[12:15] dmask:0x1
 // CHECK: [0x00,0x01,0x80,0xf1,0xfd,0x05,0x62,0x00]

llvm/test/MC/Disassembler/AMDGPU/gfx9_mimg.txt

 # CHECK: image_gather4_lz_o v[5:8], v[1:2], s[8:15], s[12:15] dmask:0x1 lwe ; encoding: [0x00,0x01,0x5e,0xf1,0x01,0x05,0x62,0x00]
 0x00,0x01,0x5e,0xf1,0x01,0x05,0x62,0x00
 
 # CHECK: image_gather4_lz_o v[5:8], v[1:2], s[8:15], s[12:15] dmask:0x1 da ; encoding: [0x00,0x41,0x5c,0xf1,0x01,0x05,0x62,0x00]
 0x00,0x41,0x5c,0xf1,0x01,0x05,0x62,0x00
 
 # CHECK: image_gather4_lz_o v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x1 d16 ; encoding: [0x00,0x01,0x5c,0xf1,0x01,0x05,0x62,0x80]
 0x00,0x01,0x5c,0xf1,0x01,0x05,0x62,0x80
+
+# CHECK: image_gather4h v[5:8], v1, s[8:15], s[12:15] dmask:0x1 ; encoding: [0x00,0x01,0x08,0xf1,0x01,0x05,0x62,0x00]
+0x00,0x01,0x08,0xf1,0x01,0x05,0x62,0x00
+
+# CHECK: image_gather4h v[5:8], v255, s[8:15], s[12:15] dmask:0x2 ; encoding: [0x00,0x02,0x08,0xf1,0xff,0x05,0x62,0x00]
+0x00,0x02,0x08,0xf1,0xff,0x05,0x62,0x00
+
+# CHECK: image_gather4h v[5:8], v255, s[8:15], s[12:15] dmask:0x4 ; encoding: [0x00,0x04,0x08,0xf1,0xff,0x05,0x62,0x00]
+0x00,0x04,0x08,0xf1,0xff,0x05,0x62,0x00
+
+# CHECK: image_gather4h v[5:8], v255, s[8:15], s[12:15] dmask:0x8 a16 ; encoding: [0x00,0x88,0x08,0xf1,0xff,0x05,0x62,0x00]
+0x00,0x88,0x08,0xf1,0xff,0x05,0x62,0x00
+
+# CHECK: image_gather4h v[5:6], v255, s[92:99], s[96:99] dmask:0x8 d16 ; encoding: [0x00,0x08,0x08,0xf1,0xff,0x05,0x17,0x83]
+0x00,0x08,0x08,0xf1,0xff,0x05,0x17,0x83
+
+# CHECK: image_gather4h v[252:255], v255, ttmp[8:15], ttmp[12:15] dmask:0x4 unorm glc slc a16 lwe da ; encoding: [0x00,0xf4,0x0a,0xf3,0xff,0xfc,0xdd,0x03]
+0x00,0xf4,0x0a,0xf3,0xff,0xfc,0xdd,0x03