[GlobalISel] Mark mi_match as nodiscard

[paquette]

Summary

Typically when you match something, you want to check the result.

Fix a couple warnings in the AMDGPUPostLegalizerCombiner which appear as a result of this.

llvm/include/llvm/CodeGen/GlobalISel/MIPatternMatch.h

 #include "llvm/CodeGen/GlobalISel/Utils.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/IR/InstrTypes.h"
 
 namespace llvm {
 namespace MIPatternMatch {
 
 template <typename Reg, typename Pattern>
-bool mi_match(Reg R, const MachineRegisterInfo &MRI, Pattern &&P) {
+[[nodiscard]] bool mi_match(Reg R, const MachineRegisterInfo &MRI,
+                            Pattern &&P) {
   return P.match(MRI, R);
 }
 
 template <typename Pattern>
-bool mi_match(MachineInstr &MI, const MachineRegisterInfo &MRI, Pattern &&P) {
+[[nodiscard]] bool mi_match(MachineInstr &MI, const MachineRegisterInfo &MRI,
+                            Pattern &&P) {
   return P.match(MRI, &MI);
 }
 
 // TODO: Extend for N use.
 template <typename SubPatternT> struct OneUse_match {
   SubPatternT SubPat;
   OneUse_match(const SubPatternT &SP) : SubPat(SP) {}
 

llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp

if (MI.getOpcode() == TargetOpcode::G_INTRINSIC &&
         MI.getIntrinsicID() == Intrinsic::amdgcn_rcp)
       ResMI = MRI.getVRegDef(MI.getOperand(2).getReg());
 
     return ResMI;
   };
 
   auto getSqrtSrc = [=](const MachineInstr &MI) {
     MachineInstr *SqrtSrcMI = nullptr;
+    auto Match =
         mi_match(MI.getOperand(0).getReg(), MRI, m_GFSqrt(m_MInstr(SqrtSrcMI)));
+    (void)Match;
     return SqrtSrcMI;
   };
 
   MachineInstr *RcpSrcMI = nullptr, *SqrtSrcMI = nullptr;
   // rcp(sqrt(x))
   if ((RcpSrcMI = getRcpSrc(MI)) && (SqrtSrcMI = getSqrtSrc(*RcpSrcMI))) {
     MatchInfo = [SqrtSrcMI, &MI](MachineIRBuilder &B) {
       B.buildIntrinsic(Intrinsic::amdgcn_rsq, {MI.getOperand(0)}, false)
bool AMDGPUPostLegalizerCombinerHelper::matchRcpSqrtToRsq(
   return false;
 }
 
 bool AMDGPUPostLegalizerCombinerHelper::matchCvtF32UByteN(
     MachineInstr &MI, CvtF32UByteMatchInfo &MatchInfo) {
   Register SrcReg = MI.getOperand(1).getReg();
 
   // Look through G_ZEXT.
-  mi_match(SrcReg, MRI, m_GZExt(m_Reg(SrcReg)));
+  bool IsShr = mi_match(SrcReg, MRI, m_GZExt(m_Reg(SrcReg)));
 
   Register Src0;
   int64_t ShiftAmt;
-  bool IsShr = mi_match(SrcReg, MRI, m_GLShr(m_Reg(Src0), m_ICst(ShiftAmt)));
+  IsShr = mi_match(SrcReg, MRI, m_GLShr(m_Reg(Src0), m_ICst(ShiftAmt)));
   if (IsShr || mi_match(SrcReg, MRI, m_GShl(m_Reg(Src0), m_ICst(ShiftAmt)))) {
     const unsigned Offset = MI.getOpcode() - AMDGPU::G_AMDGPU_CVT_F32_UBYTE0;
 
     unsigned ShiftOffset = 8 * Offset;
     if (IsShr)
       ShiftOffset += ShiftAmt;
     else
       ShiftOffset -= ShiftAmt;