[Clang][OpenMP] Add one missing form of atomic compare capture

[tianshilei1992]

Summary

Two another atomic compare capture forms, { v = x; expr-stmt } and { expr-stmt; v = x; }
where expr-stmt could be cond-expr-stmt are missing.

[tianshilei1992]

rebase and fix tests

[ABataev]

LG

[tianshilei1992]

regenerate tests

clang/lib/Sema/SemaOpenMP.cpp

if (CS->size() == 1) {
 
     return checkForm3(IS, ErrorInfo);
   } else if (CS->size() == 2) {
     auto *S1 = CS->body_front();
     auto *S2 = CS->body_back();
 
     Stmt *UpdateStmt = nullptr;
     Stmt *CondUpdateStmt = nullptr;
+    Stmt *CondExprStmt = nullptr;
 
     if (auto *BO = dyn_cast<BinaryOperator>(S1)) {
-      // { v = x; cond-update-stmt } or form 45.
-      UpdateStmt = S1;
-      CondUpdateStmt = S2;
-      // Check if form 45.
-      if (isa<BinaryOperator>(BO->getRHS()->IgnoreImpCasts()) &&
-          isa<IfStmt>(S2))
+      // It could be one of the following cases:
+      // { v = x; cond-update-stmt }
+      // { v = x; cond-expr-stmt }
+      // { cond-expr-stmt; v = x; }
+      // form 45
+      if (isa<BinaryOperator>(BO->getRHS()->IgnoreImpCasts()) ||
+          isa<ConditionalOperator>(BO->getRHS()->IgnoreImpCasts())) {
+        // check if form 45
+        if (isa<IfStmt>(S2))
           return checkForm45(CS, ErrorInfo);
-      // It cannot be set before we the check for form45.
+        // { cond-expr-stmt; v = x; }
+        CondExprStmt = S1;
+        UpdateStmt = S2;
+      } else {
         IsPostfixUpdate = true;
+        UpdateStmt = S1;
+        if (isa<IfStmt>(S2)) {
+          // { v = x; cond-update-stmt }
+          CondUpdateStmt = S2;
+        } else {
+          // { v = x; cond-expr-stmt }
+          CondExprStmt = S2;
+        }
+      }
     } else {
       // { cond-update-stmt v = x; }
       UpdateStmt = S2;
       CondUpdateStmt = S1;
     }
 
     auto CheckCondUpdateStmt = [this, &ErrorInfo](Stmt *CUS) {
       auto *IS = dyn_cast<IfStmt>(CUS);
       if (!IS) {
         ErrorInfo.Error = ErrorTy::NotIfStmt;
         ErrorInfo.ErrorLoc = ErrorInfo.NoteLoc = CUS->getBeginLoc();
         ErrorInfo.ErrorRange = ErrorInfo.NoteRange = CUS->getSourceRange();
         return false;
       }
 
-      if (!checkCondUpdateStmt(IS, ErrorInfo))
-        return false;
-
-      return true;
+      return checkCondUpdateStmt(IS, ErrorInfo);
     };
 
     // CheckUpdateStmt has to be called *after* CheckCondUpdateStmt.
     auto CheckUpdateStmt = [this, &ErrorInfo](Stmt *US) {
       auto *BO = dyn_cast<BinaryOperator>(US);
       if (!BO) {
         ErrorInfo.Error = ErrorTy::NotAnAssignment;
         ErrorInfo.ErrorLoc = ErrorInfo.NoteLoc = US->getBeginLoc();
auto CheckUpdateStmt = [this, &ErrorInfo](Stmt *US) {
         return false;
       }
 
       this->V = BO->getLHS();
 
       return true;
     };
 
-    if (!CheckCondUpdateStmt(CondUpdateStmt))
+    if (CondUpdateStmt && !CheckCondUpdateStmt(CondUpdateStmt))
+      return false;
+    if (CondExprStmt && !checkCondExprStmt(CondExprStmt, ErrorInfo))
       return false;
     if (!CheckUpdateStmt(UpdateStmt))
       return false;
   } else {
     ErrorInfo.Error = ErrorTy::MoreThanTwoStmts;
     ErrorInfo.ErrorLoc = ErrorInfo.NoteLoc = CS->getBeginLoc();
     ErrorInfo.ErrorRange = ErrorInfo.NoteRange = CS->getSourceRange();
     return false;

clang/test/OpenMP/atomic_ast_print.cpp

 // CHECK-51-NEXT: ffoo(&x, e, d);
 // CHECK-51-NEXT: }
 // CHECK-51-NEXT: {
 // CHECK-51-NEXT: double x, e, d;
 // CHECK-51-NEXT: ffoo(&x, e, d);
 // CHECK-51-NEXT: }
 // CHECK-51-NEXT: }
 
+int xevd() {
+  int x, v, e, d;
+
+#pragma omp atomic compare capture
+  {
+    v = x;
+    x = x > e ? e : x;
+  }
+#pragma omp atomic compare capture
+  {
+    v = x;
+    x = x < e ? e : x;
+  }
+#pragma omp atomic compare capture
+  {
+    v = x;
+    x = x == e ? d : x;
+  }
+#pragma omp atomic compare capture
+  {
+    x = x > e ? e : x;
+    v = x;
+  }
+#pragma omp atomic compare capture
+  {
+    x = x < e ? e : x;
+    v = x;
+  }
+#pragma omp atomic compare capture
+  {
+    x = x == e ? d : x;
+    v = x;
+  }
+
+#pragma omp atomic compare capture acq_rel
+  {
+    v = x;
+    x = x > e ? e : x;
+  }
+#pragma omp atomic compare capture acq_rel
+  {
+    v = x;
+    x = x < e ? e : x;
+  }
+#pragma omp atomic compare capture acq_rel
+  {
+    v = x;
+    x = x == e ? d : x;
+  }
+#pragma omp atomic compare capture acq_rel
+  {
+    x = x > e ? e : x;
+    v = x;
+  }
+#pragma omp atomic compare capture acq_rel
+  {
+    x = x < e ? e : x;
+    v = x;
+  }
+#pragma omp atomic compare capture acq_rel
+  {
+    x = x == e ? d : x;
+    v = x;
+  }
+
+#pragma omp atomic compare capture acquire
+  {
+    v = x;
+    x = x > e ? e : x;
+  }
+#pragma omp atomic compare capture acquire
+  {
+    v = x;
+    x = x < e ? e : x;
+  }
+#pragma omp atomic compare capture acquire
+  {
+    v = x;
+    x = x == e ? d : x;
+  }
+#pragma omp atomic compare capture acquire
+  {
+    x = x > e ? e : x;
+    v = x;
+  }
+#pragma omp atomic compare capture acquire
+  {
+    x = x < e ? e : x;
+    v = x;
+  }
+#pragma omp atomic compare capture acquire
+  {
+    x = x == e ? d : x;
+    v = x;
+  }
+
+#pragma omp atomic compare capture relaxed
+  {
+    v = x;
+    x = x > e ? e : x;
+  }
+#pragma omp atomic compare capture relaxed
+  {
+    v = x;
+    x = x < e ? e : x;
+  }
+#pragma omp atomic compare capture relaxed
+  {
+    v = x;
+    x = x == e ? d : x;
+  }
+#pragma omp atomic compare capture relaxed
+  {
+    x = x > e ? e : x;
+    v = x;
+  }
+#pragma omp atomic compare capture relaxed
+  {
+    x = x < e ? e : x;
+    v = x;
+  }
+#pragma omp atomic compare capture relaxed
+  {
+    x = x == e ? d : x;
+    v = x;
+  }
+
+#pragma omp atomic compare capture release
+  {
+    v = x;
+    x = x > e ? e : x;
+  }
+#pragma omp atomic compare capture release
+  {
+    v = x;
+    x = x < e ? e : x;
+  }
+#pragma omp atomic compare capture release
+  {
+    v = x;
+    x = x == e ? d : x;
+  }
+#pragma omp atomic compare capture release
+  {
+    x = x > e ? e : x;
+    v = x;
+  }
+#pragma omp atomic compare capture release
+  {
+    x = x < e ? e : x;
+    v = x;
+  }
+#pragma omp atomic compare capture release
+  {
+    x = x == e ? d : x;
+    v = x;
+  }
+
+#pragma omp atomic compare capture seq_cst
+  {
+    v = x;
+    x = x > e ? e : x;
+  }
+#pragma omp atomic compare capture seq_cst
+  {
+    v = x;
+    x = x < e ? e : x;
+  }
+#pragma omp atomic compare capture seq_cst
+  {
+    v = x;
+    x = x == e ? d : x;
+  }
+#pragma omp atomic compare capture seq_cst
+  {
+    x = x > e ? e : x;
+    v = x;
+  }
+#pragma omp atomic compare capture seq_cst
+  {
+    x = x < e ? e : x;
+    v = x;
+  }
+#pragma omp atomic compare capture seq_cst
+  {
+    x = x == e ? d : x;
+    v = x;
+  }
+
+  return v;
+}
+
+// CHECK-51: int xevd() {
+// CHECK-51-NEXT: int x, v, e, d;
+// CHECK-51-NEXT: #pragma omp atomic compare capture
+// CHECK-51-NEXT: {
+// CHECK-51-NEXT: v = x;
+// CHECK-51-NEXT: x = x > e ? e : x;
+// CHECK-51-NEXT: }
+// CHECK-51-NEXT: #pragma omp atomic compare capture
+// CHECK-51-NEXT: {
+// CHECK-51-NEXT: v = x;
+// CHECK-51-NEXT: x = x < e ? e : x;
+// CHECK-51-NEXT: }
+// CHECK-51-NEXT: #pragma omp atomic compare capture
+// CHECK-51-NEXT: {
+// CHECK-51-NEXT: v = x;
+// CHECK-51-NEXT: x = x == e ? d : x;
+// CHECK-51-NEXT: }
+// CHECK-51-NEXT: #pragma omp atomic compare capture
+// CHECK-51-NEXT: {
+// CHECK-51-NEXT: x = x > e ? e : x;
+// CHECK-51-NEXT: v = x;
+// CHECK-51-NEXT: }
+// CHECK-51-NEXT: #pragma omp atomic compare capture
+// CHECK-51-NEXT: {
+// CHECK-51-NEXT: x = x < e ? e : x;
+// CHECK-51-NEXT: v = x;
+// CHECK-51-NEXT: }
+// CHECK-51-NEXT: #pragma omp atomic compare capture
+// CHECK-51-NEXT: {
+// CHECK-51-NEXT: x = x == e ? d : x;
+// CHECK-51-NEXT: v = x;
+// CHECK-51-NEXT: }
+// CHECK-51-NEXT: #pragma omp atomic compare capture acq_rel
+// CHECK-51-NEXT: {
+// CHECK-51-NEXT: v = x;
+// CHECK-51-NEXT: x = x > e ? e : x;
+// CHECK-51-NEXT: }
+// CHECK-51-NEXT: #pragma omp atomic compare capture acq_rel
+// CHECK-51-NEXT: {
+// CHECK-51-NEXT: v = x;
+// CHECK-51-NEXT: x = x < e ? e : x;
+// CHECK-51-NEXT: }
+// CHECK-51-NEXT: #pragma omp atomic compare capture acq_rel
+// CHECK-51-NEXT: {
+// CHECK-51-NEXT: v = x;
+// CHECK-51-NEXT: x = x == e ? d : x;
+// CHECK-51-NEXT: }
+// CHECK-51-NEXT: #pragma omp atomic compare capture acq_rel
+// CHECK-51-NEXT: {
+// CHECK-51-NEXT: x = x > e ? e : x;
+// CHECK-51-NEXT: v = x;
+// CHECK-51-NEXT: }
+// CHECK-51-NEXT: #pragma omp atomic compare capture acq_rel
+// CHECK-51-NEXT: {
+// CHECK-51-NEXT: x = x < e ? e : x;
+// CHECK-51-NEXT: v = x;
+// CHECK-51-NEXT: }
+// CHECK-51-NEXT: #pragma omp atomic compare capture acq_rel
+// CHECK-51-NEXT: {
+// CHECK-51-NEXT: x = x == e ? d : x;
+// CHECK-51-NEXT: v = x;
+// CHECK-51-NEXT: }
+// CHECK-51-NEXT: #pragma omp atomic compare capture acquire
+// CHECK-51-NEXT: {
+// CHECK-51-NEXT: v = x;
+// CHECK-51-NEXT: x = x > e ? e : x;
+// CHECK-51-NEXT: }
+// CHECK-51-NEXT: #pragma omp atomic compare capture acquire
+// CHECK-51-NEXT: {
+// CHECK-51-NEXT: v = x;
+// CHECK-51-NEXT: x = x < e ? e : x;
+// CHECK-51-NEXT: }
+// CHECK-51-NEXT: #pragma omp atomic compare capture acquire
+// CHECK-51-NEXT: {
+// CHECK-51-NEXT: v = x;
+// CHECK-51-NEXT: x = x == e ? d : x;
+// CHECK-51-NEXT: }
+// CHECK-51-NEXT: #pragma omp atomic compare capture acquire
+// CHECK-51-NEXT: {
+// CHECK-51-NEXT: x = x > e ? e : x;
+// CHECK-51-NEXT: v = x;
+// CHECK-51-NEXT: }
+// CHECK-51-NEXT: #pragma omp atomic compare capture acquire
+// CHECK-51-NEXT: {
+// CHECK-51-NEXT: x = x < e ? e : x;
+// CHECK-51-NEXT: v = x;
+// CHECK-51-NEXT: }
+// CHECK-51-NEXT: #pragma omp atomic compare capture acquire
+// CHECK-51-NEXT: {
+// CHECK-51-NEXT: x = x == e ? d : x;
+// CHECK-51-NEXT: v = x;
+// CHECK-51-NEXT: }
+// CHECK-51-NEXT: #pragma omp atomic compare capture relaxed
+// CHECK-51-NEXT: {
+// CHECK-51-NEXT: v = x;
+// CHECK-51-NEXT: x = x > e ? e : x;
+// CHECK-51-NEXT: }
+// CHECK-51-NEXT: #pragma omp atomic compare capture relaxed
+// CHECK-51-NEXT: {
+// CHECK-51-NEXT: v = x;
+// CHECK-51-NEXT: x = x < e ? e : x;
+// CHECK-51-NEXT: }
+// CHECK-51-NEXT: #pragma omp atomic compare capture relaxed
+// CHECK-51-NEXT: {
+// CHECK-51-NEXT: v = x;
+// CHECK-51-NEXT: x = x == e ? d : x;
+// CHECK-51-NEXT: }
+// CHECK-51-NEXT: #pragma omp atomic compare capture relaxed
+// CHECK-51-NEXT: {
+// CHECK-51-NEXT: x = x > e ? e : x;
+// CHECK-51-NEXT: v = x;
+// CHECK-51-NEXT: }
+// CHECK-51-NEXT: #pragma omp atomic compare capture relaxed
+// CHECK-51-NEXT: {
+// CHECK-51-NEXT: x = x < e ? e : x;
+// CHECK-51-NEXT: v = x;
+// CHECK-51-NEXT: }
+// CHECK-51-NEXT: #pragma omp atomic compare capture relaxed
+// CHECK-51-NEXT: {
+// CHECK-51-NEXT: x = x == e ? d : x;
+// CHECK-51-NEXT: v = x;
+// CHECK-51-NEXT: }
+// CHECK-51-NEXT: #pragma omp atomic compare capture release
+// CHECK-51-NEXT: {
+// CHECK-51-NEXT: v = x;
+// CHECK-51-NEXT: x = x > e ? e : x;
+// CHECK-51-NEXT: }
+// CHECK-51-NEXT: #pragma omp atomic compare capture release
+// CHECK-51-NEXT: {
+// CHECK-51-NEXT: v = x;
+// CHECK-51-NEXT: x = x < e ? e : x;
+// CHECK-51-NEXT: }
+// CHECK-51-NEXT: #pragma omp atomic compare capture release
+// CHECK-51-NEXT: {
+// CHECK-51-NEXT: v = x;
+// CHECK-51-NEXT: x = x == e ? d : x;
+// CHECK-51-NEXT: }
+// CHECK-51-NEXT: #pragma omp atomic compare capture release
+// CHECK-51-NEXT: {
+// CHECK-51-NEXT: x = x > e ? e : x;
+// CHECK-51-NEXT: v = x;
+// CHECK-51-NEXT: }
+// CHECK-51-NEXT: #pragma omp atomic compare capture release
+// CHECK-51-NEXT: {
+// CHECK-51-NEXT: x = x < e ? e : x;
+// CHECK-51-NEXT: v = x;
+// CHECK-51-NEXT: }
+// CHECK-51-NEXT: #pragma omp atomic compare capture release
+// CHECK-51-NEXT: {
+// CHECK-51-NEXT: x = x == e ? d : x;
+// CHECK-51-NEXT: v = x;
+// CHECK-51-NEXT: }
+// CHECK-51-NEXT: #pragma omp atomic compare capture seq_cst
+// CHECK-51-NEXT: {
+// CHECK-51-NEXT: v = x;
+// CHECK-51-NEXT: x = x > e ? e : x;
+// CHECK-51-NEXT: }
+// CHECK-51-NEXT: #pragma omp atomic compare capture seq_cst
+// CHECK-51-NEXT: {
+// CHECK-51-NEXT: v = x;
+// CHECK-51-NEXT: x = x < e ? e : x;
+// CHECK-51-NEXT: }
+// CHECK-51-NEXT: #pragma omp atomic compare capture seq_cst
+// CHECK-51-NEXT: {
+// CHECK-51-NEXT: v = x;
+// CHECK-51-NEXT: x = x == e ? d : x;
+// CHECK-51-NEXT: }
+// CHECK-51-NEXT: #pragma omp atomic compare capture seq_cst
+// CHECK-51-NEXT: {
+// CHECK-51-NEXT: x = x > e ? e : x;
+// CHECK-51-NEXT: v = x;
+// CHECK-51-NEXT: }
+// CHECK-51-NEXT: #pragma omp atomic compare capture seq_cst
+// CHECK-51-NEXT: {
+// CHECK-51-NEXT: x = x < e ? e : x;
+// CHECK-51-NEXT: v = x;
+// CHECK-51-NEXT: }
+// CHECK-51-NEXT: pragma omp atomic compare capture seq_cst
+// CHECK-51-NEXT: {
+// CHECK-51-NEXT: x = x == e ? d : x;
+// CHECK-51-NEXT: v = x;
+// CHECK-51-NEXT: }
+// CHECK-51-NEXT: return v;
+// CHECK-51-NEXT: }
+
 #endif
 
 #endif

clang/test/OpenMP/atomic_compare_codegen.cpp

#pragma omp atomic compare capture seq_cst
     if (ir) {
       dx = dd;
     } else {
       dv = dx;
     }
   }
 }
 
+
+char cxevd() {
+  char cx, cv, ce, cd;
+
+#pragma omp atomic compare capture
+  {
+    cv = cx;
+    cx = cx > ce ? ce : cx;
+  }
+#pragma omp atomic compare capture
+  {
+    cv = cx;
+    cx = cx < ce ? ce : cx;
+  }
+#pragma omp atomic compare capture
+  {
+    cv = cx;
+    cx = cx == ce ? cd : cx;
+  }
+#pragma omp atomic compare capture
+  {
+    cx = cx > ce ? ce : cx;
+    cv = cx;
+  }
+#pragma omp atomic compare capture
+  {
+    cx = cx < ce ? ce : cx;
+    cv = cx;
+  }
+#pragma omp atomic compare capture
+  {
+    cx = cx == ce ? cd : cx;
+    cv = cx;
+  }
+
+#pragma omp atomic compare capture acq_rel
+  {
+    cv = cx;
+    cx = cx > ce ? ce : cx;
+  }
+#pragma omp atomic compare capture acq_rel
+  {
+    cv = cx;
+    cx = cx < ce ? ce : cx;
+  }
+#pragma omp atomic compare capture acq_rel
+  {
+    cv = cx;
+    cx = cx == ce ? cd : cx;
+  }
+#pragma omp atomic compare capture acq_rel
+  {
+    cx = cx > ce ? ce : cx;
+    cv = cx;
+  }
+#pragma omp atomic compare capture acq_rel
+  {
+    cx = cx < ce ? ce : cx;
+    cv = cx;
+  }
+#pragma omp atomic compare capture acq_rel
+  {
+    cx = cx == ce ? cd : cx;
+    cv = cx;
+  }
+
+#pragma omp atomic compare capture acquire
+  {
+    cv = cx;
+    cx = cx > ce ? ce : cx;
+  }
+#pragma omp atomic compare capture acquire
+  {
+    cv = cx;
+    cx = cx < ce ? ce : cx;
+  }
+#pragma omp atomic compare capture acquire
+  {
+    cv = cx;
+    cx = cx == ce ? cd : cx;
+  }
+#pragma omp atomic compare capture acquire
+  {
+    cx = cx > ce ? ce : cx;
+    cv = cx;
+  }
+#pragma omp atomic compare capture acquire
+  {
+    cx = cx < ce ? ce : cx;
+    cv = cx;
+  }
+#pragma omp atomic compare capture acquire
+  {
+    cx = cx == ce ? cd : cx;
+    cv = cx;
+  }
+
+#pragma omp atomic compare capture relaxed
+  {
+    cv = cx;
+    cx = cx > ce ? ce : cx;
+  }
+#pragma omp atomic compare capture relaxed
+  {
+    cv = cx;
+    cx = cx < ce ? ce : cx;
+  }
+#pragma omp atomic compare capture relaxed
+  {
+    cv = cx;
+    cx = cx == ce ? cd : cx;
+  }
+#pragma omp atomic compare capture relaxed
+  {
+    cx = cx > ce ? ce : cx;
+    cv = cx;
+  }
+#pragma omp atomic compare capture relaxed
+  {
+    cx = cx < ce ? ce : cx;
+    cv = cx;
+  }
+#pragma omp atomic compare capture relaxed
+  {
+    cx = cx == ce ? cd : cx;
+    cv = cx;
+  }
+
+#pragma omp atomic compare capture release
+  {
+    cv = cx;
+    cx = cx > ce ? ce : cx;
+  }
+#pragma omp atomic compare capture release
+  {
+    cv = cx;
+    cx = cx < ce ? ce : cx;
+  }
+#pragma omp atomic compare capture release
+  {
+    cv = cx;
+    cx = cx == ce ? cd : cx;
+  }
+#pragma omp atomic compare capture release
+  {
+    cx = cx > ce ? ce : cx;
+    cv = cx;
+  }
+#pragma omp atomic compare capture release
+  {
+    cx = cx < ce ? ce : cx;
+    cv = cx;
+  }
+#pragma omp atomic compare capture release
+  {
+    cx = cx == ce ? cd : cx;
+    cv = cx;
+  }
+
+#pragma omp atomic compare capture seq_cst
+  {
+    cv = cx;
+    cx = cx > ce ? ce : cx;
+  }
+#pragma omp atomic compare capture seq_cst
+  {
+    cv = cx;
+    cx = cx < ce ? ce : cx;
+  }
+#pragma omp atomic compare capture seq_cst
+  {
+    cv = cx;
+    cx = cx == ce ? cd : cx;
+  }
+#pragma omp atomic compare capture seq_cst
+  {
+    cx = cx > ce ? ce : cx;
+    cv = cx;
+  }
+#pragma omp atomic compare capture seq_cst
+  {
+    cx = cx < ce ? ce : cx;
+    cv = cx;
+  }
+#pragma omp atomic compare capture seq_cst
+  {
+    cx = cx == ce ? cd : cx;
+    cv = cx;
+  }
+
+  return cv;
+}
+
+unsigned char ucxevd() {
+  unsigned char ucx, ucv, uce, ucd;
+
+#pragma omp atomic compare capture
+  {
+    ucv = ucx;
+    ucx = ucx > uce ? uce : ucx;
+  }
+#pragma omp atomic compare capture
+  {
+    ucv = ucx;
+    ucx = ucx < uce ? uce : ucx;
+  }
+#pragma omp atomic compare capture
+  {
+    ucv = ucx;
+    ucx = ucx == uce ? ucd : ucx;
+  }
+#pragma omp atomic compare capture
+  {
+    ucx = ucx > uce ? uce : ucx;
+    ucv = ucx;
+  }
+#pragma omp atomic compare capture
+  {
+    ucx = ucx < uce ? uce : ucx;
+    ucv = ucx;
+  }
+#pragma omp atomic compare capture
+  {
+    ucx = ucx == uce ? ucd : ucx;
+    ucv = ucx;
+  }
+
+#pragma omp atomic compare capture acq_rel
+  {
+    ucv = ucx;
+    ucx = ucx > uce ? uce : ucx;
+  }
+#pragma omp atomic compare capture acq_rel
+  {
+    ucv = ucx;
+    ucx = ucx < uce ? uce : ucx;
+  }
+#pragma omp atomic compare capture acq_rel
+  {
+    ucv = ucx;
+    ucx = ucx == uce ? ucd : ucx;
+  }
+#pragma omp atomic compare capture acq_rel
+  {
+    ucx = ucx > uce ? uce : ucx;
+    ucv = ucx;
+  }
+#pragma omp atomic compare capture acq_rel
+  {
+    ucx = ucx < uce ? uce : ucx;
+    ucv = ucx;
+  }
+#pragma omp atomic compare capture acq_rel
+  {
+    ucx = ucx == uce ? ucd : ucx;
+    ucv = ucx;
+  }
+
+#pragma omp atomic compare capture acquire
+  {
+    ucv = ucx;
+    ucx = ucx > uce ? uce : ucx;
+  }
+#pragma omp atomic compare capture acquire
+  {
+    ucv = ucx;
+    ucx = ucx < uce ? uce : ucx;
+  }
+#pragma omp atomic compare capture acquire
+  {
+    ucv = ucx;
+    ucx = ucx == uce ? ucd : ucx;
+  }
+#pragma omp atomic compare capture acquire
+  {
+    ucx = ucx > uce ? uce : ucx;
+    ucv = ucx;
+  }
+#pragma omp atomic compare capture acquire
+  {
+    ucx = ucx < uce ? uce : ucx;
+    ucv = ucx;
+  }
+#pragma omp atomic compare capture acquire
+  {
+    ucx = ucx == uce ? ucd : ucx;
+    ucv = ucx;
+  }
+
+#pragma omp atomic compare capture relaxed
+  {
+    ucv = ucx;
+    ucx = ucx > uce ? uce : ucx;
+  }
+#pragma omp atomic compare capture relaxed
+  {
+    ucv = ucx;
+    ucx = ucx < uce ? uce : ucx;
+  }
+#pragma omp atomic compare capture relaxed
+  {
+    ucv = ucx;
+    ucx = ucx == uce ? ucd : ucx;
+  }
+#pragma omp atomic compare capture relaxed
+  {
+    ucx = ucx > uce ? uce : ucx;
+    ucv = ucx;
+  }
+#pragma omp atomic compare capture relaxed
+  {
+    ucx = ucx < uce ? uce : ucx;
+    ucv = ucx;
+  }
+#pragma omp atomic compare capture relaxed
+  {
+    ucx = ucx == uce ? ucd : ucx;
+    ucv = ucx;
+  }
+
+#pragma omp atomic compare capture release
+  {
+    ucv = ucx;
+    ucx = ucx > uce ? uce : ucx;
+  }
+#pragma omp atomic compare capture release
+  {
+    ucv = ucx;
+    ucx = ucx < uce ? uce : ucx;
+  }
+#pragma omp atomic compare capture release
+  {
+    ucv = ucx;
+    ucx = ucx == uce ? ucd : ucx;
+  }
+#pragma omp atomic compare capture release
+  {
+    ucx = ucx > uce ? uce : ucx;
+    ucv = ucx;
+  }
+#pragma omp atomic compare capture release
+  {
+    ucx = ucx < uce ? uce : ucx;
+    ucv = ucx;
+  }
+#pragma omp atomic compare capture release
+  {
+    ucx = ucx == uce ? ucd : ucx;
+    ucv = ucx;
+  }
+
+#pragma omp atomic compare capture seq_cst
+  {
+    ucv = ucx;
+    ucx = ucx > uce ? uce : ucx;
+  }
+#pragma omp atomic compare capture seq_cst
+  {
+    ucv = ucx;
+    ucx = ucx < uce ? uce : ucx;
+  }
+#pragma omp atomic compare capture seq_cst
+  {
+    ucv = ucx;
+    ucx = ucx == uce ? ucd : ucx;
+  }
+#pragma omp atomic compare capture seq_cst
+  {
+    ucx = ucx > uce ? uce : ucx;
+    ucv = ucx;
+  }
+#pragma omp atomic compare capture seq_cst
+  {
+    ucx = ucx < uce ? uce : ucx;
+    ucv = ucx;
+  }
+#pragma omp atomic compare capture seq_cst
+  {
+    ucx = ucx == uce ? ucd : ucx;
+    ucv = ucx;
+  }
+
+  return ucv;
+}
+
+short sxevd() {
+  short sx, sv, se, sd;
+
+#pragma omp atomic compare capture
+  {
+    sv = sx;
+    sx = sx > se ? se : sx;
+  }
+#pragma omp atomic compare capture
+  {
+    sv = sx;
+    sx = sx < se ? se : sx;
+  }
+#pragma omp atomic compare capture
+  {
+    sv = sx;
+    sx = sx == se ? sd : sx;
+  }
+#pragma omp atomic compare capture
+  {
+    sx = sx > se ? se : sx;
+    sv = sx;
+  }
+#pragma omp atomic compare capture
+  {
+    sx = sx < se ? se : sx;
+    sv = sx;
+  }
+#pragma omp atomic compare capture
+  {
+    sx = sx == se ? sd : sx;
+    sv = sx;
+  }
+
+#pragma omp atomic compare capture acq_rel
+  {
+    sv = sx;
+    sx = sx > se ? se : sx;
+  }
+#pragma omp atomic compare capture acq_rel
+  {
+    sv = sx;
+    sx = sx < se ? se : sx;
+  }
+#pragma omp atomic compare capture acq_rel
+  {
+    sv = sx;
+    sx = sx == se ? sd : sx;
+  }
+#pragma omp atomic compare capture acq_rel
+  {
+    sx = sx > se ? se : sx;
+    sv = sx;
+  }
+#pragma omp atomic compare capture acq_rel
+  {
+    sx = sx < se ? se : sx;
+    sv = sx;
+  }
+#pragma omp atomic compare capture acq_rel
+  {
+    sx = sx == se ? sd : sx;
+    sv = sx;
+  }
+
+#pragma omp atomic compare capture acquire
+  {
+    sv = sx;
+    sx = sx > se ? se : sx;
+  }
+#pragma omp atomic compare capture acquire
+  {
+    sv = sx;
+    sx = sx < se ? se : sx;
+  }
+#pragma omp atomic compare capture acquire
+  {
+    sv = sx;
+    sx = sx == se ? sd : sx;
+  }
+#pragma omp atomic compare capture acquire
+  {
+    sx = sx > se ? se : sx;
+    sv = sx;
+  }
+#pragma omp atomic compare capture acquire
+  {
+    sx = sx < se ? se : sx;
+    sv = sx;
+  }
+#pragma omp atomic compare capture acquire
+  {
+    sx = sx == se ? sd : sx;
+    sv = sx;
+  }
+
+#pragma omp atomic compare capture relaxed
+  {
+    sv = sx;
+    sx = sx > se ? se : sx;
+  }
+#pragma omp atomic compare capture relaxed
+  {
+    sv = sx;
+    sx = sx < se ? se : sx;
+  }
+#pragma omp atomic compare capture relaxed
+  {
+    sv = sx;
+    sx = sx == se ? sd : sx;
+  }
+#pragma omp atomic compare capture relaxed
+  {
+    sx = sx > se ? se : sx;
+    sv = sx;
+  }
+#pragma omp atomic compare capture relaxed
+  {
+    sx = sx < se ? se : sx;
+    sv = sx;
+  }
+#pragma omp atomic compare capture relaxed
+  {
+    sx = sx == se ? sd : sx;
+    sv = sx;
+  }
+
+#pragma omp atomic compare capture release
+  {
+    sv = sx;
+    sx = sx > se ? se : sx;
+  }
+#pragma omp atomic compare capture release
+  {
+    sv = sx;
+    sx = sx < se ? se : sx;
+  }
+#pragma omp atomic compare capture release
+  {
+    sv = sx;
+    sx = sx == se ? sd : sx;
+  }
+#pragma omp atomic compare capture release
+  {
+    sx = sx > se ? se : sx;
+    sv = sx;
+  }
+#pragma omp atomic compare capture release
+  {
+    sx = sx < se ? se : sx;
+    sv = sx;
+  }
+#pragma omp atomic compare capture release
+  {
+    sx = sx == se ? sd : sx;
+    sv = sx;
+  }
+
+#pragma omp atomic compare capture seq_cst
+  {
+    sv = sx;
+    sx = sx > se ? se : sx;
+  }
+#pragma omp atomic compare capture seq_cst
+  {
+    sv = sx;
+    sx = sx < se ? se : sx;
+  }
+#pragma omp atomic compare capture seq_cst
+  {
+    sv = sx;
+    sx = sx == se ? sd : sx;
+  }
+#pragma omp atomic compare capture seq_cst
+  {
+    sx = sx > se ? se : sx;
+    sv = sx;
+  }
+#pragma omp atomic compare capture seq_cst
+  {
+    sx = sx < se ? se : sx;
+    sv = sx;
+  }
+#pragma omp atomic compare capture seq_cst
+  {
+    sx = sx == se ? sd : sx;
+    sv = sx;
+  }
+
+  return sv;
+}
+
+unsigned short usxevd() {
+  unsigned short usx, usv, use, usd;
+
+#pragma omp atomic compare capture
+  {
+    usv = usx;
+    usx = usx > use ? use : usx;
+  }
+#pragma omp atomic compare capture
+  {
+    usv = usx;
+    usx = usx < use ? use : usx;
+  }
+#pragma omp atomic compare capture
+  {
+    usv = usx;
+    usx = usx == use ? usd : usx;
+  }
+#pragma omp atomic compare capture
+  {
+    usx = usx > use ? use : usx;
+    usv = usx;
+  }
+#pragma omp atomic compare capture
+  {
+    usx = usx < use ? use : usx;
+    usv = usx;
+  }
+#pragma omp atomic compare capture
+  {
+    usx = usx == use ? usd : usx;
+    usv = usx;
+  }
+
+#pragma omp atomic compare capture acq_rel
+  {
+    usv = usx;
+    usx = usx > use ? use : usx;
+  }
+#pragma omp atomic compare capture acq_rel
+  {
+    usv = usx;
+    usx = usx < use ? use : usx;
+  }
+#pragma omp atomic compare capture acq_rel
+  {
+    usv = usx;
+    usx = usx == use ? usd : usx;
+  }
+#pragma omp atomic compare capture acq_rel
+  {
+    usx = usx > use ? use : usx;
+    usv = usx;
+  }
+#pragma omp atomic compare capture acq_rel
+  {
+    usx = usx < use ? use : usx;
+    usv = usx;
+  }
+#pragma omp atomic compare capture acq_rel
+  {
+    usx = usx == use ? usd : usx;
+    usv = usx;
+  }
+
+#pragma omp atomic compare capture acquire
+  {
+    usv = usx;
+    usx = usx > use ? use : usx;
+  }
+#pragma omp atomic compare capture acquire
+  {
+    usv = usx;
+    usx = usx < use ? use : usx;
+  }
+#pragma omp atomic compare capture acquire
+  {
+    usv = usx;
+    usx = usx == use ? usd : usx;
+  }
+#pragma omp atomic compare capture acquire
+  {
+    usx = usx > use ? use : usx;
+    usv = usx;
+  }
+#pragma omp atomic compare capture acquire
+  {
+    usx = usx < use ? use : usx;
+    usv = usx;
+  }
+#pragma omp atomic compare capture acquire
+  {
+    usx = usx == use ? usd : usx;
+    usv = usx;
+  }
+
+#pragma omp atomic compare capture relaxed
+  {
+    usv = usx;
+    usx = usx > use ? use : usx;
+  }
+#pragma omp atomic compare capture relaxed
+  {
+    usv = usx;
+    usx = usx < use ? use : usx;
+  }
+#pragma omp atomic compare capture relaxed
+  {
+    usv = usx;
+    usx = usx == use ? usd : usx;
+  }
+#pragma omp atomic compare capture relaxed
+  {
+    usx = usx > use ? use : usx;
+    usv = usx;
+  }
+#pragma omp atomic compare capture relaxed
+  {
+    usx = usx < use ? use : usx;
+    usv = usx;
+  }
+#pragma omp atomic compare capture relaxed
+  {
+    usx = usx == use ? usd : usx;
+    usv = usx;
+  }
+
+#pragma omp atomic compare capture release
+  {
+    usv = usx;
+    usx = usx > use ? use : usx;
+  }
+#pragma omp atomic compare capture release
+  {
+    usv = usx;
+    usx = usx < use ? use : usx;
+  }
+#pragma omp atomic compare capture release
+  {
+    usv = usx;
+    usx = usx == use ? usd : usx;
+  }
+#pragma omp atomic compare capture release
+  {
+    usx = usx > use ? use : usx;
+    usv = usx;
+  }
+#pragma omp atomic compare capture release
+  {
+    usx = usx < use ? use : usx;
+    usv = usx;
+  }
+#pragma omp atomic compare capture release
+  {
+    usx = usx == use ? usd : usx;
+    usv = usx;
+  }
+
+#pragma omp atomic compare capture seq_cst
+  {
+    usv = usx;
+    usx = usx > use ? use : usx;
+  }
+#pragma omp atomic compare capture seq_cst
+  {
+    usv = usx;
+    usx = usx < use ? use : usx;
+  }
+#pragma omp atomic compare capture seq_cst
+  {
+    usv = usx;
+    usx = usx == use ? usd : usx;
+  }
+#pragma omp atomic compare capture seq_cst
+  {
+    usx = usx > use ? use : usx;
+    usv = usx;
+  }
+#pragma omp atomic compare capture seq_cst
+  {
+    usx = usx < use ? use : usx;
+    usv = usx;
+  }
+#pragma omp atomic compare capture seq_cst
+  {
+    usx = usx == use ? usd : usx;
+    usv = usx;
+  }
+
+  return usv;
+}
+
+int ixevd() {
+  int ix, iv, ie, id;
+
+#pragma omp atomic compare capture
+  {
+    iv = ix;
+    ix = ix > ie ? ie : ix;
+  }
+#pragma omp atomic compare capture
+  {
+    iv = ix;
+    ix = ix < ie ? ie : ix;
+  }
+#pragma omp atomic compare capture
+  {
+    iv = ix;
+    ix = ix == ie ? id : ix;
+  }
+#pragma omp atomic compare capture
+  {
+    ix = ix > ie ? ie : ix;
+    iv = ix;
+  }
+#pragma omp atomic compare capture
+  {
+    ix = ix < ie ? ie : ix;
+    iv = ix;
+  }
+#pragma omp atomic compare capture
+  {
+    ix = ix == ie ? id : ix;
+    iv = ix;
+  }
+
+#pragma omp atomic compare capture acq_rel
+  {
+    iv = ix;
+    ix = ix > ie ? ie : ix;
+  }
+#pragma omp atomic compare capture acq_rel
+  {
+    iv = ix;
+    ix = ix < ie ? ie : ix;
+  }
+#pragma omp atomic compare capture acq_rel
+  {
+    iv = ix;
+    ix = ix == ie ? id : ix;
+  }
+#pragma omp atomic compare capture acq_rel
+  {
+    ix = ix > ie ? ie : ix;
+    iv = ix;
+  }
+#pragma omp atomic compare capture acq_rel
+  {
+    ix = ix < ie ? ie : ix;
+    iv = ix;
+  }
+#pragma omp atomic compare capture acq_rel
+  {
+    ix = ix == ie ? id : ix;
+    iv = ix;
+  }
+
+#pragma omp atomic compare capture acquire
+  {
+    iv = ix;
+    ix = ix > ie ? ie : ix;
+  }
+#pragma omp atomic compare capture acquire
+  {
+    iv = ix;
+    ix = ix < ie ? ie : ix;
+  }
+#pragma omp atomic compare capture acquire
+  {
+    iv = ix;
+    ix = ix == ie ? id : ix;
+  }
+#pragma omp atomic compare capture acquire
+  {
+    ix = ix > ie ? ie : ix;
+    iv = ix;
+  }
+#pragma omp atomic compare capture acquire
+  {
+    ix = ix < ie ? ie : ix;
+    iv = ix;
+  }
+#pragma omp atomic compare capture acquire
+  {
+    ix = ix == ie ? id : ix;
+    iv = ix;
+  }
+
+#pragma omp atomic compare capture relaxed
+  {
+    iv = ix;
+    ix = ix > ie ? ie : ix;
+  }
+#pragma omp atomic compare capture relaxed
+  {
+    iv = ix;
+    ix = ix < ie ? ie : ix;
+  }
+#pragma omp atomic compare capture relaxed
+  {
+    iv = ix;
+    ix = ix == ie ? id : ix;
+  }
+#pragma omp atomic compare capture relaxed
+  {
+    ix = ix > ie ? ie : ix;
+    iv = ix;
+  }
+#pragma omp atomic compare capture relaxed
+  {
+    ix = ix < ie ? ie : ix;
+    iv = ix;
+  }
+#pragma omp atomic compare capture relaxed
+  {
+    ix = ix == ie ? id : ix;
+    iv = ix;
+  }
+
+#pragma omp atomic compare capture release
+  {
+    iv = ix;
+    ix = ix > ie ? ie : ix;
+  }
+#pragma omp atomic compare capture release
+  {
+    iv = ix;
+    ix = ix < ie ? ie : ix;
+  }
+#pragma omp atomic compare capture release
+  {
+    iv = ix;
+    ix = ix == ie ? id : ix;
+  }
+#pragma omp atomic compare capture release
+  {
+    ix = ix > ie ? ie : ix;
+    iv = ix;
+  }
+#pragma omp atomic compare capture release
+  {
+    ix = ix < ie ? ie : ix;
+    iv = ix;
+  }
+#pragma omp atomic compare capture release
+  {
+    ix = ix == ie ? id : ix;
+    iv = ix;
+  }
+
+#pragma omp atomic compare capture seq_cst
+  {
+    iv = ix;
+    ix = ix > ie ? ie : ix;
+  }
+#pragma omp atomic compare capture seq_cst
+  {
+    iv = ix;
+    ix = ix < ie ? ie : ix;
+  }
+#pragma omp atomic compare capture seq_cst
+  {
+    iv = ix;
+    ix = ix == ie ? id : ix;
+  }
+#pragma omp atomic compare capture seq_cst
+  {
+    ix = ix > ie ? ie : ix;
+    iv = ix;
+  }
+#pragma omp atomic compare capture seq_cst
+  {
+    ix = ix < ie ? ie : ix;
+    iv = ix;
+  }
+#pragma omp atomic compare capture seq_cst
+  {
+    ix = ix == ie ? id : ix;
+    iv = ix;
+  }
+
+  return iv;
+}
+
+unsigned int uixevd() {
+  unsigned int uix, uiv, uie, uid;
+
+#pragma omp atomic compare capture
+  {
+    uiv = uix;
+    uix = uix > uie ? uie : uix;
+  }
+#pragma omp atomic compare capture
+  {
+    uiv = uix;
+    uix = uix < uie ? uie : uix;
+  }
+#pragma omp atomic compare capture
+  {
+    uiv = uix;
+    uix = uix == uie ? uid : uix;
+  }
+#pragma omp atomic compare capture
+  {
+    uix = uix > uie ? uie : uix;
+    uiv = uix;
+  }
+#pragma omp atomic compare capture
+  {
+    uix = uix < uie ? uie : uix;
+    uiv = uix;
+  }
+#pragma omp atomic compare capture
+  {
+    uix = uix == uie ? uid : uix;
+    uiv = uix;
+  }
+
+#pragma omp atomic compare capture acq_rel
+  {
+    uiv = uix;
+    uix = uix > uie ? uie : uix;
+  }
+#pragma omp atomic compare capture acq_rel
+  {
+    uiv = uix;
+    uix = uix < uie ? uie : uix;
+  }
+#pragma omp atomic compare capture acq_rel
+  {
+    uiv = uix;
+    uix = uix == uie ? uid : uix;
+  }
+#pragma omp atomic compare capture acq_rel
+  {
+    uix = uix > uie ? uie : uix;
+    uiv = uix;
+  }
+#pragma omp atomic compare capture acq_rel
+  {
+    uix = uix < uie ? uie : uix;
+    uiv = uix;
+  }
+#pragma omp atomic compare capture acq_rel
+  {
+    uix = uix == uie ? uid : uix;
+    uiv = uix;
+  }
+
+#pragma omp atomic compare capture acquire
+  {
+    uiv = uix;
+    uix = uix > uie ? uie : uix;
+  }
+#pragma omp atomic compare capture acquire
+  {
+    uiv = uix;
+    uix = uix < uie ? uie : uix;
+  }
+#pragma omp atomic compare capture acquire
+  {
+    uiv = uix;
+    uix = uix == uie ? uid : uix;
+  }
+#pragma omp atomic compare capture acquire
+  {
+    uix = uix > uie ? uie : uix;
+    uiv = uix;
+  }
+#pragma omp atomic compare capture acquire
+  {
+    uix = uix < uie ? uie : uix;
+    uiv = uix;
+  }
+#pragma omp atomic compare capture acquire
+  {
+    uix = uix == uie ? uid : uix;
+    uiv = uix;
+  }
+
+#pragma omp atomic compare capture relaxed
+  {
+    uiv = uix;
+    uix = uix > uie ? uie : uix;
+  }
+#pragma omp atomic compare capture relaxed
+  {
+    uiv = uix;
+    uix = uix < uie ? uie : uix;
+  }
+#pragma omp atomic compare capture relaxed
+  {
+    uiv = uix;
+    uix = uix == uie ? uid : uix;
+  }
+#pragma omp atomic compare capture relaxed
+  {
+    uix = uix > uie ? uie : uix;
+    uiv = uix;
+  }
+#pragma omp atomic compare capture relaxed
+  {
+    uix = uix < uie ? uie : uix;
+    uiv = uix;
+  }
+#pragma omp atomic compare capture relaxed
+  {
+    uix = uix == uie ? uid : uix;
+    uiv = uix;
+  }
+
+#pragma omp atomic compare capture release
+  {
+    uiv = uix;
+    uix = uix > uie ? uie : uix;
+  }
+#pragma omp atomic compare capture release
+  {
+    uiv = uix;
+    uix = uix < uie ? uie : uix;
+  }
+#pragma omp atomic compare capture release
+  {
+    uiv = uix;
+    uix = uix == uie ? uid : uix;
+  }
+#pragma omp atomic compare capture release
+  {
+    uix = uix > uie ? uie : uix;
+    uiv = uix;
+  }
+#pragma omp atomic compare capture release
+  {
+    uix = uix < uie ? uie : uix;
+    uiv = uix;
+  }
+#pragma omp atomic compare capture release
+  {
+    uix = uix == uie ? uid : uix;
+    uiv = uix;
+  }
+
+#pragma omp atomic compare capture seq_cst
+  {
+    uiv = uix;
+    uix = uix > uie ? uie : uix;
+  }
+#pragma omp atomic compare capture seq_cst
+  {
+    uiv = uix;
+    uix = uix < uie ? uie : uix;
+  }
+#pragma omp atomic compare capture seq_cst
+  {
+    uiv = uix;
+    uix = uix == uie ? uid : uix;
+  }
+#pragma omp atomic compare capture seq_cst
+  {
+    uix = uix > uie ? uie : uix;
+    uiv = uix;
+  }
+#pragma omp atomic compare capture seq_cst
+  {
+    uix = uix < uie ? uie : uix;
+    uiv = uix;
+  }
+#pragma omp atomic compare capture seq_cst
+  {
+    uix = uix == uie ? uid : uix;
+    uiv = uix;
+  }
+
+  return uiv;
+}
+
+long lxevd() {
+  long lx, lv, le, ld;
+
+#pragma omp atomic compare capture
+  {
+    lv = lx;
+    lx = lx > le ? le : lx;
+  }
+#pragma omp atomic compare capture
+  {
+    lv = lx;
+    lx = lx < le ? le : lx;
+  }
+#pragma omp atomic compare capture
+  {
+    lv = lx;
+    lx = lx == le ? ld : lx;
+  }
+#pragma omp atomic compare capture
+  {
+    lx = lx > le ? le : lx;
+    lv = lx;
+  }
+#pragma omp atomic compare capture
+  {
+    lx = lx < le ? le : lx;
+    lv = lx;
+  }
+#pragma omp atomic compare capture
+  {
+    lx = lx == le ? ld : lx;
+    lv = lx;
+  }
+
+#pragma omp atomic compare capture acq_rel
+  {
+    lv = lx;
+    lx = lx > le ? le : lx;
+  }
+#pragma omp atomic compare capture acq_rel
+  {
+    lv = lx;
+    lx = lx < le ? le : lx;
+  }
+#pragma omp atomic compare capture acq_rel
+  {
+    lv = lx;
+    lx = lx == le ? ld : lx;
+  }
+#pragma omp atomic compare capture acq_rel
+  {
+    lx = lx > le ? le : lx;
+    lv = lx;
+  }
+#pragma omp atomic compare capture acq_rel
+  {
+    lx = lx < le ? le : lx;
+    lv = lx;
+  }
+#pragma omp atomic compare capture acq_rel
+  {
+    lx = lx == le ? ld : lx;
+    lv = lx;
+  }
+
+#pragma omp atomic compare capture acquire
+  {
+    lv = lx;
+    lx = lx > le ? le : lx;
+  }
+#pragma omp atomic compare capture acquire
+  {
+    lv = lx;
+    lx = lx < le ? le : lx;
+  }
+#pragma omp atomic compare capture acquire
+  {
+    lv = lx;
+    lx = lx == le ? ld : lx;
+  }
+#pragma omp atomic compare capture acquire
+  {
+    lx = lx > le ? le : lx;
+    lv = lx;
+  }
+#pragma omp atomic compare capture acquire
+  {
+    lx = lx < le ? le : lx;
+    lv = lx;
+  }
+#pragma omp atomic compare capture acquire
+  {
+    lx = lx == le ? ld : lx;
+    lv = lx;
+  }
+
+#pragma omp atomic compare capture relaxed
+  {
+    lv = lx;
+    lx = lx > le ? le : lx;
+  }
+#pragma omp atomic compare capture relaxed
+  {
+    lv = lx;
+    lx = lx < le ? le : lx;
+  }
+#pragma omp atomic compare capture relaxed
+  {
+    lv = lx;
+    lx = lx == le ? ld : lx;
+  }
+#pragma omp atomic compare capture relaxed
+  {
+    lx = lx > le ? le : lx;
+    lv = lx;
+  }
+#pragma omp atomic compare capture relaxed
+  {
+    lx = lx < le ? le : lx;
+    lv = lx;
+  }
+#pragma omp atomic compare capture relaxed
+  {
+    lx = lx == le ? ld : lx;
+    lv = lx;
+  }
+
+#pragma omp atomic compare capture release
+  {
+    lv = lx;
+    lx = lx > le ? le : lx;
+  }
+#pragma omp atomic compare capture release
+  {
+    lv = lx;
+    lx = lx < le ? le : lx;
+  }
+#pragma omp atomic compare capture release
+  {
+    lv = lx;
+    lx = lx == le ? ld : lx;
+  }
+#pragma omp atomic compare capture release
+  {
+    lx = lx > le ? le : lx;
+    lv = lx;
+  }
+#pragma omp atomic compare capture release
+  {
+    lx = lx < le ? le : lx;
+    lv = lx;
+  }
+#pragma omp atomic compare capture release
+  {
+    lx = lx == le ? ld : lx;
+    lv = lx;
+  }
+
+#pragma omp atomic compare capture seq_cst
+  {
+    lv = lx;
+    lx = lx > le ? le : lx;
+  }
+#pragma omp atomic compare capture seq_cst
+  {
+    lv = lx;
+    lx = lx < le ? le : lx;
+  }
+#pragma omp atomic compare capture seq_cst
+  {
+    lv = lx;
+    lx = lx == le ? ld : lx;
+  }
+#pragma omp atomic compare capture seq_cst
+  {
+    lx = lx > le ? le : lx;
+    lv = lx;
+  }
+#pragma omp atomic compare capture seq_cst
+  {
+    lx = lx < le ? le : lx;
+    lv = lx;
+  }
+#pragma omp atomic compare capture seq_cst
+  {
+    lx = lx == le ? ld : lx;
+    lv = lx;
+  }
+
+  return lv;
+}
+
+unsigned long ulxevd() {
+  unsigned long ulx, ulv, ule, uld;
+
+#pragma omp atomic compare capture
+  {
+    ulv = ulx;
+    ulx = ulx > ule ? ule : ulx;
+  }
+#pragma omp atomic compare capture
+  {
+    ulv = ulx;
+    ulx = ulx < ule ? ule : ulx;
+  }
+#pragma omp atomic compare capture
+  {
+    ulv = ulx;
+    ulx = ulx == ule ? uld : ulx;
+  }
+#pragma omp atomic compare capture
+  {
+    ulx = ulx > ule ? ule : ulx;
+    ulv = ulx;
+  }
+#pragma omp atomic compare capture
+  {
+    ulx = ulx < ule ? ule : ulx;
+    ulv = ulx;
+  }
+#pragma omp atomic compare capture
+  {
+    ulx = ulx == ule ? uld : ulx;
+    ulv = ulx;
+  }
+
+#pragma omp atomic compare capture acq_rel
+  {
+    ulv = ulx;
+    ulx = ulx > ule ? ule : ulx;
+  }
+#pragma omp atomic compare capture acq_rel
+  {
+    ulv = ulx;
+    ulx = ulx < ule ? ule : ulx;
+  }
+#pragma omp atomic compare capture acq_rel
+  {
+    ulv = ulx;
+    ulx = ulx == ule ? uld : ulx;
+  }
+#pragma omp atomic compare capture acq_rel
+  {
+    ulx = ulx > ule ? ule : ulx;
+    ulv = ulx;
+  }
+#pragma omp atomic compare capture acq_rel
+  {
+    ulx = ulx < ule ? ule : ulx;
+    ulv = ulx;
+  }
+#pragma omp atomic compare capture acq_rel
+  {
+    ulx = ulx == ule ? uld : ulx;
+    ulv = ulx;
+  }
+
+#pragma omp atomic compare capture acquire
+  {
+    ulv = ulx;
+    ulx = ulx > ule ? ule : ulx;
+  }
+#pragma omp atomic compare capture acquire
+  {
+    ulv = ulx;
+    ulx = ulx < ule ? ule : ulx;
+  }
+#pragma omp atomic compare capture acquire
+  {
+    ulv = ulx;
+    ulx = ulx == ule ? uld : ulx;
+  }
+#pragma omp atomic compare capture acquire
+  {
+    ulx = ulx > ule ? ule : ulx;
+    ulv = ulx;
+  }
+#pragma omp atomic compare capture acquire
+  {
+    ulx = ulx < ule ? ule : ulx;
+    ulv = ulx;
+  }
+#pragma omp atomic compare capture acquire
+  {
+    ulx = ulx == ule ? uld : ulx;
+    ulv = ulx;
+  }
+
+#pragma omp atomic compare capture relaxed
+  {
+    ulv = ulx;
+    ulx = ulx > ule ? ule : ulx;
+  }
+#pragma omp atomic compare capture relaxed
+  {
+    ulv = ulx;
+    ulx = ulx < ule ? ule : ulx;
+  }
+#pragma omp atomic compare capture relaxed
+  {
+    ulv = ulx;
+    ulx = ulx == ule ? uld : ulx;
+  }
+#pragma omp atomic compare capture relaxed
+  {
+    ulx = ulx > ule ? ule : ulx;
+    ulv = ulx;
+  }
+#pragma omp atomic compare capture relaxed
+  {
+    ulx = ulx < ule ? ule : ulx;
+    ulv = ulx;
+  }
+#pragma omp atomic compare capture relaxed
+  {
+    ulx = ulx == ule ? uld : ulx;
+    ulv = ulx;
+  }
+
+#pragma omp atomic compare capture release
+  {
+    ulv = ulx;
+    ulx = ulx > ule ? ule : ulx;
+  }
+#pragma omp atomic compare capture release
+  {
+    ulv = ulx;
+    ulx = ulx < ule ? ule : ulx;
+  }
+#pragma omp atomic compare capture release
+  {
+    ulv = ulx;
+    ulx = ulx == ule ? uld : ulx;
+  }
+#pragma omp atomic compare capture release
+  {
+    ulx = ulx > ule ? ule : ulx;
+    ulv = ulx;
+  }
+#pragma omp atomic compare capture release
+  {
+    ulx = ulx < ule ? ule : ulx;
+    ulv = ulx;
+  }
+#pragma omp atomic compare capture release
+  {
+    ulx = ulx == ule ? uld : ulx;
+    ulv = ulx;
+  }
+
+#pragma omp atomic compare capture seq_cst
+  {
+    ulv = ulx;
+    ulx = ulx > ule ? ule : ulx;
+  }
+#pragma omp atomic compare capture seq_cst
+  {
+    ulv = ulx;
+    ulx = ulx < ule ? ule : ulx;
+  }
+#pragma omp atomic compare capture seq_cst
+  {
+    ulv = ulx;
+    ulx = ulx == ule ? uld : ulx;
+  }
+#pragma omp atomic compare capture seq_cst
+  {
+    ulx = ulx > ule ? ule : ulx;
+    ulv = ulx;
+  }
+#pragma omp atomic compare capture seq_cst
+  {
+    ulx = ulx < ule ? ule : ulx;
+    ulv = ulx;
+  }
+#pragma omp atomic compare capture seq_cst
+  {
+    ulx = ulx == ule ? uld : ulx;
+    ulv = ulx;
+  }
+
+  return ulv;
+}
+
+long long llxevd() {
+  long long llx, llv, lle, lld;
+
+#pragma omp atomic compare capture
+  {
+    llv = llx;
+    llx = llx > lle ? lle : llx;
+  }
+#pragma omp atomic compare capture
+  {
+    llv = llx;
+    llx = llx < lle ? lle : llx;
+  }
+#pragma omp atomic compare capture
+  {
+    llv = llx;
+    llx = llx == lle ? lld : llx;
+  }
+#pragma omp atomic compare capture
+  {
+    llx = llx > lle ? lle : llx;
+    llv = llx;
+  }
+#pragma omp atomic compare capture
+  {
+    llx = llx < lle ? lle : llx;
+    llv = llx;
+  }
+#pragma omp atomic compare capture
+  {
+    llx = llx == lle ? lld : llx;
+    llv = llx;
+  }
+
+#pragma omp atomic compare capture acq_rel
+  {
+    llv = llx;
+    llx = llx > lle ? lle : llx;
+  }
+#pragma omp atomic compare capture acq_rel
+  {
+    llv = llx;
+    llx = llx < lle ? lle : llx;
+  }
+#pragma omp atomic compare capture acq_rel
+  {
+    llv = llx;
+    llx = llx == lle ? lld : llx;
+  }
+#pragma omp atomic compare capture acq_rel
+  {
+    llx = llx > lle ? lle : llx;
+    llv = llx;
+  }
+#pragma omp atomic compare capture acq_rel
+  {
+    llx = llx < lle ? lle : llx;
+    llv = llx;
+  }
+#pragma omp atomic compare capture acq_rel
+  {
+    llx = llx == lle ? lld : llx;
+    llv = llx;
+  }
+
+#pragma omp atomic compare capture acquire
+  {
+    llv = llx;
+    llx = llx > lle ? lle : llx;
+  }
+#pragma omp atomic compare capture acquire
+  {
+    llv = llx;
+    llx = llx < lle ? lle : llx;
+  }
+#pragma omp atomic compare capture acquire
+  {
+    llv = llx;
+    llx = llx == lle ? lld : llx;
+  }
+#pragma omp atomic compare capture acquire
+  {
+    llx = llx > lle ? lle : llx;
+    llv = llx;
+  }
+#pragma omp atomic compare capture acquire
+  {
+    llx = llx < lle ? lle : llx;
+    llv = llx;
+  }
+#pragma omp atomic compare capture acquire
+  {
+    llx = llx == lle ? lld : llx;
+    llv = llx;
+  }
+
+#pragma omp atomic compare capture relaxed
+  {
+    llv = llx;
+    llx = llx > lle ? lle : llx;
+  }
+#pragma omp atomic compare capture relaxed
+  {
+    llv = llx;
+    llx = llx < lle ? lle : llx;
+  }
+#pragma omp atomic compare capture relaxed
+  {
+    llv = llx;
+    llx = llx == lle ? lld : llx;
+  }
+#pragma omp atomic compare capture relaxed
+  {
+    llx = llx > lle ? lle : llx;
+    llv = llx;
+  }
+#pragma omp atomic compare capture relaxed
+  {
+    llx = llx < lle ? lle : llx;
+    llv = llx;
+  }
+#pragma omp atomic compare capture relaxed
+  {
+    llx = llx == lle ? lld : llx;
+    llv = llx;
+  }
+
+#pragma omp atomic compare capture release
+  {
+    llv = llx;
+    llx = llx > lle ? lle : llx;
+  }
+#pragma omp atomic compare capture release
+  {
+    llv = llx;
+    llx = llx < lle ? lle : llx;
+  }
+#pragma omp atomic compare capture release
+  {
+    llv = llx;
+    llx = llx == lle ? lld : llx;
+  }
+#pragma omp atomic compare capture release
+  {
+    llx = llx > lle ? lle : llx;
+    llv = llx;
+  }
+#pragma omp atomic compare capture release
+  {
+    llx = llx < lle ? lle : llx;
+    llv = llx;
+  }
+#pragma omp atomic compare capture release
+  {
+    llx = llx == lle ? lld : llx;
+    llv = llx;
+  }
+
+#pragma omp atomic compare capture seq_cst
+  {
+    llv = llx;
+    llx = llx > lle ? lle : llx;
+  }
+#pragma omp atomic compare capture seq_cst
+  {
+    llv = llx;
+    llx = llx < lle ? lle : llx;
+  }
+#pragma omp atomic compare capture seq_cst
+  {
+    llv = llx;
+    llx = llx == lle ? lld : llx;
+  }
+#pragma omp atomic compare capture seq_cst
+  {
+    llx = llx > lle ? lle : llx;
+    llv = llx;
+  }
+#pragma omp atomic compare capture seq_cst
+  {
+    llx = llx < lle ? lle : llx;
+    llv = llx;
+  }
+#pragma omp atomic compare capture seq_cst
+  {
+    llx = llx == lle ? lld : llx;
+    llv = llx;
+  }
+
+  return llv;
+}
+
+unsigned long long ullxevd() {
+  unsigned long long ullx, ullv, ulle, ulld;
+
+#pragma omp atomic compare capture
+  {
+    ullv = ullx;
+    ullx = ullx > ulle ? ulle : ullx;
+  }
+#pragma omp atomic compare capture
+  {
+    ullv = ullx;
+    ullx = ullx < ulle ? ulle : ullx;
+  }
+#pragma omp atomic compare capture
+  {
+    ullv = ullx;
+    ullx = ullx == ulle ? ulld : ullx;
+  }
+#pragma omp atomic compare capture
+  {
+    ullx = ullx > ulle ? ulle : ullx;
+    ullv = ullx;
+  }
+#pragma omp atomic compare capture
+  {
+    ullx = ullx < ulle ? ulle : ullx;
+    ullv = ullx;
+  }
+#pragma omp atomic compare capture
+  {
+    ullx = ullx == ulle ? ulld : ullx;
+    ullv = ullx;
+  }
+
+#pragma omp atomic compare capture acq_rel
+  {
+    ullv = ullx;
+    ullx = ullx > ulle ? ulle : ullx;
+  }
+#pragma omp atomic compare capture acq_rel
+  {
+    ullv = ullx;
+    ullx = ullx < ulle ? ulle : ullx;
+  }
+#pragma omp atomic compare capture acq_rel
+  {
+    ullv = ullx;
+    ullx = ullx == ulle ? ulld : ullx;
+  }
+#pragma omp atomic compare capture acq_rel
+  {
+    ullx = ullx > ulle ? ulle : ullx;
+    ullv = ullx;
+  }
+#pragma omp atomic compare capture acq_rel
+  {
+    ullx = ullx < ulle ? ulle : ullx;
+    ullv = ullx;
+  }
+#pragma omp atomic compare capture acq_rel
+  {
+    ullx = ullx == ulle ? ulld : ullx;
+    ullv = ullx;
+  }
+
+#pragma omp atomic compare capture acquire
+  {
+    ullv = ullx;
+    ullx = ullx > ulle ? ulle : ullx;
+  }
+#pragma omp atomic compare capture acquire
+  {
+    ullv = ullx;
+    ullx = ullx < ulle ? ulle : ullx;
+  }
+#pragma omp atomic compare capture acquire
+  {
+    ullv = ullx;
+    ullx = ullx == ulle ? ulld : ullx;
+  }
+#pragma omp atomic compare capture acquire
+  {
+    ullx = ullx > ulle ? ulle : ullx;
+    ullv = ullx;
+  }
+#pragma omp atomic compare capture acquire
+  {
+    ullx = ullx < ulle ? ulle : ullx;
+    ullv = ullx;
+  }
+#pragma omp atomic compare capture acquire
+  {
+    ullx = ullx == ulle ? ulld : ullx;
+    ullv = ullx;
+  }
+
+#pragma omp atomic compare capture relaxed
+  {
+    ullv = ullx;
+    ullx = ullx > ulle ? ulle : ullx;
+  }
+#pragma omp atomic compare capture relaxed
+  {
+    ullv = ullx;
+    ullx = ullx < ulle ? ulle : ullx;
+  }
+#pragma omp atomic compare capture relaxed
+  {
+    ullv = ullx;
+    ullx = ullx == ulle ? ulld : ullx;
+  }
+#pragma omp atomic compare capture relaxed
+  {
+    ullx = ullx > ulle ? ulle : ullx;
+    ullv = ullx;
+  }
+#pragma omp atomic compare capture relaxed
+  {
+    ullx = ullx < ulle ? ulle : ullx;
+    ullv = ullx;
+  }
+#pragma omp atomic compare capture relaxed
+  {
+    ullx = ullx == ulle ? ulld : ullx;
+    ullv = ullx;
+  }
+
+#pragma omp atomic compare capture release
+  {
+    ullv = ullx;
+    ullx = ullx > ulle ? ulle : ullx;
+  }
+#pragma omp atomic compare capture release
+  {
+    ullv = ullx;
+    ullx = ullx < ulle ? ulle : ullx;
+  }
+#pragma omp atomic compare capture release
+  {
+    ullv = ullx;
+    ullx = ullx == ulle ? ulld : ullx;
+  }
+#pragma omp atomic compare capture release
+  {
+    ullx = ullx > ulle ? ulle : ullx;
+    ullv = ullx;
+  }
+#pragma omp atomic compare capture release
+  {
+    ullx = ullx < ulle ? ulle : ullx;
+    ullv = ullx;
+  }
+#pragma omp atomic compare capture release
+  {
+    ullx = ullx == ulle ? ulld : ullx;
+    ullv = ullx;
+  }
+
+#pragma omp atomic compare capture seq_cst
+  {
+    ullv = ullx;
+    ullx = ullx > ulle ? ulle : ullx;
+  }
+#pragma omp atomic compare capture seq_cst
+  {
+    ullv = ullx;
+    ullx = ullx < ulle ? ulle : ullx;
+  }
+#pragma omp atomic compare capture seq_cst
+  {
+    ullv = ullx;
+    ullx = ullx == ulle ? ulld : ullx;
+  }
+#pragma omp atomic compare capture seq_cst
+  {
+    ullx = ullx > ulle ? ulle : ullx;
+    ullv = ullx;
+  }
+#pragma omp atomic compare capture seq_cst
+  {
+    ullx = ullx < ulle ? ulle : ullx;
+    ullv = ullx;
+  }
+#pragma omp atomic compare capture seq_cst
+  {
+    ullx = ullx == ulle ? ulld : ullx;
+    ullv = ullx;
+  }
+
+  return ullv;
+}
+
+float fxevd() {
+  float fx, fv, fe, fd;
+
+#pragma omp atomic compare capture
+  {
+    fv = fx;
+    fx = fx > fe ? fe : fx;
+  }
+#pragma omp atomic compare capture
+  {
+    fv = fx;
+    fx = fx < fe ? fe : fx;
+  }
+#pragma omp atomic compare capture
+  {
+    fv = fx;
+    fx = fx == fe ? fd : fx;
+  }
+#pragma omp atomic compare capture
+  {
+    fx = fx > fe ? fe : fx;
+    fv = fx;
+  }
+#pragma omp atomic compare capture
+  {
+    fx = fx < fe ? fe : fx;
+    fv = fx;
+  }
+#pragma omp atomic compare capture
+  {
+    fx = fx == fe ? fd : fx;
+    fv = fx;
+  }
+
+#pragma omp atomic compare capture acq_rel
+  {
+    fv = fx;
+    fx = fx > fe ? fe : fx;
+  }
+#pragma omp atomic compare capture acq_rel
+  {
+    fv = fx;
+    fx = fx < fe ? fe : fx;
+  }
+#pragma omp atomic compare capture acq_rel
+  {
+    fv = fx;
+    fx = fx == fe ? fd : fx;
+  }
+#pragma omp atomic compare capture acq_rel
+  {
+    fx = fx > fe ? fe : fx;
+    fv = fx;
+  }
+#pragma omp atomic compare capture acq_rel
+  {
+    fx = fx < fe ? fe : fx;
+    fv = fx;
+  }
+#pragma omp atomic compare capture acq_rel
+  {
+    fx = fx == fe ? fd : fx;
+    fv = fx;
+  }
+
+#pragma omp atomic compare capture acquire
+  {
+    fv = fx;
+    fx = fx > fe ? fe : fx;
+  }
+#pragma omp atomic compare capture acquire
+  {
+    fv = fx;
+    fx = fx < fe ? fe : fx;
+  }
+#pragma omp atomic compare capture acquire
+  {
+    fv = fx;
+    fx = fx == fe ? fd : fx;
+  }
+#pragma omp atomic compare capture acquire
+  {
+    fx = fx > fe ? fe : fx;
+    fv = fx;
+  }
+#pragma omp atomic compare capture acquire
+  {
+    fx = fx < fe ? fe : fx;
+    fv = fx;
+  }
+#pragma omp atomic compare capture acquire
+  {
+    fx = fx == fe ? fd : fx;
+    fv = fx;
+  }
+
+#pragma omp atomic compare capture relaxed
+  {
+    fv = fx;
+    fx = fx > fe ? fe : fx;
+  }
+#pragma omp atomic compare capture relaxed
+  {
+    fv = fx;
+    fx = fx < fe ? fe : fx;
+  }
+#pragma omp atomic compare capture relaxed
+  {
+    fv = fx;
+    fx = fx == fe ? fd : fx;
+  }
+#pragma omp atomic compare capture relaxed
+  {
+    fx = fx > fe ? fe : fx;
+    fv = fx;
+  }
+#pragma omp atomic compare capture relaxed
+  {
+    fx = fx < fe ? fe : fx;
+    fv = fx;
+  }
+#pragma omp atomic compare capture relaxed
+  {
+    fx = fx == fe ? fd : fx;
+    fv = fx;
+  }
+
+#pragma omp atomic compare capture release
+  {
+    fv = fx;
+    fx = fx > fe ? fe : fx;
+  }
+#pragma omp atomic compare capture release
+  {
+    fv = fx;
+    fx = fx < fe ? fe : fx;
+  }
+#pragma omp atomic compare capture release
+  {
+    fv = fx;
+    fx = fx == fe ? fd : fx;
+  }
+#pragma omp atomic compare capture release
+  {
+    fx = fx > fe ? fe : fx;
+    fv = fx;
+  }
+#pragma omp atomic compare capture release
+  {
+    fx = fx < fe ? fe : fx;
+    fv = fx;
+  }
+#pragma omp atomic compare capture release
+  {
+    fx = fx == fe ? fd : fx;
+    fv = fx;
+  }
+
+#pragma omp atomic compare capture seq_cst
+  {
+    fv = fx;
+    fx = fx > fe ? fe : fx;
+  }
+#pragma omp atomic compare capture seq_cst
+  {
+    fv = fx;
+    fx = fx < fe ? fe : fx;
+  }
+#pragma omp atomic compare capture seq_cst
+  {
+    fv = fx;
+    fx = fx == fe ? fd : fx;
+  }
+#pragma omp atomic compare capture seq_cst
+  {
+    fx = fx > fe ? fe : fx;
+    fv = fx;
+  }
+#pragma omp atomic compare capture seq_cst
+  {
+    fx = fx < fe ? fe : fx;
+    fv = fx;
+  }
+#pragma omp atomic compare capture seq_cst
+  {
+    fx = fx == fe ? fd : fx;
+    fv = fx;
+  }
+
+  return fv;
+}
+
+double dxevd() {
+  double dx, dv, de, dd;
+
+#pragma omp atomic compare capture
+  {
+    dv = dx;
+    dx = dx > de ? de : dx;
+  }
+#pragma omp atomic compare capture
+  {
+    dv = dx;
+    dx = dx < de ? de : dx;
+  }
+#pragma omp atomic compare capture
+  {
+    dv = dx;
+    dx = dx == de ? dd : dx;
+  }
+#pragma omp atomic compare capture
+  {
+    dx = dx > de ? de : dx;
+    dv = dx;
+  }
+#pragma omp atomic compare capture
+  {
+    dx = dx < de ? de : dx;
+    dv = dx;
+  }
+#pragma omp atomic compare capture
+  {
+    dx = dx == de ? dd : dx;
+    dv = dx;
+  }
+
+#pragma omp atomic compare capture acq_rel
+  {
+    dv = dx;
+    dx = dx > de ? de : dx;
+  }
+#pragma omp atomic compare capture acq_rel
+  {
+    dv = dx;
+    dx = dx < de ? de : dx;
+  }
+#pragma omp atomic compare capture acq_rel
+  {
+    dv = dx;
+    dx = dx == de ? dd : dx;
+  }
+#pragma omp atomic compare capture acq_rel
+  {
+    dx = dx > de ? de : dx;
+    dv = dx;
+  }
+#pragma omp atomic compare capture acq_rel
+  {
+    dx = dx < de ? de : dx;
+    dv = dx;
+  }
+#pragma omp atomic compare capture acq_rel
+  {
+    dx = dx == de ? dd : dx;
+    dv = dx;
+  }
+
+#pragma omp atomic compare capture acquire
+  {
+    dv = dx;
+    dx = dx > de ? de : dx;
+  }
+#pragma omp atomic compare capture acquire
+  {
+    dv = dx;
+    dx = dx < de ? de : dx;
+  }
+#pragma omp atomic compare capture acquire
+  {
+    dv = dx;
+    dx = dx == de ? dd : dx;
+  }
+#pragma omp atomic compare capture acquire
+  {
+    dx = dx > de ? de : dx;
+    dv = dx;
+  }
+#pragma omp atomic compare capture acquire
+  {
+    dx = dx < de ? de : dx;
+    dv = dx;
+  }
+#pragma omp atomic compare capture acquire
+  {
+    dx = dx == de ? dd : dx;
+    dv = dx;
+  }
+
+#pragma omp atomic compare capture relaxed
+  {
+    dv = dx;
+    dx = dx > de ? de : dx;
+  }
+#pragma omp atomic compare capture relaxed
+  {
+    dv = dx;
+    dx = dx < de ? de : dx;
+  }
+#pragma omp atomic compare capture relaxed
+  {
+    dv = dx;
+    dx = dx == de ? dd : dx;
+  }
+#pragma omp atomic compare capture relaxed
+  {
+    dx = dx > de ? de : dx;
+    dv = dx;
+  }
+#pragma omp atomic compare capture relaxed
+  {
+    dx = dx < de ? de : dx;
+    dv = dx;
+  }
+#pragma omp atomic compare capture relaxed
+  {
+    dx = dx == de ? dd : dx;
+    dv = dx;
+  }
+
+#pragma omp atomic compare capture release
+  {
+    dv = dx;
+    dx = dx > de ? de : dx;
+  }
+#pragma omp atomic compare capture release
+  {
+    dv = dx;
+    dx = dx < de ? de : dx;
+  }
+#pragma omp atomic compare capture release
+  {
+    dv = dx;
+    dx = dx == de ? dd : dx;
+  }
+#pragma omp atomic compare capture release
+  {
+    dx = dx > de ? de : dx;
+    dv = dx;
+  }
+#pragma omp atomic compare capture release
+  {
+    dx = dx < de ? de : dx;
+    dv = dx;
+  }
+#pragma omp atomic compare capture release
+  {
+    dx = dx == de ? dd : dx;
+    dv = dx;
+  }
+
+#pragma omp atomic compare capture seq_cst
+  {
+    dv = dx;
+    dx = dx > de ? de : dx;
+  }
+#pragma omp atomic compare capture seq_cst
+  {
+    dv = dx;
+    dx = dx < de ? de : dx;
+  }
+#pragma omp atomic compare capture seq_cst
+  {
+    dv = dx;
+    dx = dx == de ? dd : dx;
+  }
+#pragma omp atomic compare capture seq_cst
+  {
+    dx = dx > de ? de : dx;
+    dv = dx;
+  }
+#pragma omp atomic compare capture seq_cst
+  {
+    dx = dx < de ? de : dx;
+    dv = dx;
+  }
+#pragma omp atomic compare capture seq_cst
+  {
+    dx = dx == de ? dd : dx;
+    dv = dx;
+  }
+
+  return dv;
+}
+
 #endif
-// CHECK-LABEL: @foo(
+// CHECK-LABEL: define {{[^@]+}}@foo
+// CHECK-SAME: () #[[ATTR0:[0-9]+]] {
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:    [[CX:%.*]] = alloca i8, align 1
 // CHECK-NEXT:    [[CE:%.*]] = alloca i8, align 1
 // CHECK-NEXT:    [[CD:%.*]] = alloca i8, align 1
 // CHECK-NEXT:    [[UCX:%.*]] = alloca i8, align 1
 // CHECK-NEXT:    [[UCE:%.*]] = alloca i8, align 1
 // CHECK-NEXT:    [[UCD:%.*]] = alloca i8, align 1
 // CHECK-NEXT:    [[SX:%.*]] = alloca i16, align 2

 // CHECK-NEXT:    [[TMP1869:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1868]] seq_cst, align 8
 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
 // CHECK-NEXT:    [[TMP1870:%.*]] = load double, ptr [[DE]], align 8
 // CHECK-NEXT:    [[TMP1871:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1870]] seq_cst, align 8
 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
 // CHECK-NEXT:    ret void
 //
 //
-// CHECK-LABEL: @bar(
+// CHECK-LABEL: define {{[^@]+}}@bar
+// CHECK-SAME: () #[[ATTR0]] {
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:    [[CX:%.*]] = alloca i8, align 1
 // CHECK-NEXT:    [[CV:%.*]] = alloca i8, align 1
 // CHECK-NEXT:    [[CR:%.*]] = alloca i8, align 1
 // CHECK-NEXT:    [[CE:%.*]] = alloca i8, align 1
 // CHECK-NEXT:    [[CD:%.*]] = alloca i8, align 1
 // CHECK-NEXT:    [[UCX:%.*]] = alloca i8, align 1
 // CHECK-NEXT:    [[UCV:%.*]] = alloca i8, align 1

 // CHECK-NEXT:    store double [[TMP6068]], ptr [[DV]], align 8
 // CHECK-NEXT:    br label [[DX_ATOMIC_EXIT551]]
 // CHECK:       dx.atomic.exit551:
 // CHECK-NEXT:    [[TMP6070:%.*]] = extractvalue { i64, i1 } [[TMP6066]], 1
 // CHECK-NEXT:    [[TMP6071:%.*]] = sext i1 [[TMP6070]] to i32
 // CHECK-NEXT:    store i32 [[TMP6071]], ptr [[IR]], align 4
 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
 // CHECK-NEXT:    ret void
+//
+//
+// CHECK-LABEL: define {{[^@]+}}@cxevd
+// CHECK-SAME: () #[[ATTR0]] {
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[CX:%.*]] = alloca i8, align 1
+// CHECK-NEXT:    [[CV:%.*]] = alloca i8, align 1
+// CHECK-NEXT:    [[CE:%.*]] = alloca i8, align 1
+// CHECK-NEXT:    [[CD:%.*]] = alloca i8, align 1
+// CHECK-NEXT:    [[TMP0:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP1:%.*]] = atomicrmw min i8* [[CX]], i8 [[TMP0]] monotonic, align 1
+// CHECK-NEXT:    store i8 [[TMP1]], i8* [[CV]], align 1
+// CHECK-NEXT:    [[TMP2:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP3:%.*]] = atomicrmw max i8* [[CX]], i8 [[TMP2]] monotonic, align 1
+// CHECK-NEXT:    store i8 [[TMP3]], i8* [[CV]], align 1
+// CHECK-NEXT:    [[TMP4:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP5:%.*]] = load i8, i8* [[CD]], align 1
+// CHECK-NEXT:    [[TMP6:%.*]] = cmpxchg i8* [[CX]], i8 [[TMP4]], i8 [[TMP5]] monotonic monotonic, align 1
+// CHECK-NEXT:    [[TMP7:%.*]] = extractvalue { i8, i1 } [[TMP6]], 0
+// CHECK-NEXT:    store i8 [[TMP7]], i8* [[CV]], align 1
+// CHECK-NEXT:    [[TMP8:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP9:%.*]] = atomicrmw min i8* [[CX]], i8 [[TMP8]] monotonic, align 1
+// CHECK-NEXT:    [[TMP10:%.*]] = icmp slt i8 [[TMP9]], [[TMP8]]
+// CHECK-NEXT:    [[TMP11:%.*]] = select i1 [[TMP10]], i8 [[TMP8]], i8 [[TMP9]]
+// CHECK-NEXT:    store i8 [[TMP11]], i8* [[CV]], align 1
+// CHECK-NEXT:    [[TMP12:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP13:%.*]] = atomicrmw max i8* [[CX]], i8 [[TMP12]] monotonic, align 1
+// CHECK-NEXT:    [[TMP14:%.*]] = icmp sgt i8 [[TMP13]], [[TMP12]]
+// CHECK-NEXT:    [[TMP15:%.*]] = select i1 [[TMP14]], i8 [[TMP12]], i8 [[TMP13]]
+// CHECK-NEXT:    store i8 [[TMP15]], i8* [[CV]], align 1
+// CHECK-NEXT:    [[TMP16:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP17:%.*]] = load i8, i8* [[CD]], align 1
+// CHECK-NEXT:    [[TMP18:%.*]] = cmpxchg i8* [[CX]], i8 [[TMP16]], i8 [[TMP17]] monotonic monotonic, align 1
+// CHECK-NEXT:    [[TMP19:%.*]] = extractvalue { i8, i1 } [[TMP18]], 0
+// CHECK-NEXT:    [[TMP20:%.*]] = extractvalue { i8, i1 } [[TMP18]], 1
+// CHECK-NEXT:    [[TMP21:%.*]] = select i1 [[TMP20]], i8 [[TMP16]], i8 [[TMP19]]
+// CHECK-NEXT:    store i8 [[TMP21]], i8* [[CV]], align 1
+// CHECK-NEXT:    [[TMP22:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP23:%.*]] = atomicrmw min i8* [[CX]], i8 [[TMP22]] acq_rel, align 1
+// CHECK-NEXT:    store i8 [[TMP23]], i8* [[CV]], align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP24:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP25:%.*]] = atomicrmw max i8* [[CX]], i8 [[TMP24]] acq_rel, align 1
+// CHECK-NEXT:    store i8 [[TMP25]], i8* [[CV]], align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP26:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP27:%.*]] = load i8, i8* [[CD]], align 1
+// CHECK-NEXT:    [[TMP28:%.*]] = cmpxchg i8* [[CX]], i8 [[TMP26]], i8 [[TMP27]] acq_rel acquire, align 1
+// CHECK-NEXT:    [[TMP29:%.*]] = extractvalue { i8, i1 } [[TMP28]], 0
+// CHECK-NEXT:    store i8 [[TMP29]], i8* [[CV]], align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP30:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP31:%.*]] = atomicrmw min i8* [[CX]], i8 [[TMP30]] acq_rel, align 1
+// CHECK-NEXT:    [[TMP32:%.*]] = icmp slt i8 [[TMP31]], [[TMP30]]
+// CHECK-NEXT:    [[TMP33:%.*]] = select i1 [[TMP32]], i8 [[TMP30]], i8 [[TMP31]]
+// CHECK-NEXT:    store i8 [[TMP33]], i8* [[CV]], align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP34:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP35:%.*]] = atomicrmw max i8* [[CX]], i8 [[TMP34]] acq_rel, align 1
+// CHECK-NEXT:    [[TMP36:%.*]] = icmp sgt i8 [[TMP35]], [[TMP34]]
+// CHECK-NEXT:    [[TMP37:%.*]] = select i1 [[TMP36]], i8 [[TMP34]], i8 [[TMP35]]
+// CHECK-NEXT:    store i8 [[TMP37]], i8* [[CV]], align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP38:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP39:%.*]] = load i8, i8* [[CD]], align 1
+// CHECK-NEXT:    [[TMP40:%.*]] = cmpxchg i8* [[CX]], i8 [[TMP38]], i8 [[TMP39]] acq_rel acquire, align 1
+// CHECK-NEXT:    [[TMP41:%.*]] = extractvalue { i8, i1 } [[TMP40]], 0
+// CHECK-NEXT:    [[TMP42:%.*]] = extractvalue { i8, i1 } [[TMP40]], 1
+// CHECK-NEXT:    [[TMP43:%.*]] = select i1 [[TMP42]], i8 [[TMP38]], i8 [[TMP41]]
+// CHECK-NEXT:    store i8 [[TMP43]], i8* [[CV]], align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP44:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP45:%.*]] = atomicrmw min i8* [[CX]], i8 [[TMP44]] acquire, align 1
+// CHECK-NEXT:    store i8 [[TMP45]], i8* [[CV]], align 1
+// CHECK-NEXT:    [[TMP46:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP47:%.*]] = atomicrmw max i8* [[CX]], i8 [[TMP46]] acquire, align 1
+// CHECK-NEXT:    store i8 [[TMP47]], i8* [[CV]], align 1
+// CHECK-NEXT:    [[TMP48:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP49:%.*]] = load i8, i8* [[CD]], align 1
+// CHECK-NEXT:    [[TMP50:%.*]] = cmpxchg i8* [[CX]], i8 [[TMP48]], i8 [[TMP49]] acquire acquire, align 1
+// CHECK-NEXT:    [[TMP51:%.*]] = extractvalue { i8, i1 } [[TMP50]], 0
+// CHECK-NEXT:    store i8 [[TMP51]], i8* [[CV]], align 1
+// CHECK-NEXT:    [[TMP52:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP53:%.*]] = atomicrmw min i8* [[CX]], i8 [[TMP52]] acquire, align 1
+// CHECK-NEXT:    [[TMP54:%.*]] = icmp slt i8 [[TMP53]], [[TMP52]]
+// CHECK-NEXT:    [[TMP55:%.*]] = select i1 [[TMP54]], i8 [[TMP52]], i8 [[TMP53]]
+// CHECK-NEXT:    store i8 [[TMP55]], i8* [[CV]], align 1
+// CHECK-NEXT:    [[TMP56:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP57:%.*]] = atomicrmw max i8* [[CX]], i8 [[TMP56]] acquire, align 1
+// CHECK-NEXT:    [[TMP58:%.*]] = icmp sgt i8 [[TMP57]], [[TMP56]]
+// CHECK-NEXT:    [[TMP59:%.*]] = select i1 [[TMP58]], i8 [[TMP56]], i8 [[TMP57]]
+// CHECK-NEXT:    store i8 [[TMP59]], i8* [[CV]], align 1
+// CHECK-NEXT:    [[TMP60:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP61:%.*]] = load i8, i8* [[CD]], align 1
+// CHECK-NEXT:    [[TMP62:%.*]] = cmpxchg i8* [[CX]], i8 [[TMP60]], i8 [[TMP61]] acquire acquire, align 1
+// CHECK-NEXT:    [[TMP63:%.*]] = extractvalue { i8, i1 } [[TMP62]], 0
+// CHECK-NEXT:    [[TMP64:%.*]] = extractvalue { i8, i1 } [[TMP62]], 1
+// CHECK-NEXT:    [[TMP65:%.*]] = select i1 [[TMP64]], i8 [[TMP60]], i8 [[TMP63]]
+// CHECK-NEXT:    store i8 [[TMP65]], i8* [[CV]], align 1
+// CHECK-NEXT:    [[TMP66:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP67:%.*]] = atomicrmw min i8* [[CX]], i8 [[TMP66]] monotonic, align 1
+// CHECK-NEXT:    store i8 [[TMP67]], i8* [[CV]], align 1
+// CHECK-NEXT:    [[TMP68:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP69:%.*]] = atomicrmw max i8* [[CX]], i8 [[TMP68]] monotonic, align 1
+// CHECK-NEXT:    store i8 [[TMP69]], i8* [[CV]], align 1
+// CHECK-NEXT:    [[TMP70:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP71:%.*]] = load i8, i8* [[CD]], align 1
+// CHECK-NEXT:    [[TMP72:%.*]] = cmpxchg i8* [[CX]], i8 [[TMP70]], i8 [[TMP71]] monotonic monotonic, align 1
+// CHECK-NEXT:    [[TMP73:%.*]] = extractvalue { i8, i1 } [[TMP72]], 0
+// CHECK-NEXT:    store i8 [[TMP73]], i8* [[CV]], align 1
+// CHECK-NEXT:    [[TMP74:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP75:%.*]] = atomicrmw min i8* [[CX]], i8 [[TMP74]] monotonic, align 1
+// CHECK-NEXT:    [[TMP76:%.*]] = icmp slt i8 [[TMP75]], [[TMP74]]
+// CHECK-NEXT:    [[TMP77:%.*]] = select i1 [[TMP76]], i8 [[TMP74]], i8 [[TMP75]]
+// CHECK-NEXT:    store i8 [[TMP77]], i8* [[CV]], align 1
+// CHECK-NEXT:    [[TMP78:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP79:%.*]] = atomicrmw max i8* [[CX]], i8 [[TMP78]] monotonic, align 1
+// CHECK-NEXT:    [[TMP80:%.*]] = icmp sgt i8 [[TMP79]], [[TMP78]]
+// CHECK-NEXT:    [[TMP81:%.*]] = select i1 [[TMP80]], i8 [[TMP78]], i8 [[TMP79]]
+// CHECK-NEXT:    store i8 [[TMP81]], i8* [[CV]], align 1
+// CHECK-NEXT:    [[TMP82:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP83:%.*]] = load i8, i8* [[CD]], align 1
+// CHECK-NEXT:    [[TMP84:%.*]] = cmpxchg i8* [[CX]], i8 [[TMP82]], i8 [[TMP83]] monotonic monotonic, align 1
+// CHECK-NEXT:    [[TMP85:%.*]] = extractvalue { i8, i1 } [[TMP84]], 0
+// CHECK-NEXT:    [[TMP86:%.*]] = extractvalue { i8, i1 } [[TMP84]], 1
+// CHECK-NEXT:    [[TMP87:%.*]] = select i1 [[TMP86]], i8 [[TMP82]], i8 [[TMP85]]
+// CHECK-NEXT:    store i8 [[TMP87]], i8* [[CV]], align 1
+// CHECK-NEXT:    [[TMP88:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP89:%.*]] = atomicrmw min i8* [[CX]], i8 [[TMP88]] release, align 1
+// CHECK-NEXT:    store i8 [[TMP89]], i8* [[CV]], align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP90:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP91:%.*]] = atomicrmw max i8* [[CX]], i8 [[TMP90]] release, align 1
+// CHECK-NEXT:    store i8 [[TMP91]], i8* [[CV]], align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP92:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP93:%.*]] = load i8, i8* [[CD]], align 1
+// CHECK-NEXT:    [[TMP94:%.*]] = cmpxchg i8* [[CX]], i8 [[TMP92]], i8 [[TMP93]] release monotonic, align 1
+// CHECK-NEXT:    [[TMP95:%.*]] = extractvalue { i8, i1 } [[TMP94]], 0
+// CHECK-NEXT:    store i8 [[TMP95]], i8* [[CV]], align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP96:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP97:%.*]] = atomicrmw min i8* [[CX]], i8 [[TMP96]] release, align 1
+// CHECK-NEXT:    [[TMP98:%.*]] = icmp slt i8 [[TMP97]], [[TMP96]]
+// CHECK-NEXT:    [[TMP99:%.*]] = select i1 [[TMP98]], i8 [[TMP96]], i8 [[TMP97]]
+// CHECK-NEXT:    store i8 [[TMP99]], i8* [[CV]], align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP100:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP101:%.*]] = atomicrmw max i8* [[CX]], i8 [[TMP100]] release, align 1
+// CHECK-NEXT:    [[TMP102:%.*]] = icmp sgt i8 [[TMP101]], [[TMP100]]
+// CHECK-NEXT:    [[TMP103:%.*]] = select i1 [[TMP102]], i8 [[TMP100]], i8 [[TMP101]]
+// CHECK-NEXT:    store i8 [[TMP103]], i8* [[CV]], align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP104:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP105:%.*]] = load i8, i8* [[CD]], align 1
+// CHECK-NEXT:    [[TMP106:%.*]] = cmpxchg i8* [[CX]], i8 [[TMP104]], i8 [[TMP105]] release monotonic, align 1
+// CHECK-NEXT:    [[TMP107:%.*]] = extractvalue { i8, i1 } [[TMP106]], 0
+// CHECK-NEXT:    [[TMP108:%.*]] = extractvalue { i8, i1 } [[TMP106]], 1
+// CHECK-NEXT:    [[TMP109:%.*]] = select i1 [[TMP108]], i8 [[TMP104]], i8 [[TMP107]]
+// CHECK-NEXT:    store i8 [[TMP109]], i8* [[CV]], align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP110:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP111:%.*]] = atomicrmw min i8* [[CX]], i8 [[TMP110]] seq_cst, align 1
+// CHECK-NEXT:    store i8 [[TMP111]], i8* [[CV]], align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP112:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP113:%.*]] = atomicrmw max i8* [[CX]], i8 [[TMP112]] seq_cst, align 1
+// CHECK-NEXT:    store i8 [[TMP113]], i8* [[CV]], align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP114:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP115:%.*]] = load i8, i8* [[CD]], align 1
+// CHECK-NEXT:    [[TMP116:%.*]] = cmpxchg i8* [[CX]], i8 [[TMP114]], i8 [[TMP115]] seq_cst seq_cst, align 1
+// CHECK-NEXT:    [[TMP117:%.*]] = extractvalue { i8, i1 } [[TMP116]], 0
+// CHECK-NEXT:    store i8 [[TMP117]], i8* [[CV]], align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP118:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP119:%.*]] = atomicrmw min i8* [[CX]], i8 [[TMP118]] seq_cst, align 1
+// CHECK-NEXT:    [[TMP120:%.*]] = icmp slt i8 [[TMP119]], [[TMP118]]
+// CHECK-NEXT:    [[TMP121:%.*]] = select i1 [[TMP120]], i8 [[TMP118]], i8 [[TMP119]]
+// CHECK-NEXT:    store i8 [[TMP121]], i8* [[CV]], align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP122:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP123:%.*]] = atomicrmw max i8* [[CX]], i8 [[TMP122]] seq_cst, align 1
+// CHECK-NEXT:    [[TMP124:%.*]] = icmp sgt i8 [[TMP123]], [[TMP122]]
+// CHECK-NEXT:    [[TMP125:%.*]] = select i1 [[TMP124]], i8 [[TMP122]], i8 [[TMP123]]
+// CHECK-NEXT:    store i8 [[TMP125]], i8* [[CV]], align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP126:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP127:%.*]] = load i8, i8* [[CD]], align 1
+// CHECK-NEXT:    [[TMP128:%.*]] = cmpxchg i8* [[CX]], i8 [[TMP126]], i8 [[TMP127]] seq_cst seq_cst, align 1
+// CHECK-NEXT:    [[TMP129:%.*]] = extractvalue { i8, i1 } [[TMP128]], 0
+// CHECK-NEXT:    [[TMP130:%.*]] = extractvalue { i8, i1 } [[TMP128]], 1
+// CHECK-NEXT:    [[TMP131:%.*]] = select i1 [[TMP130]], i8 [[TMP126]], i8 [[TMP129]]
+// CHECK-NEXT:    store i8 [[TMP131]], i8* [[CV]], align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP132:%.*]] = load i8, i8* [[CV]], align 1
+// CHECK-NEXT:    ret i8 [[TMP132]]
+//
+//
+// CHECK-LABEL: define {{[^@]+}}@ucxevd
+// CHECK-SAME: () #[[ATTR0]] {
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[UCX:%.*]] = alloca i8, align 1
+// CHECK-NEXT:    [[UCV:%.*]] = alloca i8, align 1
+// CHECK-NEXT:    [[UCE:%.*]] = alloca i8, align 1
+// CHECK-NEXT:    [[UCD:%.*]] = alloca i8, align 1
+// CHECK-NEXT:    [[TMP0:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP1:%.*]] = atomicrmw umin i8* [[UCX]], i8 [[TMP0]] monotonic, align 1
+// CHECK-NEXT:    store i8 [[TMP1]], i8* [[UCV]], align 1
+// CHECK-NEXT:    [[TMP2:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP3:%.*]] = atomicrmw umax i8* [[UCX]], i8 [[TMP2]] monotonic, align 1
+// CHECK-NEXT:    store i8 [[TMP3]], i8* [[UCV]], align 1
+// CHECK-NEXT:    [[TMP4:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP5:%.*]] = load i8, i8* [[UCD]], align 1
+// CHECK-NEXT:    [[TMP6:%.*]] = cmpxchg i8* [[UCX]], i8 [[TMP4]], i8 [[TMP5]] monotonic monotonic, align 1
+// CHECK-NEXT:    [[TMP7:%.*]] = extractvalue { i8, i1 } [[TMP6]], 0
+// CHECK-NEXT:    store i8 [[TMP7]], i8* [[UCV]], align 1
+// CHECK-NEXT:    [[TMP8:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP9:%.*]] = atomicrmw umin i8* [[UCX]], i8 [[TMP8]] monotonic, align 1
+// CHECK-NEXT:    [[TMP10:%.*]] = icmp ult i8 [[TMP9]], [[TMP8]]
+// CHECK-NEXT:    [[TMP11:%.*]] = select i1 [[TMP10]], i8 [[TMP8]], i8 [[TMP9]]
+// CHECK-NEXT:    store i8 [[TMP11]], i8* [[UCV]], align 1
+// CHECK-NEXT:    [[TMP12:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP13:%.*]] = atomicrmw umax i8* [[UCX]], i8 [[TMP12]] monotonic, align 1
+// CHECK-NEXT:    [[TMP14:%.*]] = icmp ugt i8 [[TMP13]], [[TMP12]]
+// CHECK-NEXT:    [[TMP15:%.*]] = select i1 [[TMP14]], i8 [[TMP12]], i8 [[TMP13]]
+// CHECK-NEXT:    store i8 [[TMP15]], i8* [[UCV]], align 1
+// CHECK-NEXT:    [[TMP16:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP17:%.*]] = load i8, i8* [[UCD]], align 1
+// CHECK-NEXT:    [[TMP18:%.*]] = cmpxchg i8* [[UCX]], i8 [[TMP16]], i8 [[TMP17]] monotonic monotonic, align 1
+// CHECK-NEXT:    [[TMP19:%.*]] = extractvalue { i8, i1 } [[TMP18]], 0
+// CHECK-NEXT:    [[TMP20:%.*]] = extractvalue { i8, i1 } [[TMP18]], 1
+// CHECK-NEXT:    [[TMP21:%.*]] = select i1 [[TMP20]], i8 [[TMP16]], i8 [[TMP19]]
+// CHECK-NEXT:    store i8 [[TMP21]], i8* [[UCV]], align 1
+// CHECK-NEXT:    [[TMP22:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP23:%.*]] = atomicrmw umin i8* [[UCX]], i8 [[TMP22]] acq_rel, align 1
+// CHECK-NEXT:    store i8 [[TMP23]], i8* [[UCV]], align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP24:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP25:%.*]] = atomicrmw umax i8* [[UCX]], i8 [[TMP24]] acq_rel, align 1
+// CHECK-NEXT:    store i8 [[TMP25]], i8* [[UCV]], align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP26:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP27:%.*]] = load i8, i8* [[UCD]], align 1
+// CHECK-NEXT:    [[TMP28:%.*]] = cmpxchg i8* [[UCX]], i8 [[TMP26]], i8 [[TMP27]] acq_rel acquire, align 1
+// CHECK-NEXT:    [[TMP29:%.*]] = extractvalue { i8, i1 } [[TMP28]], 0
+// CHECK-NEXT:    store i8 [[TMP29]], i8* [[UCV]], align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP30:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP31:%.*]] = atomicrmw umin i8* [[UCX]], i8 [[TMP30]] acq_rel, align 1
+// CHECK-NEXT:    [[TMP32:%.*]] = icmp ult i8 [[TMP31]], [[TMP30]]
+// CHECK-NEXT:    [[TMP33:%.*]] = select i1 [[TMP32]], i8 [[TMP30]], i8 [[TMP31]]
+// CHECK-NEXT:    store i8 [[TMP33]], i8* [[UCV]], align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP34:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP35:%.*]] = atomicrmw umax i8* [[UCX]], i8 [[TMP34]] acq_rel, align 1
+// CHECK-NEXT:    [[TMP36:%.*]] = icmp ugt i8 [[TMP35]], [[TMP34]]
+// CHECK-NEXT:    [[TMP37:%.*]] = select i1 [[TMP36]], i8 [[TMP34]], i8 [[TMP35]]
+// CHECK-NEXT:    store i8 [[TMP37]], i8* [[UCV]], align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP38:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP39:%.*]] = load i8, i8* [[UCD]], align 1
+// CHECK-NEXT:    [[TMP40:%.*]] = cmpxchg i8* [[UCX]], i8 [[TMP38]], i8 [[TMP39]] acq_rel acquire, align 1
+// CHECK-NEXT:    [[TMP41:%.*]] = extractvalue { i8, i1 } [[TMP40]], 0
+// CHECK-NEXT:    [[TMP42:%.*]] = extractvalue { i8, i1 } [[TMP40]], 1
+// CHECK-NEXT:    [[TMP43:%.*]] = select i1 [[TMP42]], i8 [[TMP38]], i8 [[TMP41]]
+// CHECK-NEXT:    store i8 [[TMP43]], i8* [[UCV]], align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP44:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP45:%.*]] = atomicrmw umin i8* [[UCX]], i8 [[TMP44]] acquire, align 1
+// CHECK-NEXT:    store i8 [[TMP45]], i8* [[UCV]], align 1
+// CHECK-NEXT:    [[TMP46:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP47:%.*]] = atomicrmw umax i8* [[UCX]], i8 [[TMP46]] acquire, align 1
+// CHECK-NEXT:    store i8 [[TMP47]], i8* [[UCV]], align 1
+// CHECK-NEXT:    [[TMP48:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP49:%.*]] = load i8, i8* [[UCD]], align 1
+// CHECK-NEXT:    [[TMP50:%.*]] = cmpxchg i8* [[UCX]], i8 [[TMP48]], i8 [[TMP49]] acquire acquire, align 1
+// CHECK-NEXT:    [[TMP51:%.*]] = extractvalue { i8, i1 } [[TMP50]], 0
+// CHECK-NEXT:    store i8 [[TMP51]], i8* [[UCV]], align 1
+// CHECK-NEXT:    [[TMP52:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP53:%.*]] = atomicrmw umin i8* [[UCX]], i8 [[TMP52]] acquire, align 1
+// CHECK-NEXT:    [[TMP54:%.*]] = icmp ult i8 [[TMP53]], [[TMP52]]
+// CHECK-NEXT:    [[TMP55:%.*]] = select i1 [[TMP54]], i8 [[TMP52]], i8 [[TMP53]]
+// CHECK-NEXT:    store i8 [[TMP55]], i8* [[UCV]], align 1
+// CHECK-NEXT:    [[TMP56:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP57:%.*]] = atomicrmw umax i8* [[UCX]], i8 [[TMP56]] acquire, align 1
+// CHECK-NEXT:    [[TMP58:%.*]] = icmp ugt i8 [[TMP57]], [[TMP56]]
+// CHECK-NEXT:    [[TMP59:%.*]] = select i1 [[TMP58]], i8 [[TMP56]], i8 [[TMP57]]
+// CHECK-NEXT:    store i8 [[TMP59]], i8* [[UCV]], align 1
+// CHECK-NEXT:    [[TMP60:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP61:%.*]] = load i8, i8* [[UCD]], align 1
+// CHECK-NEXT:    [[TMP62:%.*]] = cmpxchg i8* [[UCX]], i8 [[TMP60]], i8 [[TMP61]] acquire acquire, align 1
+// CHECK-NEXT:    [[TMP63:%.*]] = extractvalue { i8, i1 } [[TMP62]], 0
+// CHECK-NEXT:    [[TMP64:%.*]] = extractvalue { i8, i1 } [[TMP62]], 1
+// CHECK-NEXT:    [[TMP65:%.*]] = select i1 [[TMP64]], i8 [[TMP60]], i8 [[TMP63]]
+// CHECK-NEXT:    store i8 [[TMP65]], i8* [[UCV]], align 1
+// CHECK-NEXT:    [[TMP66:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP67:%.*]] = atomicrmw umin i8* [[UCX]], i8 [[TMP66]] monotonic, align 1
+// CHECK-NEXT:    store i8 [[TMP67]], i8* [[UCV]], align 1
+// CHECK-NEXT:    [[TMP68:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP69:%.*]] = atomicrmw umax i8* [[UCX]], i8 [[TMP68]] monotonic, align 1
+// CHECK-NEXT:    store i8 [[TMP69]], i8* [[UCV]], align 1
+// CHECK-NEXT:    [[TMP70:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP71:%.*]] = load i8, i8* [[UCD]], align 1
+// CHECK-NEXT:    [[TMP72:%.*]] = cmpxchg i8* [[UCX]], i8 [[TMP70]], i8 [[TMP71]] monotonic monotonic, align 1
+// CHECK-NEXT:    [[TMP73:%.*]] = extractvalue { i8, i1 } [[TMP72]], 0
+// CHECK-NEXT:    store i8 [[TMP73]], i8* [[UCV]], align 1
+// CHECK-NEXT:    [[TMP74:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP75:%.*]] = atomicrmw umin i8* [[UCX]], i8 [[TMP74]] monotonic, align 1
+// CHECK-NEXT:    [[TMP76:%.*]] = icmp ult i8 [[TMP75]], [[TMP74]]
+// CHECK-NEXT:    [[TMP77:%.*]] = select i1 [[TMP76]], i8 [[TMP74]], i8 [[TMP75]]
+// CHECK-NEXT:    store i8 [[TMP77]], i8* [[UCV]], align 1
+// CHECK-NEXT:    [[TMP78:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP79:%.*]] = atomicrmw umax i8* [[UCX]], i8 [[TMP78]] monotonic, align 1
+// CHECK-NEXT:    [[TMP80:%.*]] = icmp ugt i8 [[TMP79]], [[TMP78]]
+// CHECK-NEXT:    [[TMP81:%.*]] = select i1 [[TMP80]], i8 [[TMP78]], i8 [[TMP79]]
+// CHECK-NEXT:    store i8 [[TMP81]], i8* [[UCV]], align 1
+// CHECK-NEXT:    [[TMP82:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP83:%.*]] = load i8, i8* [[UCD]], align 1
+// CHECK-NEXT:    [[TMP84:%.*]] = cmpxchg i8* [[UCX]], i8 [[TMP82]], i8 [[TMP83]] monotonic monotonic, align 1
+// CHECK-NEXT:    [[TMP85:%.*]] = extractvalue { i8, i1 } [[TMP84]], 0
+// CHECK-NEXT:    [[TMP86:%.*]] = extractvalue { i8, i1 } [[TMP84]], 1
+// CHECK-NEXT:    [[TMP87:%.*]] = select i1 [[TMP86]], i8 [[TMP82]], i8 [[TMP85]]
+// CHECK-NEXT:    store i8 [[TMP87]], i8* [[UCV]], align 1
+// CHECK-NEXT:    [[TMP88:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP89:%.*]] = atomicrmw umin i8* [[UCX]], i8 [[TMP88]] release, align 1
+// CHECK-NEXT:    store i8 [[TMP89]], i8* [[UCV]], align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP90:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP91:%.*]] = atomicrmw umax i8* [[UCX]], i8 [[TMP90]] release, align 1
+// CHECK-NEXT:    store i8 [[TMP91]], i8* [[UCV]], align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP92:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP93:%.*]] = load i8, i8* [[UCD]], align 1
+// CHECK-NEXT:    [[TMP94:%.*]] = cmpxchg i8* [[UCX]], i8 [[TMP92]], i8 [[TMP93]] release monotonic, align 1
+// CHECK-NEXT:    [[TMP95:%.*]] = extractvalue { i8, i1 } [[TMP94]], 0
+// CHECK-NEXT:    store i8 [[TMP95]], i8* [[UCV]], align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP96:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP97:%.*]] = atomicrmw umin i8* [[UCX]], i8 [[TMP96]] release, align 1
+// CHECK-NEXT:    [[TMP98:%.*]] = icmp ult i8 [[TMP97]], [[TMP96]]
+// CHECK-NEXT:    [[TMP99:%.*]] = select i1 [[TMP98]], i8 [[TMP96]], i8 [[TMP97]]
+// CHECK-NEXT:    store i8 [[TMP99]], i8* [[UCV]], align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP100:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP101:%.*]] = atomicrmw umax i8* [[UCX]], i8 [[TMP100]] release, align 1
+// CHECK-NEXT:    [[TMP102:%.*]] = icmp ugt i8 [[TMP101]], [[TMP100]]
+// CHECK-NEXT:    [[TMP103:%.*]] = select i1 [[TMP102]], i8 [[TMP100]], i8 [[TMP101]]
+// CHECK-NEXT:    store i8 [[TMP103]], i8* [[UCV]], align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP104:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP105:%.*]] = load i8, i8* [[UCD]], align 1
+// CHECK-NEXT:    [[TMP106:%.*]] = cmpxchg i8* [[UCX]], i8 [[TMP104]], i8 [[TMP105]] release monotonic, align 1
+// CHECK-NEXT:    [[TMP107:%.*]] = extractvalue { i8, i1 } [[TMP106]], 0
+// CHECK-NEXT:    [[TMP108:%.*]] = extractvalue { i8, i1 } [[TMP106]], 1
+// CHECK-NEXT:    [[TMP109:%.*]] = select i1 [[TMP108]], i8 [[TMP104]], i8 [[TMP107]]
+// CHECK-NEXT:    store i8 [[TMP109]], i8* [[UCV]], align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP110:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP111:%.*]] = atomicrmw umin i8* [[UCX]], i8 [[TMP110]] seq_cst, align 1
+// CHECK-NEXT:    store i8 [[TMP111]], i8* [[UCV]], align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP112:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP113:%.*]] = atomicrmw umax i8* [[UCX]], i8 [[TMP112]] seq_cst, align 1
+// CHECK-NEXT:    store i8 [[TMP113]], i8* [[UCV]], align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP114:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP115:%.*]] = load i8, i8* [[UCD]], align 1
+// CHECK-NEXT:    [[TMP116:%.*]] = cmpxchg i8* [[UCX]], i8 [[TMP114]], i8 [[TMP115]] seq_cst seq_cst, align 1
+// CHECK-NEXT:    [[TMP117:%.*]] = extractvalue { i8, i1 } [[TMP116]], 0
+// CHECK-NEXT:    store i8 [[TMP117]], i8* [[UCV]], align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP118:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP119:%.*]] = atomicrmw umin i8* [[UCX]], i8 [[TMP118]] seq_cst, align 1
+// CHECK-NEXT:    [[TMP120:%.*]] = icmp ult i8 [[TMP119]], [[TMP118]]
+// CHECK-NEXT:    [[TMP121:%.*]] = select i1 [[TMP120]], i8 [[TMP118]], i8 [[TMP119]]
+// CHECK-NEXT:    store i8 [[TMP121]], i8* [[UCV]], align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP122:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP123:%.*]] = atomicrmw umax i8* [[UCX]], i8 [[TMP122]] seq_cst, align 1
+// CHECK-NEXT:    [[TMP124:%.*]] = icmp ugt i8 [[TMP123]], [[TMP122]]
+// CHECK-NEXT:    [[TMP125:%.*]] = select i1 [[TMP124]], i8 [[TMP122]], i8 [[TMP123]]
+// CHECK-NEXT:    store i8 [[TMP125]], i8* [[UCV]], align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP126:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP127:%.*]] = load i8, i8* [[UCD]], align 1
+// CHECK-NEXT:    [[TMP128:%.*]] = cmpxchg i8* [[UCX]], i8 [[TMP126]], i8 [[TMP127]] seq_cst seq_cst, align 1
+// CHECK-NEXT:    [[TMP129:%.*]] = extractvalue { i8, i1 } [[TMP128]], 0
+// CHECK-NEXT:    [[TMP130:%.*]] = extractvalue { i8, i1 } [[TMP128]], 1
+// CHECK-NEXT:    [[TMP131:%.*]] = select i1 [[TMP130]], i8 [[TMP126]], i8 [[TMP129]]
+// CHECK-NEXT:    store i8 [[TMP131]], i8* [[UCV]], align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP132:%.*]] = load i8, i8* [[UCV]], align 1
+// CHECK-NEXT:    ret i8 [[TMP132]]
+//
+//
+// CHECK-LABEL: define {{[^@]+}}@sxevd
+// CHECK-SAME: () #[[ATTR0]] {
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[SX:%.*]] = alloca i16, align 2
+// CHECK-NEXT:    [[SV:%.*]] = alloca i16, align 2
+// CHECK-NEXT:    [[SE:%.*]] = alloca i16, align 2
+// CHECK-NEXT:    [[SD:%.*]] = alloca i16, align 2
+// CHECK-NEXT:    [[TMP0:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP1:%.*]] = atomicrmw min i16* [[SX]], i16 [[TMP0]] monotonic, align 2
+// CHECK-NEXT:    store i16 [[TMP1]], i16* [[SV]], align 2
+// CHECK-NEXT:    [[TMP2:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP3:%.*]] = atomicrmw max i16* [[SX]], i16 [[TMP2]] monotonic, align 2
+// CHECK-NEXT:    store i16 [[TMP3]], i16* [[SV]], align 2
+// CHECK-NEXT:    [[TMP4:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP5:%.*]] = load i16, i16* [[SD]], align 2
+// CHECK-NEXT:    [[TMP6:%.*]] = cmpxchg i16* [[SX]], i16 [[TMP4]], i16 [[TMP5]] monotonic monotonic, align 2
+// CHECK-NEXT:    [[TMP7:%.*]] = extractvalue { i16, i1 } [[TMP6]], 0
+// CHECK-NEXT:    store i16 [[TMP7]], i16* [[SV]], align 2
+// CHECK-NEXT:    [[TMP8:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP9:%.*]] = atomicrmw min i16* [[SX]], i16 [[TMP8]] monotonic, align 2
+// CHECK-NEXT:    [[TMP10:%.*]] = icmp slt i16 [[TMP9]], [[TMP8]]
+// CHECK-NEXT:    [[TMP11:%.*]] = select i1 [[TMP10]], i16 [[TMP8]], i16 [[TMP9]]
+// CHECK-NEXT:    store i16 [[TMP11]], i16* [[SV]], align 2
+// CHECK-NEXT:    [[TMP12:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP13:%.*]] = atomicrmw max i16* [[SX]], i16 [[TMP12]] monotonic, align 2
+// CHECK-NEXT:    [[TMP14:%.*]] = icmp sgt i16 [[TMP13]], [[TMP12]]
+// CHECK-NEXT:    [[TMP15:%.*]] = select i1 [[TMP14]], i16 [[TMP12]], i16 [[TMP13]]
+// CHECK-NEXT:    store i16 [[TMP15]], i16* [[SV]], align 2
+// CHECK-NEXT:    [[TMP16:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP17:%.*]] = load i16, i16* [[SD]], align 2
+// CHECK-NEXT:    [[TMP18:%.*]] = cmpxchg i16* [[SX]], i16 [[TMP16]], i16 [[TMP17]] monotonic monotonic, align 2
+// CHECK-NEXT:    [[TMP19:%.*]] = extractvalue { i16, i1 } [[TMP18]], 0
+// CHECK-NEXT:    [[TMP20:%.*]] = extractvalue { i16, i1 } [[TMP18]], 1
+// CHECK-NEXT:    [[TMP21:%.*]] = select i1 [[TMP20]], i16 [[TMP16]], i16 [[TMP19]]
+// CHECK-NEXT:    store i16 [[TMP21]], i16* [[SV]], align 2
+// CHECK-NEXT:    [[TMP22:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP23:%.*]] = atomicrmw min i16* [[SX]], i16 [[TMP22]] acq_rel, align 2
+// CHECK-NEXT:    store i16 [[TMP23]], i16* [[SV]], align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP24:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP25:%.*]] = atomicrmw max i16* [[SX]], i16 [[TMP24]] acq_rel, align 2
+// CHECK-NEXT:    store i16 [[TMP25]], i16* [[SV]], align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP26:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP27:%.*]] = load i16, i16* [[SD]], align 2
+// CHECK-NEXT:    [[TMP28:%.*]] = cmpxchg i16* [[SX]], i16 [[TMP26]], i16 [[TMP27]] acq_rel acquire, align 2
+// CHECK-NEXT:    [[TMP29:%.*]] = extractvalue { i16, i1 } [[TMP28]], 0
+// CHECK-NEXT:    store i16 [[TMP29]], i16* [[SV]], align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP30:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP31:%.*]] = atomicrmw min i16* [[SX]], i16 [[TMP30]] acq_rel, align 2
+// CHECK-NEXT:    [[TMP32:%.*]] = icmp slt i16 [[TMP31]], [[TMP30]]
+// CHECK-NEXT:    [[TMP33:%.*]] = select i1 [[TMP32]], i16 [[TMP30]], i16 [[TMP31]]
+// CHECK-NEXT:    store i16 [[TMP33]], i16* [[SV]], align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP34:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP35:%.*]] = atomicrmw max i16* [[SX]], i16 [[TMP34]] acq_rel, align 2
+// CHECK-NEXT:    [[TMP36:%.*]] = icmp sgt i16 [[TMP35]], [[TMP34]]
+// CHECK-NEXT:    [[TMP37:%.*]] = select i1 [[TMP36]], i16 [[TMP34]], i16 [[TMP35]]
+// CHECK-NEXT:    store i16 [[TMP37]], i16* [[SV]], align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP38:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP39:%.*]] = load i16, i16* [[SD]], align 2
+// CHECK-NEXT:    [[TMP40:%.*]] = cmpxchg i16* [[SX]], i16 [[TMP38]], i16 [[TMP39]] acq_rel acquire, align 2
+// CHECK-NEXT:    [[TMP41:%.*]] = extractvalue { i16, i1 } [[TMP40]], 0
+// CHECK-NEXT:    [[TMP42:%.*]] = extractvalue { i16, i1 } [[TMP40]], 1
+// CHECK-NEXT:    [[TMP43:%.*]] = select i1 [[TMP42]], i16 [[TMP38]], i16 [[TMP41]]
+// CHECK-NEXT:    store i16 [[TMP43]], i16* [[SV]], align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP44:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP45:%.*]] = atomicrmw min i16* [[SX]], i16 [[TMP44]] acquire, align 2
+// CHECK-NEXT:    store i16 [[TMP45]], i16* [[SV]], align 2
+// CHECK-NEXT:    [[TMP46:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP47:%.*]] = atomicrmw max i16* [[SX]], i16 [[TMP46]] acquire, align 2
+// CHECK-NEXT:    store i16 [[TMP47]], i16* [[SV]], align 2
+// CHECK-NEXT:    [[TMP48:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP49:%.*]] = load i16, i16* [[SD]], align 2
+// CHECK-NEXT:    [[TMP50:%.*]] = cmpxchg i16* [[SX]], i16 [[TMP48]], i16 [[TMP49]] acquire acquire, align 2
+// CHECK-NEXT:    [[TMP51:%.*]] = extractvalue { i16, i1 } [[TMP50]], 0
+// CHECK-NEXT:    store i16 [[TMP51]], i16* [[SV]], align 2
+// CHECK-NEXT:    [[TMP52:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP53:%.*]] = atomicrmw min i16* [[SX]], i16 [[TMP52]] acquire, align 2
+// CHECK-NEXT:    [[TMP54:%.*]] = icmp slt i16 [[TMP53]], [[TMP52]]
+// CHECK-NEXT:    [[TMP55:%.*]] = select i1 [[TMP54]], i16 [[TMP52]], i16 [[TMP53]]
+// CHECK-NEXT:    store i16 [[TMP55]], i16* [[SV]], align 2
+// CHECK-NEXT:    [[TMP56:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP57:%.*]] = atomicrmw max i16* [[SX]], i16 [[TMP56]] acquire, align 2
+// CHECK-NEXT:    [[TMP58:%.*]] = icmp sgt i16 [[TMP57]], [[TMP56]]
+// CHECK-NEXT:    [[TMP59:%.*]] = select i1 [[TMP58]], i16 [[TMP56]], i16 [[TMP57]]
+// CHECK-NEXT:    store i16 [[TMP59]], i16* [[SV]], align 2
+// CHECK-NEXT:    [[TMP60:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP61:%.*]] = load i16, i16* [[SD]], align 2
+// CHECK-NEXT:    [[TMP62:%.*]] = cmpxchg i16* [[SX]], i16 [[TMP60]], i16 [[TMP61]] acquire acquire, align 2
+// CHECK-NEXT:    [[TMP63:%.*]] = extractvalue { i16, i1 } [[TMP62]], 0
+// CHECK-NEXT:    [[TMP64:%.*]] = extractvalue { i16, i1 } [[TMP62]], 1
+// CHECK-NEXT:    [[TMP65:%.*]] = select i1 [[TMP64]], i16 [[TMP60]], i16 [[TMP63]]
+// CHECK-NEXT:    store i16 [[TMP65]], i16* [[SV]], align 2
+// CHECK-NEXT:    [[TMP66:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP67:%.*]] = atomicrmw min i16* [[SX]], i16 [[TMP66]] monotonic, align 2
+// CHECK-NEXT:    store i16 [[TMP67]], i16* [[SV]], align 2
+// CHECK-NEXT:    [[TMP68:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP69:%.*]] = atomicrmw max i16* [[SX]], i16 [[TMP68]] monotonic, align 2
+// CHECK-NEXT:    store i16 [[TMP69]], i16* [[SV]], align 2
+// CHECK-NEXT:    [[TMP70:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP71:%.*]] = load i16, i16* [[SD]], align 2
+// CHECK-NEXT:    [[TMP72:%.*]] = cmpxchg i16* [[SX]], i16 [[TMP70]], i16 [[TMP71]] monotonic monotonic, align 2
+// CHECK-NEXT:    [[TMP73:%.*]] = extractvalue { i16, i1 } [[TMP72]], 0
+// CHECK-NEXT:    store i16 [[TMP73]], i16* [[SV]], align 2
+// CHECK-NEXT:    [[TMP74:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP75:%.*]] = atomicrmw min i16* [[SX]], i16 [[TMP74]] monotonic, align 2
+// CHECK-NEXT:    [[TMP76:%.*]] = icmp slt i16 [[TMP75]], [[TMP74]]
+// CHECK-NEXT:    [[TMP77:%.*]] = select i1 [[TMP76]], i16 [[TMP74]], i16 [[TMP75]]
+// CHECK-NEXT:    store i16 [[TMP77]], i16* [[SV]], align 2
+// CHECK-NEXT:    [[TMP78:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP79:%.*]] = atomicrmw max i16* [[SX]], i16 [[TMP78]] monotonic, align 2
+// CHECK-NEXT:    [[TMP80:%.*]] = icmp sgt i16 [[TMP79]], [[TMP78]]
+// CHECK-NEXT:    [[TMP81:%.*]] = select i1 [[TMP80]], i16 [[TMP78]], i16 [[TMP79]]
+// CHECK-NEXT:    store i16 [[TMP81]], i16* [[SV]], align 2
+// CHECK-NEXT:    [[TMP82:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP83:%.*]] = load i16, i16* [[SD]], align 2
+// CHECK-NEXT:    [[TMP84:%.*]] = cmpxchg i16* [[SX]], i16 [[TMP82]], i16 [[TMP83]] monotonic monotonic, align 2
+// CHECK-NEXT:    [[TMP85:%.*]] = extractvalue { i16, i1 } [[TMP84]], 0
+// CHECK-NEXT:    [[TMP86:%.*]] = extractvalue { i16, i1 } [[TMP84]], 1
+// CHECK-NEXT:    [[TMP87:%.*]] = select i1 [[TMP86]], i16 [[TMP82]], i16 [[TMP85]]
+// CHECK-NEXT:    store i16 [[TMP87]], i16* [[SV]], align 2
+// CHECK-NEXT:    [[TMP88:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP89:%.*]] = atomicrmw min i16* [[SX]], i16 [[TMP88]] release, align 2
+// CHECK-NEXT:    store i16 [[TMP89]], i16* [[SV]], align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP90:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP91:%.*]] = atomicrmw max i16* [[SX]], i16 [[TMP90]] release, align 2
+// CHECK-NEXT:    store i16 [[TMP91]], i16* [[SV]], align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP92:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP93:%.*]] = load i16, i16* [[SD]], align 2
+// CHECK-NEXT:    [[TMP94:%.*]] = cmpxchg i16* [[SX]], i16 [[TMP92]], i16 [[TMP93]] release monotonic, align 2
+// CHECK-NEXT:    [[TMP95:%.*]] = extractvalue { i16, i1 } [[TMP94]], 0
+// CHECK-NEXT:    store i16 [[TMP95]], i16* [[SV]], align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP96:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP97:%.*]] = atomicrmw min i16* [[SX]], i16 [[TMP96]] release, align 2
+// CHECK-NEXT:    [[TMP98:%.*]] = icmp slt i16 [[TMP97]], [[TMP96]]
+// CHECK-NEXT:    [[TMP99:%.*]] = select i1 [[TMP98]], i16 [[TMP96]], i16 [[TMP97]]
+// CHECK-NEXT:    store i16 [[TMP99]], i16* [[SV]], align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP100:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP101:%.*]] = atomicrmw max i16* [[SX]], i16 [[TMP100]] release, align 2
+// CHECK-NEXT:    [[TMP102:%.*]] = icmp sgt i16 [[TMP101]], [[TMP100]]
+// CHECK-NEXT:    [[TMP103:%.*]] = select i1 [[TMP102]], i16 [[TMP100]], i16 [[TMP101]]
+// CHECK-NEXT:    store i16 [[TMP103]], i16* [[SV]], align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP104:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP105:%.*]] = load i16, i16* [[SD]], align 2
+// CHECK-NEXT:    [[TMP106:%.*]] = cmpxchg i16* [[SX]], i16 [[TMP104]], i16 [[TMP105]] release monotonic, align 2
+// CHECK-NEXT:    [[TMP107:%.*]] = extractvalue { i16, i1 } [[TMP106]], 0
+// CHECK-NEXT:    [[TMP108:%.*]] = extractvalue { i16, i1 } [[TMP106]], 1
+// CHECK-NEXT:    [[TMP109:%.*]] = select i1 [[TMP108]], i16 [[TMP104]], i16 [[TMP107]]
+// CHECK-NEXT:    store i16 [[TMP109]], i16* [[SV]], align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP110:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP111:%.*]] = atomicrmw min i16* [[SX]], i16 [[TMP110]] seq_cst, align 2
+// CHECK-NEXT:    store i16 [[TMP111]], i16* [[SV]], align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP112:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP113:%.*]] = atomicrmw max i16* [[SX]], i16 [[TMP112]] seq_cst, align 2
+// CHECK-NEXT:    store i16 [[TMP113]], i16* [[SV]], align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP114:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP115:%.*]] = load i16, i16* [[SD]], align 2
+// CHECK-NEXT:    [[TMP116:%.*]] = cmpxchg i16* [[SX]], i16 [[TMP114]], i16 [[TMP115]] seq_cst seq_cst, align 2
+// CHECK-NEXT:    [[TMP117:%.*]] = extractvalue { i16, i1 } [[TMP116]], 0
+// CHECK-NEXT:    store i16 [[TMP117]], i16* [[SV]], align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP118:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP119:%.*]] = atomicrmw min i16* [[SX]], i16 [[TMP118]] seq_cst, align 2
+// CHECK-NEXT:    [[TMP120:%.*]] = icmp slt i16 [[TMP119]], [[TMP118]]
+// CHECK-NEXT:    [[TMP121:%.*]] = select i1 [[TMP120]], i16 [[TMP118]], i16 [[TMP119]]
+// CHECK-NEXT:    store i16 [[TMP121]], i16* [[SV]], align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP122:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP123:%.*]] = atomicrmw max i16* [[SX]], i16 [[TMP122]] seq_cst, align 2
+// CHECK-NEXT:    [[TMP124:%.*]] = icmp sgt i16 [[TMP123]], [[TMP122]]
+// CHECK-NEXT:    [[TMP125:%.*]] = select i1 [[TMP124]], i16 [[TMP122]], i16 [[TMP123]]
+// CHECK-NEXT:    store i16 [[TMP125]], i16* [[SV]], align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP126:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP127:%.*]] = load i16, i16* [[SD]], align 2
+// CHECK-NEXT:    [[TMP128:%.*]] = cmpxchg i16* [[SX]], i16 [[TMP126]], i16 [[TMP127]] seq_cst seq_cst, align 2
+// CHECK-NEXT:    [[TMP129:%.*]] = extractvalue { i16, i1 } [[TMP128]], 0
+// CHECK-NEXT:    [[TMP130:%.*]] = extractvalue { i16, i1 } [[TMP128]], 1
+// CHECK-NEXT:    [[TMP131:%.*]] = select i1 [[TMP130]], i16 [[TMP126]], i16 [[TMP129]]
+// CHECK-NEXT:    store i16 [[TMP131]], i16* [[SV]], align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP132:%.*]] = load i16, i16* [[SV]], align 2
+// CHECK-NEXT:    ret i16 [[TMP132]]
+//
+//
+// CHECK-LABEL: define {{[^@]+}}@usxevd
+// CHECK-SAME: () #[[ATTR0]] {
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[USX:%.*]] = alloca i16, align 2
+// CHECK-NEXT:    [[USV:%.*]] = alloca i16, align 2
+// CHECK-NEXT:    [[USE:%.*]] = alloca i16, align 2
+// CHECK-NEXT:    [[USD:%.*]] = alloca i16, align 2
+// CHECK-NEXT:    [[TMP0:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP1:%.*]] = atomicrmw umin i16* [[USX]], i16 [[TMP0]] monotonic, align 2
+// CHECK-NEXT:    store i16 [[TMP1]], i16* [[USV]], align 2
+// CHECK-NEXT:    [[TMP2:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP3:%.*]] = atomicrmw umax i16* [[USX]], i16 [[TMP2]] monotonic, align 2
+// CHECK-NEXT:    store i16 [[TMP3]], i16* [[USV]], align 2
+// CHECK-NEXT:    [[TMP4:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP5:%.*]] = load i16, i16* [[USD]], align 2
+// CHECK-NEXT:    [[TMP6:%.*]] = cmpxchg i16* [[USX]], i16 [[TMP4]], i16 [[TMP5]] monotonic monotonic, align 2
+// CHECK-NEXT:    [[TMP7:%.*]] = extractvalue { i16, i1 } [[TMP6]], 0
+// CHECK-NEXT:    store i16 [[TMP7]], i16* [[USV]], align 2
+// CHECK-NEXT:    [[TMP8:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP9:%.*]] = atomicrmw umin i16* [[USX]], i16 [[TMP8]] monotonic, align 2
+// CHECK-NEXT:    [[TMP10:%.*]] = icmp ult i16 [[TMP9]], [[TMP8]]
+// CHECK-NEXT:    [[TMP11:%.*]] = select i1 [[TMP10]], i16 [[TMP8]], i16 [[TMP9]]
+// CHECK-NEXT:    store i16 [[TMP11]], i16* [[USV]], align 2
+// CHECK-NEXT:    [[TMP12:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP13:%.*]] = atomicrmw umax i16* [[USX]], i16 [[TMP12]] monotonic, align 2
+// CHECK-NEXT:    [[TMP14:%.*]] = icmp ugt i16 [[TMP13]], [[TMP12]]
+// CHECK-NEXT:    [[TMP15:%.*]] = select i1 [[TMP14]], i16 [[TMP12]], i16 [[TMP13]]
+// CHECK-NEXT:    store i16 [[TMP15]], i16* [[USV]], align 2
+// CHECK-NEXT:    [[TMP16:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP17:%.*]] = load i16, i16* [[USD]], align 2
+// CHECK-NEXT:    [[TMP18:%.*]] = cmpxchg i16* [[USX]], i16 [[TMP16]], i16 [[TMP17]] monotonic monotonic, align 2
+// CHECK-NEXT:    [[TMP19:%.*]] = extractvalue { i16, i1 } [[TMP18]], 0
+// CHECK-NEXT:    [[TMP20:%.*]] = extractvalue { i16, i1 } [[TMP18]], 1
+// CHECK-NEXT:    [[TMP21:%.*]] = select i1 [[TMP20]], i16 [[TMP16]], i16 [[TMP19]]
+// CHECK-NEXT:    store i16 [[TMP21]], i16* [[USV]], align 2
+// CHECK-NEXT:    [[TMP22:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP23:%.*]] = atomicrmw umin i16* [[USX]], i16 [[TMP22]] acq_rel, align 2
+// CHECK-NEXT:    store i16 [[TMP23]], i16* [[USV]], align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP24:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP25:%.*]] = atomicrmw umax i16* [[USX]], i16 [[TMP24]] acq_rel, align 2
+// CHECK-NEXT:    store i16 [[TMP25]], i16* [[USV]], align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP26:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP27:%.*]] = load i16, i16* [[USD]], align 2
+// CHECK-NEXT:    [[TMP28:%.*]] = cmpxchg i16* [[USX]], i16 [[TMP26]], i16 [[TMP27]] acq_rel acquire, align 2
+// CHECK-NEXT:    [[TMP29:%.*]] = extractvalue { i16, i1 } [[TMP28]], 0
+// CHECK-NEXT:    store i16 [[TMP29]], i16* [[USV]], align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP30:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP31:%.*]] = atomicrmw umin i16* [[USX]], i16 [[TMP30]] acq_rel, align 2
+// CHECK-NEXT:    [[TMP32:%.*]] = icmp ult i16 [[TMP31]], [[TMP30]]
+// CHECK-NEXT:    [[TMP33:%.*]] = select i1 [[TMP32]], i16 [[TMP30]], i16 [[TMP31]]
+// CHECK-NEXT:    store i16 [[TMP33]], i16* [[USV]], align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP34:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP35:%.*]] = atomicrmw umax i16* [[USX]], i16 [[TMP34]] acq_rel, align 2
+// CHECK-NEXT:    [[TMP36:%.*]] = icmp ugt i16 [[TMP35]], [[TMP34]]
+// CHECK-NEXT:    [[TMP37:%.*]] = select i1 [[TMP36]], i16 [[TMP34]], i16 [[TMP35]]
+// CHECK-NEXT:    store i16 [[TMP37]], i16* [[USV]], align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP38:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP39:%.*]] = load i16, i16* [[USD]], align 2
+// CHECK-NEXT:    [[TMP40:%.*]] = cmpxchg i16* [[USX]], i16 [[TMP38]], i16 [[TMP39]] acq_rel acquire, align 2
+// CHECK-NEXT:    [[TMP41:%.*]] = extractvalue { i16, i1 } [[TMP40]], 0
+// CHECK-NEXT:    [[TMP42:%.*]] = extractvalue { i16, i1 } [[TMP40]], 1
+// CHECK-NEXT:    [[TMP43:%.*]] = select i1 [[TMP42]], i16 [[TMP38]], i16 [[TMP41]]
+// CHECK-NEXT:    store i16 [[TMP43]], i16* [[USV]], align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP44:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP45:%.*]] = atomicrmw umin i16* [[USX]], i16 [[TMP44]] acquire, align 2
+// CHECK-NEXT:    store i16 [[TMP45]], i16* [[USV]], align 2
+// CHECK-NEXT:    [[TMP46:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP47:%.*]] = atomicrmw umax i16* [[USX]], i16 [[TMP46]] acquire, align 2
+// CHECK-NEXT:    store i16 [[TMP47]], i16* [[USV]], align 2
+// CHECK-NEXT:    [[TMP48:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP49:%.*]] = load i16, i16* [[USD]], align 2
+// CHECK-NEXT:    [[TMP50:%.*]] = cmpxchg i16* [[USX]], i16 [[TMP48]], i16 [[TMP49]] acquire acquire, align 2
+// CHECK-NEXT:    [[TMP51:%.*]] = extractvalue { i16, i1 } [[TMP50]], 0
+// CHECK-NEXT:    store i16 [[TMP51]], i16* [[USV]], align 2
+// CHECK-NEXT:    [[TMP52:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP53:%.*]] = atomicrmw umin i16* [[USX]], i16 [[TMP52]] acquire, align 2
+// CHECK-NEXT:    [[TMP54:%.*]] = icmp ult i16 [[TMP53]], [[TMP52]]
+// CHECK-NEXT:    [[TMP55:%.*]] = select i1 [[TMP54]], i16 [[TMP52]], i16 [[TMP53]]
+// CHECK-NEXT:    store i16 [[TMP55]], i16* [[USV]], align 2
+// CHECK-NEXT:    [[TMP56:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP57:%.*]] = atomicrmw umax i16* [[USX]], i16 [[TMP56]] acquire, align 2
+// CHECK-NEXT:    [[TMP58:%.*]] = icmp ugt i16 [[TMP57]], [[TMP56]]
+// CHECK-NEXT:    [[TMP59:%.*]] = select i1 [[TMP58]], i16 [[TMP56]], i16 [[TMP57]]
+// CHECK-NEXT:    store i16 [[TMP59]], i16* [[USV]], align 2
+// CHECK-NEXT:    [[TMP60:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP61:%.*]] = load i16, i16* [[USD]], align 2
+// CHECK-NEXT:    [[TMP62:%.*]] = cmpxchg i16* [[USX]], i16 [[TMP60]], i16 [[TMP61]] acquire acquire, align 2
+// CHECK-NEXT:    [[TMP63:%.*]] = extractvalue { i16, i1 } [[TMP62]], 0
+// CHECK-NEXT:    [[TMP64:%.*]] = extractvalue { i16, i1 } [[TMP62]], 1
+// CHECK-NEXT:    [[TMP65:%.*]] = select i1 [[TMP64]], i16 [[TMP60]], i16 [[TMP63]]
+// CHECK-NEXT:    store i16 [[TMP65]], i16* [[USV]], align 2
+// CHECK-NEXT:    [[TMP66:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP67:%.*]] = atomicrmw umin i16* [[USX]], i16 [[TMP66]] monotonic, align 2
+// CHECK-NEXT:    store i16 [[TMP67]], i16* [[USV]], align 2
+// CHECK-NEXT:    [[TMP68:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP69:%.*]] = atomicrmw umax i16* [[USX]], i16 [[TMP68]] monotonic, align 2
+// CHECK-NEXT:    store i16 [[TMP69]], i16* [[USV]], align 2
+// CHECK-NEXT:    [[TMP70:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP71:%.*]] = load i16, i16* [[USD]], align 2
+// CHECK-NEXT:    [[TMP72:%.*]] = cmpxchg i16* [[USX]], i16 [[TMP70]], i16 [[TMP71]] monotonic monotonic, align 2
+// CHECK-NEXT:    [[TMP73:%.*]] = extractvalue { i16, i1 } [[TMP72]], 0
+// CHECK-NEXT:    store i16 [[TMP73]], i16* [[USV]], align 2
+// CHECK-NEXT:    [[TMP74:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP75:%.*]] = atomicrmw umin i16* [[USX]], i16 [[TMP74]] monotonic, align 2
+// CHECK-NEXT:    [[TMP76:%.*]] = icmp ult i16 [[TMP75]], [[TMP74]]
+// CHECK-NEXT:    [[TMP77:%.*]] = select i1 [[TMP76]], i16 [[TMP74]], i16 [[TMP75]]
+// CHECK-NEXT:    store i16 [[TMP77]], i16* [[USV]], align 2
+// CHECK-NEXT:    [[TMP78:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP79:%.*]] = atomicrmw umax i16* [[USX]], i16 [[TMP78]] monotonic, align 2
+// CHECK-NEXT:    [[TMP80:%.*]] = icmp ugt i16 [[TMP79]], [[TMP78]]
+// CHECK-NEXT:    [[TMP81:%.*]] = select i1 [[TMP80]], i16 [[TMP78]], i16 [[TMP79]]
+// CHECK-NEXT:    store i16 [[TMP81]], i16* [[USV]], align 2
+// CHECK-NEXT:    [[TMP82:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP83:%.*]] = load i16, i16* [[USD]], align 2
+// CHECK-NEXT:    [[TMP84:%.*]] = cmpxchg i16* [[USX]], i16 [[TMP82]], i16 [[TMP83]] monotonic monotonic, align 2
+// CHECK-NEXT:    [[TMP85:%.*]] = extractvalue { i16, i1 } [[TMP84]], 0
+// CHECK-NEXT:    [[TMP86:%.*]] = extractvalue { i16, i1 } [[TMP84]], 1
+// CHECK-NEXT:    [[TMP87:%.*]] = select i1 [[TMP86]], i16 [[TMP82]], i16 [[TMP85]]
+// CHECK-NEXT:    store i16 [[TMP87]], i16* [[USV]], align 2
+// CHECK-NEXT:    [[TMP88:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP89:%.*]] = atomicrmw umin i16* [[USX]], i16 [[TMP88]] release, align 2
+// CHECK-NEXT:    store i16 [[TMP89]], i16* [[USV]], align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP90:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP91:%.*]] = atomicrmw umax i16* [[USX]], i16 [[TMP90]] release, align 2
+// CHECK-NEXT:    store i16 [[TMP91]], i16* [[USV]], align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP92:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP93:%.*]] = load i16, i16* [[USD]], align 2
+// CHECK-NEXT:    [[TMP94:%.*]] = cmpxchg i16* [[USX]], i16 [[TMP92]], i16 [[TMP93]] release monotonic, align 2
+// CHECK-NEXT:    [[TMP95:%.*]] = extractvalue { i16, i1 } [[TMP94]], 0
+// CHECK-NEXT:    store i16 [[TMP95]], i16* [[USV]], align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP96:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP97:%.*]] = atomicrmw umin i16* [[USX]], i16 [[TMP96]] release, align 2
+// CHECK-NEXT:    [[TMP98:%.*]] = icmp ult i16 [[TMP97]], [[TMP96]]
+// CHECK-NEXT:    [[TMP99:%.*]] = select i1 [[TMP98]], i16 [[TMP96]], i16 [[TMP97]]
+// CHECK-NEXT:    store i16 [[TMP99]], i16* [[USV]], align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP100:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP101:%.*]] = atomicrmw umax i16* [[USX]], i16 [[TMP100]] release, align 2
+// CHECK-NEXT:    [[TMP102:%.*]] = icmp ugt i16 [[TMP101]], [[TMP100]]
+// CHECK-NEXT:    [[TMP103:%.*]] = select i1 [[TMP102]], i16 [[TMP100]], i16 [[TMP101]]
+// CHECK-NEXT:    store i16 [[TMP103]], i16* [[USV]], align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP104:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP105:%.*]] = load i16, i16* [[USD]], align 2
+// CHECK-NEXT:    [[TMP106:%.*]] = cmpxchg i16* [[USX]], i16 [[TMP104]], i16 [[TMP105]] release monotonic, align 2
+// CHECK-NEXT:    [[TMP107:%.*]] = extractvalue { i16, i1 } [[TMP106]], 0
+// CHECK-NEXT:    [[TMP108:%.*]] = extractvalue { i16, i1 } [[TMP106]], 1
+// CHECK-NEXT:    [[TMP109:%.*]] = select i1 [[TMP108]], i16 [[TMP104]], i16 [[TMP107]]
+// CHECK-NEXT:    store i16 [[TMP109]], i16* [[USV]], align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP110:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP111:%.*]] = atomicrmw umin i16* [[USX]], i16 [[TMP110]] seq_cst, align 2
+// CHECK-NEXT:    store i16 [[TMP111]], i16* [[USV]], align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP112:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP113:%.*]] = atomicrmw umax i16* [[USX]], i16 [[TMP112]] seq_cst, align 2
+// CHECK-NEXT:    store i16 [[TMP113]], i16* [[USV]], align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP114:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP115:%.*]] = load i16, i16* [[USD]], align 2
+// CHECK-NEXT:    [[TMP116:%.*]] = cmpxchg i16* [[USX]], i16 [[TMP114]], i16 [[TMP115]] seq_cst seq_cst, align 2
+// CHECK-NEXT:    [[TMP117:%.*]] = extractvalue { i16, i1 } [[TMP116]], 0
+// CHECK-NEXT:    store i16 [[TMP117]], i16* [[USV]], align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP118:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP119:%.*]] = atomicrmw umin i16* [[USX]], i16 [[TMP118]] seq_cst, align 2
+// CHECK-NEXT:    [[TMP120:%.*]] = icmp ult i16 [[TMP119]], [[TMP118]]
+// CHECK-NEXT:    [[TMP121:%.*]] = select i1 [[TMP120]], i16 [[TMP118]], i16 [[TMP119]]
+// CHECK-NEXT:    store i16 [[TMP121]], i16* [[USV]], align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP122:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP123:%.*]] = atomicrmw umax i16* [[USX]], i16 [[TMP122]] seq_cst, align 2
+// CHECK-NEXT:    [[TMP124:%.*]] = icmp ugt i16 [[TMP123]], [[TMP122]]
+// CHECK-NEXT:    [[TMP125:%.*]] = select i1 [[TMP124]], i16 [[TMP122]], i16 [[TMP123]]
+// CHECK-NEXT:    store i16 [[TMP125]], i16* [[USV]], align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP126:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP127:%.*]] = load i16, i16* [[USD]], align 2
+// CHECK-NEXT:    [[TMP128:%.*]] = cmpxchg i16* [[USX]], i16 [[TMP126]], i16 [[TMP127]] seq_cst seq_cst, align 2
+// CHECK-NEXT:    [[TMP129:%.*]] = extractvalue { i16, i1 } [[TMP128]], 0
+// CHECK-NEXT:    [[TMP130:%.*]] = extractvalue { i16, i1 } [[TMP128]], 1
+// CHECK-NEXT:    [[TMP131:%.*]] = select i1 [[TMP130]], i16 [[TMP126]], i16 [[TMP129]]
+// CHECK-NEXT:    store i16 [[TMP131]], i16* [[USV]], align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP132:%.*]] = load i16, i16* [[USV]], align 2
+// CHECK-NEXT:    ret i16 [[TMP132]]
+//
+//
+// CHECK-LABEL: define {{[^@]+}}@ixevd
+// CHECK-SAME: () #[[ATTR0]] {
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[IX:%.*]] = alloca i32, align 4
+// CHECK-NEXT:    [[IV:%.*]] = alloca i32, align 4
+// CHECK-NEXT:    [[IE:%.*]] = alloca i32, align 4
+// CHECK-NEXT:    [[ID:%.*]] = alloca i32, align 4
+// CHECK-NEXT:    [[TMP0:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP1:%.*]] = atomicrmw min i32* [[IX]], i32 [[TMP0]] monotonic, align 4
+// CHECK-NEXT:    store i32 [[TMP1]], i32* [[IV]], align 4
+// CHECK-NEXT:    [[TMP2:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP3:%.*]] = atomicrmw max i32* [[IX]], i32 [[TMP2]] monotonic, align 4
+// CHECK-NEXT:    store i32 [[TMP3]], i32* [[IV]], align 4
+// CHECK-NEXT:    [[TMP4:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP5:%.*]] = load i32, i32* [[ID]], align 4
+// CHECK-NEXT:    [[TMP6:%.*]] = cmpxchg i32* [[IX]], i32 [[TMP4]], i32 [[TMP5]] monotonic monotonic, align 4
+// CHECK-NEXT:    [[TMP7:%.*]] = extractvalue { i32, i1 } [[TMP6]], 0
+// CHECK-NEXT:    store i32 [[TMP7]], i32* [[IV]], align 4
+// CHECK-NEXT:    [[TMP8:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP9:%.*]] = atomicrmw min i32* [[IX]], i32 [[TMP8]] monotonic, align 4
+// CHECK-NEXT:    [[TMP10:%.*]] = icmp slt i32 [[TMP9]], [[TMP8]]
+// CHECK-NEXT:    [[TMP11:%.*]] = select i1 [[TMP10]], i32 [[TMP8]], i32 [[TMP9]]
+// CHECK-NEXT:    store i32 [[TMP11]], i32* [[IV]], align 4
+// CHECK-NEXT:    [[TMP12:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP13:%.*]] = atomicrmw max i32* [[IX]], i32 [[TMP12]] monotonic, align 4
+// CHECK-NEXT:    [[TMP14:%.*]] = icmp sgt i32 [[TMP13]], [[TMP12]]
+// CHECK-NEXT:    [[TMP15:%.*]] = select i1 [[TMP14]], i32 [[TMP12]], i32 [[TMP13]]
+// CHECK-NEXT:    store i32 [[TMP15]], i32* [[IV]], align 4
+// CHECK-NEXT:    [[TMP16:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP17:%.*]] = load i32, i32* [[ID]], align 4
+// CHECK-NEXT:    [[TMP18:%.*]] = cmpxchg i32* [[IX]], i32 [[TMP16]], i32 [[TMP17]] monotonic monotonic, align 4
+// CHECK-NEXT:    [[TMP19:%.*]] = extractvalue { i32, i1 } [[TMP18]], 0
+// CHECK-NEXT:    [[TMP20:%.*]] = extractvalue { i32, i1 } [[TMP18]], 1
+// CHECK-NEXT:    [[TMP21:%.*]] = select i1 [[TMP20]], i32 [[TMP16]], i32 [[TMP19]]
+// CHECK-NEXT:    store i32 [[TMP21]], i32* [[IV]], align 4
+// CHECK-NEXT:    [[TMP22:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP23:%.*]] = atomicrmw min i32* [[IX]], i32 [[TMP22]] acq_rel, align 4
+// CHECK-NEXT:    store i32 [[TMP23]], i32* [[IV]], align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP24:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP25:%.*]] = atomicrmw max i32* [[IX]], i32 [[TMP24]] acq_rel, align 4
+// CHECK-NEXT:    store i32 [[TMP25]], i32* [[IV]], align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP26:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP27:%.*]] = load i32, i32* [[ID]], align 4
+// CHECK-NEXT:    [[TMP28:%.*]] = cmpxchg i32* [[IX]], i32 [[TMP26]], i32 [[TMP27]] acq_rel acquire, align 4
+// CHECK-NEXT:    [[TMP29:%.*]] = extractvalue { i32, i1 } [[TMP28]], 0
+// CHECK-NEXT:    store i32 [[TMP29]], i32* [[IV]], align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP30:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP31:%.*]] = atomicrmw min i32* [[IX]], i32 [[TMP30]] acq_rel, align 4
+// CHECK-NEXT:    [[TMP32:%.*]] = icmp slt i32 [[TMP31]], [[TMP30]]
+// CHECK-NEXT:    [[TMP33:%.*]] = select i1 [[TMP32]], i32 [[TMP30]], i32 [[TMP31]]
+// CHECK-NEXT:    store i32 [[TMP33]], i32* [[IV]], align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP34:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP35:%.*]] = atomicrmw max i32* [[IX]], i32 [[TMP34]] acq_rel, align 4
+// CHECK-NEXT:    [[TMP36:%.*]] = icmp sgt i32 [[TMP35]], [[TMP34]]
+// CHECK-NEXT:    [[TMP37:%.*]] = select i1 [[TMP36]], i32 [[TMP34]], i32 [[TMP35]]
+// CHECK-NEXT:    store i32 [[TMP37]], i32* [[IV]], align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP38:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP39:%.*]] = load i32, i32* [[ID]], align 4
+// CHECK-NEXT:    [[TMP40:%.*]] = cmpxchg i32* [[IX]], i32 [[TMP38]], i32 [[TMP39]] acq_rel acquire, align 4
+// CHECK-NEXT:    [[TMP41:%.*]] = extractvalue { i32, i1 } [[TMP40]], 0
+// CHECK-NEXT:    [[TMP42:%.*]] = extractvalue { i32, i1 } [[TMP40]], 1
+// CHECK-NEXT:    [[TMP43:%.*]] = select i1 [[TMP42]], i32 [[TMP38]], i32 [[TMP41]]
+// CHECK-NEXT:    store i32 [[TMP43]], i32* [[IV]], align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP44:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP45:%.*]] = atomicrmw min i32* [[IX]], i32 [[TMP44]] acquire, align 4
+// CHECK-NEXT:    store i32 [[TMP45]], i32* [[IV]], align 4
+// CHECK-NEXT:    [[TMP46:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP47:%.*]] = atomicrmw max i32* [[IX]], i32 [[TMP46]] acquire, align 4
+// CHECK-NEXT:    store i32 [[TMP47]], i32* [[IV]], align 4
+// CHECK-NEXT:    [[TMP48:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP49:%.*]] = load i32, i32* [[ID]], align 4
+// CHECK-NEXT:    [[TMP50:%.*]] = cmpxchg i32* [[IX]], i32 [[TMP48]], i32 [[TMP49]] acquire acquire, align 4
+// CHECK-NEXT:    [[TMP51:%.*]] = extractvalue { i32, i1 } [[TMP50]], 0
+// CHECK-NEXT:    store i32 [[TMP51]], i32* [[IV]], align 4
+// CHECK-NEXT:    [[TMP52:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP53:%.*]] = atomicrmw min i32* [[IX]], i32 [[TMP52]] acquire, align 4
+// CHECK-NEXT:    [[TMP54:%.*]] = icmp slt i32 [[TMP53]], [[TMP52]]
+// CHECK-NEXT:    [[TMP55:%.*]] = select i1 [[TMP54]], i32 [[TMP52]], i32 [[TMP53]]
+// CHECK-NEXT:    store i32 [[TMP55]], i32* [[IV]], align 4
+// CHECK-NEXT:    [[TMP56:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP57:%.*]] = atomicrmw max i32* [[IX]], i32 [[TMP56]] acquire, align 4
+// CHECK-NEXT:    [[TMP58:%.*]] = icmp sgt i32 [[TMP57]], [[TMP56]]
+// CHECK-NEXT:    [[TMP59:%.*]] = select i1 [[TMP58]], i32 [[TMP56]], i32 [[TMP57]]
+// CHECK-NEXT:    store i32 [[TMP59]], i32* [[IV]], align 4
+// CHECK-NEXT:    [[TMP60:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP61:%.*]] = load i32, i32* [[ID]], align 4
+// CHECK-NEXT:    [[TMP62:%.*]] = cmpxchg i32* [[IX]], i32 [[TMP60]], i32 [[TMP61]] acquire acquire, align 4
+// CHECK-NEXT:    [[TMP63:%.*]] = extractvalue { i32, i1 } [[TMP62]], 0
+// CHECK-NEXT:    [[TMP64:%.*]] = extractvalue { i32, i1 } [[TMP62]], 1
+// CHECK-NEXT:    [[TMP65:%.*]] = select i1 [[TMP64]], i32 [[TMP60]], i32 [[TMP63]]
+// CHECK-NEXT:    store i32 [[TMP65]], i32* [[IV]], align 4
+// CHECK-NEXT:    [[TMP66:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP67:%.*]] = atomicrmw min i32* [[IX]], i32 [[TMP66]] monotonic, align 4
+// CHECK-NEXT:    store i32 [[TMP67]], i32* [[IV]], align 4
+// CHECK-NEXT:    [[TMP68:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP69:%.*]] = atomicrmw max i32* [[IX]], i32 [[TMP68]] monotonic, align 4
+// CHECK-NEXT:    store i32 [[TMP69]], i32* [[IV]], align 4
+// CHECK-NEXT:    [[TMP70:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP71:%.*]] = load i32, i32* [[ID]], align 4
+// CHECK-NEXT:    [[TMP72:%.*]] = cmpxchg i32* [[IX]], i32 [[TMP70]], i32 [[TMP71]] monotonic monotonic, align 4
+// CHECK-NEXT:    [[TMP73:%.*]] = extractvalue { i32, i1 } [[TMP72]], 0
+// CHECK-NEXT:    store i32 [[TMP73]], i32* [[IV]], align 4
+// CHECK-NEXT:    [[TMP74:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP75:%.*]] = atomicrmw min i32* [[IX]], i32 [[TMP74]] monotonic, align 4
+// CHECK-NEXT:    [[TMP76:%.*]] = icmp slt i32 [[TMP75]], [[TMP74]]
+// CHECK-NEXT:    [[TMP77:%.*]] = select i1 [[TMP76]], i32 [[TMP74]], i32 [[TMP75]]
+// CHECK-NEXT:    store i32 [[TMP77]], i32* [[IV]], align 4
+// CHECK-NEXT:    [[TMP78:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP79:%.*]] = atomicrmw max i32* [[IX]], i32 [[TMP78]] monotonic, align 4
+// CHECK-NEXT:    [[TMP80:%.*]] = icmp sgt i32 [[TMP79]], [[TMP78]]
+// CHECK-NEXT:    [[TMP81:%.*]] = select i1 [[TMP80]], i32 [[TMP78]], i32 [[TMP79]]
+// CHECK-NEXT:    store i32 [[TMP81]], i32* [[IV]], align 4
+// CHECK-NEXT:    [[TMP82:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP83:%.*]] = load i32, i32* [[ID]], align 4
+// CHECK-NEXT:    [[TMP84:%.*]] = cmpxchg i32* [[IX]], i32 [[TMP82]], i32 [[TMP83]] monotonic monotonic, align 4
+// CHECK-NEXT:    [[TMP85:%.*]] = extractvalue { i32, i1 } [[TMP84]], 0
+// CHECK-NEXT:    [[TMP86:%.*]] = extractvalue { i32, i1 } [[TMP84]], 1
+// CHECK-NEXT:    [[TMP87:%.*]] = select i1 [[TMP86]], i32 [[TMP82]], i32 [[TMP85]]
+// CHECK-NEXT:    store i32 [[TMP87]], i32* [[IV]], align 4
+// CHECK-NEXT:    [[TMP88:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP89:%.*]] = atomicrmw min i32* [[IX]], i32 [[TMP88]] release, align 4
+// CHECK-NEXT:    store i32 [[TMP89]], i32* [[IV]], align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP90:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP91:%.*]] = atomicrmw max i32* [[IX]], i32 [[TMP90]] release, align 4
+// CHECK-NEXT:    store i32 [[TMP91]], i32* [[IV]], align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP92:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP93:%.*]] = load i32, i32* [[ID]], align 4
+// CHECK-NEXT:    [[TMP94:%.*]] = cmpxchg i32* [[IX]], i32 [[TMP92]], i32 [[TMP93]] release monotonic, align 4
+// CHECK-NEXT:    [[TMP95:%.*]] = extractvalue { i32, i1 } [[TMP94]], 0
+// CHECK-NEXT:    store i32 [[TMP95]], i32* [[IV]], align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP96:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP97:%.*]] = atomicrmw min i32* [[IX]], i32 [[TMP96]] release, align 4
+// CHECK-NEXT:    [[TMP98:%.*]] = icmp slt i32 [[TMP97]], [[TMP96]]
+// CHECK-NEXT:    [[TMP99:%.*]] = select i1 [[TMP98]], i32 [[TMP96]], i32 [[TMP97]]
+// CHECK-NEXT:    store i32 [[TMP99]], i32* [[IV]], align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP100:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP101:%.*]] = atomicrmw max i32* [[IX]], i32 [[TMP100]] release, align 4
+// CHECK-NEXT:    [[TMP102:%.*]] = icmp sgt i32 [[TMP101]], [[TMP100]]
+// CHECK-NEXT:    [[TMP103:%.*]] = select i1 [[TMP102]], i32 [[TMP100]], i32 [[TMP101]]
+// CHECK-NEXT:    store i32 [[TMP103]], i32* [[IV]], align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP104:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP105:%.*]] = load i32, i32* [[ID]], align 4
+// CHECK-NEXT:    [[TMP106:%.*]] = cmpxchg i32* [[IX]], i32 [[TMP104]], i32 [[TMP105]] release monotonic, align 4
+// CHECK-NEXT:    [[TMP107:%.*]] = extractvalue { i32, i1 } [[TMP106]], 0
+// CHECK-NEXT:    [[TMP108:%.*]] = extractvalue { i32, i1 } [[TMP106]], 1
+// CHECK-NEXT:    [[TMP109:%.*]] = select i1 [[TMP108]], i32 [[TMP104]], i32 [[TMP107]]
+// CHECK-NEXT:    store i32 [[TMP109]], i32* [[IV]], align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP110:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP111:%.*]] = atomicrmw min i32* [[IX]], i32 [[TMP110]] seq_cst, align 4
+// CHECK-NEXT:    store i32 [[TMP111]], i32* [[IV]], align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP112:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP113:%.*]] = atomicrmw max i32* [[IX]], i32 [[TMP112]] seq_cst, align 4
+// CHECK-NEXT:    store i32 [[TMP113]], i32* [[IV]], align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP114:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP115:%.*]] = load i32, i32* [[ID]], align 4
+// CHECK-NEXT:    [[TMP116:%.*]] = cmpxchg i32* [[IX]], i32 [[TMP114]], i32 [[TMP115]] seq_cst seq_cst, align 4
+// CHECK-NEXT:    [[TMP117:%.*]] = extractvalue { i32, i1 } [[TMP116]], 0
+// CHECK-NEXT:    store i32 [[TMP117]], i32* [[IV]], align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP118:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP119:%.*]] = atomicrmw min i32* [[IX]], i32 [[TMP118]] seq_cst, align 4
+// CHECK-NEXT:    [[TMP120:%.*]] = icmp slt i32 [[TMP119]], [[TMP118]]
+// CHECK-NEXT:    [[TMP121:%.*]] = select i1 [[TMP120]], i32 [[TMP118]], i32 [[TMP119]]
+// CHECK-NEXT:    store i32 [[TMP121]], i32* [[IV]], align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP122:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP123:%.*]] = atomicrmw max i32* [[IX]], i32 [[TMP122]] seq_cst, align 4
+// CHECK-NEXT:    [[TMP124:%.*]] = icmp sgt i32 [[TMP123]], [[TMP122]]
+// CHECK-NEXT:    [[TMP125:%.*]] = select i1 [[TMP124]], i32 [[TMP122]], i32 [[TMP123]]
+// CHECK-NEXT:    store i32 [[TMP125]], i32* [[IV]], align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP126:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP127:%.*]] = load i32, i32* [[ID]], align 4
+// CHECK-NEXT:    [[TMP128:%.*]] = cmpxchg i32* [[IX]], i32 [[TMP126]], i32 [[TMP127]] seq_cst seq_cst, align 4
+// CHECK-NEXT:    [[TMP129:%.*]] = extractvalue { i32, i1 } [[TMP128]], 0
+// CHECK-NEXT:    [[TMP130:%.*]] = extractvalue { i32, i1 } [[TMP128]], 1
+// CHECK-NEXT:    [[TMP131:%.*]] = select i1 [[TMP130]], i32 [[TMP126]], i32 [[TMP129]]
+// CHECK-NEXT:    store i32 [[TMP131]], i32* [[IV]], align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP132:%.*]] = load i32, i32* [[IV]], align 4
+// CHECK-NEXT:    ret i32 [[TMP132]]
+//
+//
+// CHECK-LABEL: define {{[^@]+}}@uixevd
+// CHECK-SAME: () #[[ATTR0]] {
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[UIX:%.*]] = alloca i32, align 4
+// CHECK-NEXT:    [[UIV:%.*]] = alloca i32, align 4
+// CHECK-NEXT:    [[UIE:%.*]] = alloca i32, align 4
+// CHECK-NEXT:    [[UID:%.*]] = alloca i32, align 4
+// CHECK-NEXT:    [[TMP0:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP1:%.*]] = atomicrmw umin i32* [[UIX]], i32 [[TMP0]] monotonic, align 4
+// CHECK-NEXT:    store i32 [[TMP1]], i32* [[UIV]], align 4
+// CHECK-NEXT:    [[TMP2:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP3:%.*]] = atomicrmw umax i32* [[UIX]], i32 [[TMP2]] monotonic, align 4
+// CHECK-NEXT:    store i32 [[TMP3]], i32* [[UIV]], align 4
+// CHECK-NEXT:    [[TMP4:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP5:%.*]] = load i32, i32* [[UID]], align 4
+// CHECK-NEXT:    [[TMP6:%.*]] = cmpxchg i32* [[UIX]], i32 [[TMP4]], i32 [[TMP5]] monotonic monotonic, align 4
+// CHECK-NEXT:    [[TMP7:%.*]] = extractvalue { i32, i1 } [[TMP6]], 0
+// CHECK-NEXT:    store i32 [[TMP7]], i32* [[UIV]], align 4
+// CHECK-NEXT:    [[TMP8:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP9:%.*]] = atomicrmw umin i32* [[UIX]], i32 [[TMP8]] monotonic, align 4
+// CHECK-NEXT:    [[TMP10:%.*]] = icmp ult i32 [[TMP9]], [[TMP8]]
+// CHECK-NEXT:    [[TMP11:%.*]] = select i1 [[TMP10]], i32 [[TMP8]], i32 [[TMP9]]
+// CHECK-NEXT:    store i32 [[TMP11]], i32* [[UIV]], align 4
+// CHECK-NEXT:    [[TMP12:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP13:%.*]] = atomicrmw umax i32* [[UIX]], i32 [[TMP12]] monotonic, align 4
+// CHECK-NEXT:    [[TMP14:%.*]] = icmp ugt i32 [[TMP13]], [[TMP12]]
+// CHECK-NEXT:    [[TMP15:%.*]] = select i1 [[TMP14]], i32 [[TMP12]], i32 [[TMP13]]
+// CHECK-NEXT:    store i32 [[TMP15]], i32* [[UIV]], align 4
+// CHECK-NEXT:    [[TMP16:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP17:%.*]] = load i32, i32* [[UID]], align 4
+// CHECK-NEXT:    [[TMP18:%.*]] = cmpxchg i32* [[UIX]], i32 [[TMP16]], i32 [[TMP17]] monotonic monotonic, align 4
+// CHECK-NEXT:    [[TMP19:%.*]] = extractvalue { i32, i1 } [[TMP18]], 0
+// CHECK-NEXT:    [[TMP20:%.*]] = extractvalue { i32, i1 } [[TMP18]], 1
+// CHECK-NEXT:    [[TMP21:%.*]] = select i1 [[TMP20]], i32 [[TMP16]], i32 [[TMP19]]
+// CHECK-NEXT:    store i32 [[TMP21]], i32* [[UIV]], align 4
+// CHECK-NEXT:    [[TMP22:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP23:%.*]] = atomicrmw umin i32* [[UIX]], i32 [[TMP22]] acq_rel, align 4
+// CHECK-NEXT:    store i32 [[TMP23]], i32* [[UIV]], align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP24:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP25:%.*]] = atomicrmw umax i32* [[UIX]], i32 [[TMP24]] acq_rel, align 4
+// CHECK-NEXT:    store i32 [[TMP25]], i32* [[UIV]], align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP26:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP27:%.*]] = load i32, i32* [[UID]], align 4
+// CHECK-NEXT:    [[TMP28:%.*]] = cmpxchg i32* [[UIX]], i32 [[TMP26]], i32 [[TMP27]] acq_rel acquire, align 4
+// CHECK-NEXT:    [[TMP29:%.*]] = extractvalue { i32, i1 } [[TMP28]], 0
+// CHECK-NEXT:    store i32 [[TMP29]], i32* [[UIV]], align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP30:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP31:%.*]] = atomicrmw umin i32* [[UIX]], i32 [[TMP30]] acq_rel, align 4
+// CHECK-NEXT:    [[TMP32:%.*]] = icmp ult i32 [[TMP31]], [[TMP30]]
+// CHECK-NEXT:    [[TMP33:%.*]] = select i1 [[TMP32]], i32 [[TMP30]], i32 [[TMP31]]
+// CHECK-NEXT:    store i32 [[TMP33]], i32* [[UIV]], align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP34:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP35:%.*]] = atomicrmw umax i32* [[UIX]], i32 [[TMP34]] acq_rel, align 4
+// CHECK-NEXT:    [[TMP36:%.*]] = icmp ugt i32 [[TMP35]], [[TMP34]]
+// CHECK-NEXT:    [[TMP37:%.*]] = select i1 [[TMP36]], i32 [[TMP34]], i32 [[TMP35]]
+// CHECK-NEXT:    store i32 [[TMP37]], i32* [[UIV]], align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP38:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP39:%.*]] = load i32, i32* [[UID]], align 4
+// CHECK-NEXT:    [[TMP40:%.*]] = cmpxchg i32* [[UIX]], i32 [[TMP38]], i32 [[TMP39]] acq_rel acquire, align 4
+// CHECK-NEXT:    [[TMP41:%.*]] = extractvalue { i32, i1 } [[TMP40]], 0
+// CHECK-NEXT:    [[TMP42:%.*]] = extractvalue { i32, i1 } [[TMP40]], 1
+// CHECK-NEXT:    [[TMP43:%.*]] = select i1 [[TMP42]], i32 [[TMP38]], i32 [[TMP41]]
+// CHECK-NEXT:    store i32 [[TMP43]], i32* [[UIV]], align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP44:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP45:%.*]] = atomicrmw umin i32* [[UIX]], i32 [[TMP44]] acquire, align 4
+// CHECK-NEXT:    store i32 [[TMP45]], i32* [[UIV]], align 4
+// CHECK-NEXT:    [[TMP46:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP47:%.*]] = atomicrmw umax i32* [[UIX]], i32 [[TMP46]] acquire, align 4
+// CHECK-NEXT:    store i32 [[TMP47]], i32* [[UIV]], align 4
+// CHECK-NEXT:    [[TMP48:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP49:%.*]] = load i32, i32* [[UID]], align 4
+// CHECK-NEXT:    [[TMP50:%.*]] = cmpxchg i32* [[UIX]], i32 [[TMP48]], i32 [[TMP49]] acquire acquire, align 4
+// CHECK-NEXT:    [[TMP51:%.*]] = extractvalue { i32, i1 } [[TMP50]], 0
+// CHECK-NEXT:    store i32 [[TMP51]], i32* [[UIV]], align 4
+// CHECK-NEXT:    [[TMP52:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP53:%.*]] = atomicrmw umin i32* [[UIX]], i32 [[TMP52]] acquire, align 4
+// CHECK-NEXT:    [[TMP54:%.*]] = icmp ult i32 [[TMP53]], [[TMP52]]
+// CHECK-NEXT:    [[TMP55:%.*]] = select i1 [[TMP54]], i32 [[TMP52]], i32 [[TMP53]]
+// CHECK-NEXT:    store i32 [[TMP55]], i32* [[UIV]], align 4
+// CHECK-NEXT:    [[TMP56:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP57:%.*]] = atomicrmw umax i32* [[UIX]], i32 [[TMP56]] acquire, align 4
+// CHECK-NEXT:    [[TMP58:%.*]] = icmp ugt i32 [[TMP57]], [[TMP56]]
+// CHECK-NEXT:    [[TMP59:%.*]] = select i1 [[TMP58]], i32 [[TMP56]], i32 [[TMP57]]
+// CHECK-NEXT:    store i32 [[TMP59]], i32* [[UIV]], align 4
+// CHECK-NEXT:    [[TMP60:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP61:%.*]] = load i32, i32* [[UID]], align 4
+// CHECK-NEXT:    [[TMP62:%.*]] = cmpxchg i32* [[UIX]], i32 [[TMP60]], i32 [[TMP61]] acquire acquire, align 4
+// CHECK-NEXT:    [[TMP63:%.*]] = extractvalue { i32, i1 } [[TMP62]], 0
+// CHECK-NEXT:    [[TMP64:%.*]] = extractvalue { i32, i1 } [[TMP62]], 1
+// CHECK-NEXT:    [[TMP65:%.*]] = select i1 [[TMP64]], i32 [[TMP60]], i32 [[TMP63]]
+// CHECK-NEXT:    store i32 [[TMP65]], i32* [[UIV]], align 4
+// CHECK-NEXT:    [[TMP66:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP67:%.*]] = atomicrmw umin i32* [[UIX]], i32 [[TMP66]] monotonic, align 4
+// CHECK-NEXT:    store i32 [[TMP67]], i32* [[UIV]], align 4
+// CHECK-NEXT:    [[TMP68:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP69:%.*]] = atomicrmw umax i32* [[UIX]], i32 [[TMP68]] monotonic, align 4
+// CHECK-NEXT:    store i32 [[TMP69]], i32* [[UIV]], align 4
+// CHECK-NEXT:    [[TMP70:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP71:%.*]] = load i32, i32* [[UID]], align 4
+// CHECK-NEXT:    [[TMP72:%.*]] = cmpxchg i32* [[UIX]], i32 [[TMP70]], i32 [[TMP71]] monotonic monotonic, align 4
+// CHECK-NEXT:    [[TMP73:%.*]] = extractvalue { i32, i1 } [[TMP72]], 0
+// CHECK-NEXT:    store i32 [[TMP73]], i32* [[UIV]], align 4
+// CHECK-NEXT:    [[TMP74:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP75:%.*]] = atomicrmw umin i32* [[UIX]], i32 [[TMP74]] monotonic, align 4
+// CHECK-NEXT:    [[TMP76:%.*]] = icmp ult i32 [[TMP75]], [[TMP74]]
+// CHECK-NEXT:    [[TMP77:%.*]] = select i1 [[TMP76]], i32 [[TMP74]], i32 [[TMP75]]
+// CHECK-NEXT:    store i32 [[TMP77]], i32* [[UIV]], align 4
+// CHECK-NEXT:    [[TMP78:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP79:%.*]] = atomicrmw umax i32* [[UIX]], i32 [[TMP78]] monotonic, align 4
+// CHECK-NEXT:    [[TMP80:%.*]] = icmp ugt i32 [[TMP79]], [[TMP78]]
+// CHECK-NEXT:    [[TMP81:%.*]] = select i1 [[TMP80]], i32 [[TMP78]], i32 [[TMP79]]
+// CHECK-NEXT:    store i32 [[TMP81]], i32* [[UIV]], align 4
+// CHECK-NEXT:    [[TMP82:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP83:%.*]] = load i32, i32* [[UID]], align 4
+// CHECK-NEXT:    [[TMP84:%.*]] = cmpxchg i32* [[UIX]], i32 [[TMP82]], i32 [[TMP83]] monotonic monotonic, align 4
+// CHECK-NEXT:    [[TMP85:%.*]] = extractvalue { i32, i1 } [[TMP84]], 0
+// CHECK-NEXT:    [[TMP86:%.*]] = extractvalue { i32, i1 } [[TMP84]], 1
+// CHECK-NEXT:    [[TMP87:%.*]] = select i1 [[TMP86]], i32 [[TMP82]], i32 [[TMP85]]
+// CHECK-NEXT:    store i32 [[TMP87]], i32* [[UIV]], align 4
+// CHECK-NEXT:    [[TMP88:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP89:%.*]] = atomicrmw umin i32* [[UIX]], i32 [[TMP88]] release, align 4
+// CHECK-NEXT:    store i32 [[TMP89]], i32* [[UIV]], align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP90:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP91:%.*]] = atomicrmw umax i32* [[UIX]], i32 [[TMP90]] release, align 4
+// CHECK-NEXT:    store i32 [[TMP91]], i32* [[UIV]], align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP92:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP93:%.*]] = load i32, i32* [[UID]], align 4
+// CHECK-NEXT:    [[TMP94:%.*]] = cmpxchg i32* [[UIX]], i32 [[TMP92]], i32 [[TMP93]] release monotonic, align 4
+// CHECK-NEXT:    [[TMP95:%.*]] = extractvalue { i32, i1 } [[TMP94]], 0
+// CHECK-NEXT:    store i32 [[TMP95]], i32* [[UIV]], align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP96:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP97:%.*]] = atomicrmw umin i32* [[UIX]], i32 [[TMP96]] release, align 4
+// CHECK-NEXT:    [[TMP98:%.*]] = icmp ult i32 [[TMP97]], [[TMP96]]
+// CHECK-NEXT:    [[TMP99:%.*]] = select i1 [[TMP98]], i32 [[TMP96]], i32 [[TMP97]]
+// CHECK-NEXT:    store i32 [[TMP99]], i32* [[UIV]], align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP100:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP101:%.*]] = atomicrmw umax i32* [[UIX]], i32 [[TMP100]] release, align 4
+// CHECK-NEXT:    [[TMP102:%.*]] = icmp ugt i32 [[TMP101]], [[TMP100]]
+// CHECK-NEXT:    [[TMP103:%.*]] = select i1 [[TMP102]], i32 [[TMP100]], i32 [[TMP101]]
+// CHECK-NEXT:    store i32 [[TMP103]], i32* [[UIV]], align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP104:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP105:%.*]] = load i32, i32* [[UID]], align 4
+// CHECK-NEXT:    [[TMP106:%.*]] = cmpxchg i32* [[UIX]], i32 [[TMP104]], i32 [[TMP105]] release monotonic, align 4
+// CHECK-NEXT:    [[TMP107:%.*]] = extractvalue { i32, i1 } [[TMP106]], 0
+// CHECK-NEXT:    [[TMP108:%.*]] = extractvalue { i32, i1 } [[TMP106]], 1
+// CHECK-NEXT:    [[TMP109:%.*]] = select i1 [[TMP108]], i32 [[TMP104]], i32 [[TMP107]]
+// CHECK-NEXT:    store i32 [[TMP109]], i32* [[UIV]], align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP110:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP111:%.*]] = atomicrmw umin i32* [[UIX]], i32 [[TMP110]] seq_cst, align 4
+// CHECK-NEXT:    store i32 [[TMP111]], i32* [[UIV]], align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP112:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP113:%.*]] = atomicrmw umax i32* [[UIX]], i32 [[TMP112]] seq_cst, align 4
+// CHECK-NEXT:    store i32 [[TMP113]], i32* [[UIV]], align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP114:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP115:%.*]] = load i32, i32* [[UID]], align 4
+// CHECK-NEXT:    [[TMP116:%.*]] = cmpxchg i32* [[UIX]], i32 [[TMP114]], i32 [[TMP115]] seq_cst seq_cst, align 4
+// CHECK-NEXT:    [[TMP117:%.*]] = extractvalue { i32, i1 } [[TMP116]], 0
+// CHECK-NEXT:    store i32 [[TMP117]], i32* [[UIV]], align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP118:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP119:%.*]] = atomicrmw umin i32* [[UIX]], i32 [[TMP118]] seq_cst, align 4
+// CHECK-NEXT:    [[TMP120:%.*]] = icmp ult i32 [[TMP119]], [[TMP118]]
+// CHECK-NEXT:    [[TMP121:%.*]] = select i1 [[TMP120]], i32 [[TMP118]], i32 [[TMP119]]
+// CHECK-NEXT:    store i32 [[TMP121]], i32* [[UIV]], align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP122:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP123:%.*]] = atomicrmw umax i32* [[UIX]], i32 [[TMP122]] seq_cst, align 4
+// CHECK-NEXT:    [[TMP124:%.*]] = icmp ugt i32 [[TMP123]], [[TMP122]]
+// CHECK-NEXT:    [[TMP125:%.*]] = select i1 [[TMP124]], i32 [[TMP122]], i32 [[TMP123]]
+// CHECK-NEXT:    store i32 [[TMP125]], i32* [[UIV]], align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP126:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP127:%.*]] = load i32, i32* [[UID]], align 4
+// CHECK-NEXT:    [[TMP128:%.*]] = cmpxchg i32* [[UIX]], i32 [[TMP126]], i32 [[TMP127]] seq_cst seq_cst, align 4
+// CHECK-NEXT:    [[TMP129:%.*]] = extractvalue { i32, i1 } [[TMP128]], 0
+// CHECK-NEXT:    [[TMP130:%.*]] = extractvalue { i32, i1 } [[TMP128]], 1
+// CHECK-NEXT:    [[TMP131:%.*]] = select i1 [[TMP130]], i32 [[TMP126]], i32 [[TMP129]]
+// CHECK-NEXT:    store i32 [[TMP131]], i32* [[UIV]], align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP132:%.*]] = load i32, i32* [[UIV]], align 4
+// CHECK-NEXT:    ret i32 [[TMP132]]
+//
+//
+// CHECK-LABEL: define {{[^@]+}}@lxevd
+// CHECK-SAME: () #[[ATTR0]] {
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[LX:%.*]] = alloca i64, align 8
+// CHECK-NEXT:    [[LV:%.*]] = alloca i64, align 8
+// CHECK-NEXT:    [[LE:%.*]] = alloca i64, align 8
+// CHECK-NEXT:    [[LD:%.*]] = alloca i64, align 8
+// CHECK-NEXT:    [[TMP0:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP1:%.*]] = atomicrmw min i64* [[LX]], i64 [[TMP0]] monotonic, align 8
+// CHECK-NEXT:    store i64 [[TMP1]], i64* [[LV]], align 8
+// CHECK-NEXT:    [[TMP2:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP3:%.*]] = atomicrmw max i64* [[LX]], i64 [[TMP2]] monotonic, align 8
+// CHECK-NEXT:    store i64 [[TMP3]], i64* [[LV]], align 8
+// CHECK-NEXT:    [[TMP4:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP5:%.*]] = load i64, i64* [[LD]], align 8
+// CHECK-NEXT:    [[TMP6:%.*]] = cmpxchg i64* [[LX]], i64 [[TMP4]], i64 [[TMP5]] monotonic monotonic, align 8
+// CHECK-NEXT:    [[TMP7:%.*]] = extractvalue { i64, i1 } [[TMP6]], 0
+// CHECK-NEXT:    store i64 [[TMP7]], i64* [[LV]], align 8
+// CHECK-NEXT:    [[TMP8:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP9:%.*]] = atomicrmw min i64* [[LX]], i64 [[TMP8]] monotonic, align 8
+// CHECK-NEXT:    [[TMP10:%.*]] = icmp slt i64 [[TMP9]], [[TMP8]]
+// CHECK-NEXT:    [[TMP11:%.*]] = select i1 [[TMP10]], i64 [[TMP8]], i64 [[TMP9]]
+// CHECK-NEXT:    store i64 [[TMP11]], i64* [[LV]], align 8
+// CHECK-NEXT:    [[TMP12:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP13:%.*]] = atomicrmw max i64* [[LX]], i64 [[TMP12]] monotonic, align 8
+// CHECK-NEXT:    [[TMP14:%.*]] = icmp sgt i64 [[TMP13]], [[TMP12]]
+// CHECK-NEXT:    [[TMP15:%.*]] = select i1 [[TMP14]], i64 [[TMP12]], i64 [[TMP13]]
+// CHECK-NEXT:    store i64 [[TMP15]], i64* [[LV]], align 8
+// CHECK-NEXT:    [[TMP16:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP17:%.*]] = load i64, i64* [[LD]], align 8
+// CHECK-NEXT:    [[TMP18:%.*]] = cmpxchg i64* [[LX]], i64 [[TMP16]], i64 [[TMP17]] monotonic monotonic, align 8
+// CHECK-NEXT:    [[TMP19:%.*]] = extractvalue { i64, i1 } [[TMP18]], 0
+// CHECK-NEXT:    [[TMP20:%.*]] = extractvalue { i64, i1 } [[TMP18]], 1
+// CHECK-NEXT:    [[TMP21:%.*]] = select i1 [[TMP20]], i64 [[TMP16]], i64 [[TMP19]]
+// CHECK-NEXT:    store i64 [[TMP21]], i64* [[LV]], align 8
+// CHECK-NEXT:    [[TMP22:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP23:%.*]] = atomicrmw min i64* [[LX]], i64 [[TMP22]] acq_rel, align 8
+// CHECK-NEXT:    store i64 [[TMP23]], i64* [[LV]], align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP24:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP25:%.*]] = atomicrmw max i64* [[LX]], i64 [[TMP24]] acq_rel, align 8
+// CHECK-NEXT:    store i64 [[TMP25]], i64* [[LV]], align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP26:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP27:%.*]] = load i64, i64* [[LD]], align 8
+// CHECK-NEXT:    [[TMP28:%.*]] = cmpxchg i64* [[LX]], i64 [[TMP26]], i64 [[TMP27]] acq_rel acquire, align 8
+// CHECK-NEXT:    [[TMP29:%.*]] = extractvalue { i64, i1 } [[TMP28]], 0
+// CHECK-NEXT:    store i64 [[TMP29]], i64* [[LV]], align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP30:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP31:%.*]] = atomicrmw min i64* [[LX]], i64 [[TMP30]] acq_rel, align 8
+// CHECK-NEXT:    [[TMP32:%.*]] = icmp slt i64 [[TMP31]], [[TMP30]]
+// CHECK-NEXT:    [[TMP33:%.*]] = select i1 [[TMP32]], i64 [[TMP30]], i64 [[TMP31]]
+// CHECK-NEXT:    store i64 [[TMP33]], i64* [[LV]], align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP34:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP35:%.*]] = atomicrmw max i64* [[LX]], i64 [[TMP34]] acq_rel, align 8
+// CHECK-NEXT:    [[TMP36:%.*]] = icmp sgt i64 [[TMP35]], [[TMP34]]
+// CHECK-NEXT:    [[TMP37:%.*]] = select i1 [[TMP36]], i64 [[TMP34]], i64 [[TMP35]]
+// CHECK-NEXT:    store i64 [[TMP37]], i64* [[LV]], align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP38:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP39:%.*]] = load i64, i64* [[LD]], align 8
+// CHECK-NEXT:    [[TMP40:%.*]] = cmpxchg i64* [[LX]], i64 [[TMP38]], i64 [[TMP39]] acq_rel acquire, align 8
+// CHECK-NEXT:    [[TMP41:%.*]] = extractvalue { i64, i1 } [[TMP40]], 0
+// CHECK-NEXT:    [[TMP42:%.*]] = extractvalue { i64, i1 } [[TMP40]], 1
+// CHECK-NEXT:    [[TMP43:%.*]] = select i1 [[TMP42]], i64 [[TMP38]], i64 [[TMP41]]
+// CHECK-NEXT:    store i64 [[TMP43]], i64* [[LV]], align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP44:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP45:%.*]] = atomicrmw min i64* [[LX]], i64 [[TMP44]] acquire, align 8
+// CHECK-NEXT:    store i64 [[TMP45]], i64* [[LV]], align 8
+// CHECK-NEXT:    [[TMP46:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP47:%.*]] = atomicrmw max i64* [[LX]], i64 [[TMP46]] acquire, align 8
+// CHECK-NEXT:    store i64 [[TMP47]], i64* [[LV]], align 8
+// CHECK-NEXT:    [[TMP48:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP49:%.*]] = load i64, i64* [[LD]], align 8
+// CHECK-NEXT:    [[TMP50:%.*]] = cmpxchg i64* [[LX]], i64 [[TMP48]], i64 [[TMP49]] acquire acquire, align 8
+// CHECK-NEXT:    [[TMP51:%.*]] = extractvalue { i64, i1 } [[TMP50]], 0
+// CHECK-NEXT:    store i64 [[TMP51]], i64* [[LV]], align 8
+// CHECK-NEXT:    [[TMP52:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP53:%.*]] = atomicrmw min i64* [[LX]], i64 [[TMP52]] acquire, align 8
+// CHECK-NEXT:    [[TMP54:%.*]] = icmp slt i64 [[TMP53]], [[TMP52]]
+// CHECK-NEXT:    [[TMP55:%.*]] = select i1 [[TMP54]], i64 [[TMP52]], i64 [[TMP53]]
+// CHECK-NEXT:    store i64 [[TMP55]], i64* [[LV]], align 8
+// CHECK-NEXT:    [[TMP56:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP57:%.*]] = atomicrmw max i64* [[LX]], i64 [[TMP56]] acquire, align 8
+// CHECK-NEXT:    [[TMP58:%.*]] = icmp sgt i64 [[TMP57]], [[TMP56]]
+// CHECK-NEXT:    [[TMP59:%.*]] = select i1 [[TMP58]], i64 [[TMP56]], i64 [[TMP57]]
+// CHECK-NEXT:    store i64 [[TMP59]], i64* [[LV]], align 8
+// CHECK-NEXT:    [[TMP60:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP61:%.*]] = load i64, i64* [[LD]], align 8
+// CHECK-NEXT:    [[TMP62:%.*]] = cmpxchg i64* [[LX]], i64 [[TMP60]], i64 [[TMP61]] acquire acquire, align 8
+// CHECK-NEXT:    [[TMP63:%.*]] = extractvalue { i64, i1 } [[TMP62]], 0
+// CHECK-NEXT:    [[TMP64:%.*]] = extractvalue { i64, i1 } [[TMP62]], 1
+// CHECK-NEXT:    [[TMP65:%.*]] = select i1 [[TMP64]], i64 [[TMP60]], i64 [[TMP63]]
+// CHECK-NEXT:    store i64 [[TMP65]], i64* [[LV]], align 8
+// CHECK-NEXT:    [[TMP66:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP67:%.*]] = atomicrmw min i64* [[LX]], i64 [[TMP66]] monotonic, align 8
+// CHECK-NEXT:    store i64 [[TMP67]], i64* [[LV]], align 8
+// CHECK-NEXT:    [[TMP68:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP69:%.*]] = atomicrmw max i64* [[LX]], i64 [[TMP68]] monotonic, align 8
+// CHECK-NEXT:    store i64 [[TMP69]], i64* [[LV]], align 8
+// CHECK-NEXT:    [[TMP70:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP71:%.*]] = load i64, i64* [[LD]], align 8
+// CHECK-NEXT:    [[TMP72:%.*]] = cmpxchg i64* [[LX]], i64 [[TMP70]], i64 [[TMP71]] monotonic monotonic, align 8
+// CHECK-NEXT:    [[TMP73:%.*]] = extractvalue { i64, i1 } [[TMP72]], 0
+// CHECK-NEXT:    store i64 [[TMP73]], i64* [[LV]], align 8
+// CHECK-NEXT:    [[TMP74:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP75:%.*]] = atomicrmw min i64* [[LX]], i64 [[TMP74]] monotonic, align 8
+// CHECK-NEXT:    [[TMP76:%.*]] = icmp slt i64 [[TMP75]], [[TMP74]]
+// CHECK-NEXT:    [[TMP77:%.*]] = select i1 [[TMP76]], i64 [[TMP74]], i64 [[TMP75]]
+// CHECK-NEXT:    store i64 [[TMP77]], i64* [[LV]], align 8
+// CHECK-NEXT:    [[TMP78:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP79:%.*]] = atomicrmw max i64* [[LX]], i64 [[TMP78]] monotonic, align 8
+// CHECK-NEXT:    [[TMP80:%.*]] = icmp sgt i64 [[TMP79]], [[TMP78]]
+// CHECK-NEXT:    [[TMP81:%.*]] = select i1 [[TMP80]], i64 [[TMP78]], i64 [[TMP79]]
+// CHECK-NEXT:    store i64 [[TMP81]], i64* [[LV]], align 8
+// CHECK-NEXT:    [[TMP82:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP83:%.*]] = load i64, i64* [[LD]], align 8
+// CHECK-NEXT:    [[TMP84:%.*]] = cmpxchg i64* [[LX]], i64 [[TMP82]], i64 [[TMP83]] monotonic monotonic, align 8
+// CHECK-NEXT:    [[TMP85:%.*]] = extractvalue { i64, i1 } [[TMP84]], 0
+// CHECK-NEXT:    [[TMP86:%.*]] = extractvalue { i64, i1 } [[TMP84]], 1
+// CHECK-NEXT:    [[TMP87:%.*]] = select i1 [[TMP86]], i64 [[TMP82]], i64 [[TMP85]]
+// CHECK-NEXT:    store i64 [[TMP87]], i64* [[LV]], align 8
+// CHECK-NEXT:    [[TMP88:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP89:%.*]] = atomicrmw min i64* [[LX]], i64 [[TMP88]] release, align 8
+// CHECK-NEXT:    store i64 [[TMP89]], i64* [[LV]], align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP90:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP91:%.*]] = atomicrmw max i64* [[LX]], i64 [[TMP90]] release, align 8
+// CHECK-NEXT:    store i64 [[TMP91]], i64* [[LV]], align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP92:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP93:%.*]] = load i64, i64* [[LD]], align 8
+// CHECK-NEXT:    [[TMP94:%.*]] = cmpxchg i64* [[LX]], i64 [[TMP92]], i64 [[TMP93]] release monotonic, align 8
+// CHECK-NEXT:    [[TMP95:%.*]] = extractvalue { i64, i1 } [[TMP94]], 0
+// CHECK-NEXT:    store i64 [[TMP95]], i64* [[LV]], align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP96:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP97:%.*]] = atomicrmw min i64* [[LX]], i64 [[TMP96]] release, align 8
+// CHECK-NEXT:    [[TMP98:%.*]] = icmp slt i64 [[TMP97]], [[TMP96]]
+// CHECK-NEXT:    [[TMP99:%.*]] = select i1 [[TMP98]], i64 [[TMP96]], i64 [[TMP97]]
+// CHECK-NEXT:    store i64 [[TMP99]], i64* [[LV]], align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP100:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP101:%.*]] = atomicrmw max i64* [[LX]], i64 [[TMP100]] release, align 8
+// CHECK-NEXT:    [[TMP102:%.*]] = icmp sgt i64 [[TMP101]], [[TMP100]]
+// CHECK-NEXT:    [[TMP103:%.*]] = select i1 [[TMP102]], i64 [[TMP100]], i64 [[TMP101]]
+// CHECK-NEXT:    store i64 [[TMP103]], i64* [[LV]], align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP104:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP105:%.*]] = load i64, i64* [[LD]], align 8
+// CHECK-NEXT:    [[TMP106:%.*]] = cmpxchg i64* [[LX]], i64 [[TMP104]], i64 [[TMP105]] release monotonic, align 8
+// CHECK-NEXT:    [[TMP107:%.*]] = extractvalue { i64, i1 } [[TMP106]], 0
+// CHECK-NEXT:    [[TMP108:%.*]] = extractvalue { i64, i1 } [[TMP106]], 1
+// CHECK-NEXT:    [[TMP109:%.*]] = select i1 [[TMP108]], i64 [[TMP104]], i64 [[TMP107]]
+// CHECK-NEXT:    store i64 [[TMP109]], i64* [[LV]], align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP110:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP111:%.*]] = atomicrmw min i64* [[LX]], i64 [[TMP110]] seq_cst, align 8
+// CHECK-NEXT:    store i64 [[TMP111]], i64* [[LV]], align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP112:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP113:%.*]] = atomicrmw max i64* [[LX]], i64 [[TMP112]] seq_cst, align 8
+// CHECK-NEXT:    store i64 [[TMP113]], i64* [[LV]], align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP114:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP115:%.*]] = load i64, i64* [[LD]], align 8
+// CHECK-NEXT:    [[TMP116:%.*]] = cmpxchg i64* [[LX]], i64 [[TMP114]], i64 [[TMP115]] seq_cst seq_cst, align 8
+// CHECK-NEXT:    [[TMP117:%.*]] = extractvalue { i64, i1 } [[TMP116]], 0
+// CHECK-NEXT:    store i64 [[TMP117]], i64* [[LV]], align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP118:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP119:%.*]] = atomicrmw min i64* [[LX]], i64 [[TMP118]] seq_cst, align 8
+// CHECK-NEXT:    [[TMP120:%.*]] = icmp slt i64 [[TMP119]], [[TMP118]]
+// CHECK-NEXT:    [[TMP121:%.*]] = select i1 [[TMP120]], i64 [[TMP118]], i64 [[TMP119]]
+// CHECK-NEXT:    store i64 [[TMP121]], i64* [[LV]], align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP122:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP123:%.*]] = atomicrmw max i64* [[LX]], i64 [[TMP122]] seq_cst, align 8
+// CHECK-NEXT:    [[TMP124:%.*]] = icmp sgt i64 [[TMP123]], [[TMP122]]
+// CHECK-NEXT:    [[TMP125:%.*]] = select i1 [[TMP124]], i64 [[TMP122]], i64 [[TMP123]]
+// CHECK-NEXT:    store i64 [[TMP125]], i64* [[LV]], align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP126:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP127:%.*]] = load i64, i64* [[LD]], align 8
+// CHECK-NEXT:    [[TMP128:%.*]] = cmpxchg i64* [[LX]], i64 [[TMP126]], i64 [[TMP127]] seq_cst seq_cst, align 8
+// CHECK-NEXT:    [[TMP129:%.*]] = extractvalue { i64, i1 } [[TMP128]], 0
+// CHECK-NEXT:    [[TMP130:%.*]] = extractvalue { i64, i1 } [[TMP128]], 1
+// CHECK-NEXT:    [[TMP131:%.*]] = select i1 [[TMP130]], i64 [[TMP126]], i64 [[TMP129]]
+// CHECK-NEXT:    store i64 [[TMP131]], i64* [[LV]], align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP132:%.*]] = load i64, i64* [[LV]], align 8
+// CHECK-NEXT:    ret i64 [[TMP132]]
+//
+//
+// CHECK-LABEL: define {{[^@]+}}@ulxevd
+// CHECK-SAME: () #[[ATTR0]] {
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[ULX:%.*]] = alloca i64, align 8
+// CHECK-NEXT:    [[ULV:%.*]] = alloca i64, align 8
+// CHECK-NEXT:    [[ULE:%.*]] = alloca i64, align 8
+// CHECK-NEXT:    [[ULD:%.*]] = alloca i64, align 8
+// CHECK-NEXT:    [[TMP0:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP1:%.*]] = atomicrmw umin i64* [[ULX]], i64 [[TMP0]] monotonic, align 8
+// CHECK-NEXT:    store i64 [[TMP1]], i64* [[ULV]], align 8
+// CHECK-NEXT:    [[TMP2:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP3:%.*]] = atomicrmw umax i64* [[ULX]], i64 [[TMP2]] monotonic, align 8
+// CHECK-NEXT:    store i64 [[TMP3]], i64* [[ULV]], align 8
+// CHECK-NEXT:    [[TMP4:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP5:%.*]] = load i64, i64* [[ULD]], align 8
+// CHECK-NEXT:    [[TMP6:%.*]] = cmpxchg i64* [[ULX]], i64 [[TMP4]], i64 [[TMP5]] monotonic monotonic, align 8
+// CHECK-NEXT:    [[TMP7:%.*]] = extractvalue { i64, i1 } [[TMP6]], 0
+// CHECK-NEXT:    store i64 [[TMP7]], i64* [[ULV]], align 8
+// CHECK-NEXT:    [[TMP8:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP9:%.*]] = atomicrmw umin i64* [[ULX]], i64 [[TMP8]] monotonic, align 8
+// CHECK-NEXT:    [[TMP10:%.*]] = icmp ult i64 [[TMP9]], [[TMP8]]
+// CHECK-NEXT:    [[TMP11:%.*]] = select i1 [[TMP10]], i64 [[TMP8]], i64 [[TMP9]]
+// CHECK-NEXT:    store i64 [[TMP11]], i64* [[ULV]], align 8
+// CHECK-NEXT:    [[TMP12:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP13:%.*]] = atomicrmw umax i64* [[ULX]], i64 [[TMP12]] monotonic, align 8
+// CHECK-NEXT:    [[TMP14:%.*]] = icmp ugt i64 [[TMP13]], [[TMP12]]
+// CHECK-NEXT:    [[TMP15:%.*]] = select i1 [[TMP14]], i64 [[TMP12]], i64 [[TMP13]]
+// CHECK-NEXT:    store i64 [[TMP15]], i64* [[ULV]], align 8
+// CHECK-NEXT:    [[TMP16:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP17:%.*]] = load i64, i64* [[ULD]], align 8
+// CHECK-NEXT:    [[TMP18:%.*]] = cmpxchg i64* [[ULX]], i64 [[TMP16]], i64 [[TMP17]] monotonic monotonic, align 8
+// CHECK-NEXT:    [[TMP19:%.*]] = extractvalue { i64, i1 } [[TMP18]], 0
+// CHECK-NEXT:    [[TMP20:%.*]] = extractvalue { i64, i1 } [[TMP18]], 1
+// CHECK-NEXT:    [[TMP21:%.*]] = select i1 [[TMP20]], i64 [[TMP16]], i64 [[TMP19]]
+// CHECK-NEXT:    store i64 [[TMP21]], i64* [[ULV]], align 8
+// CHECK-NEXT:    [[TMP22:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP23:%.*]] = atomicrmw umin i64* [[ULX]], i64 [[TMP22]] acq_rel, align 8
+// CHECK-NEXT:    store i64 [[TMP23]], i64* [[ULV]], align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP24:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP25:%.*]] = atomicrmw umax i64* [[ULX]], i64 [[TMP24]] acq_rel, align 8
+// CHECK-NEXT:    store i64 [[TMP25]], i64* [[ULV]], align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP26:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP27:%.*]] = load i64, i64* [[ULD]], align 8
+// CHECK-NEXT:    [[TMP28:%.*]] = cmpxchg i64* [[ULX]], i64 [[TMP26]], i64 [[TMP27]] acq_rel acquire, align 8
+// CHECK-NEXT:    [[TMP29:%.*]] = extractvalue { i64, i1 } [[TMP28]], 0
+// CHECK-NEXT:    store i64 [[TMP29]], i64* [[ULV]], align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP30:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP31:%.*]] = atomicrmw umin i64* [[ULX]], i64 [[TMP30]] acq_rel, align 8
+// CHECK-NEXT:    [[TMP32:%.*]] = icmp ult i64 [[TMP31]], [[TMP30]]
+// CHECK-NEXT:    [[TMP33:%.*]] = select i1 [[TMP32]], i64 [[TMP30]], i64 [[TMP31]]
+// CHECK-NEXT:    store i64 [[TMP33]], i64* [[ULV]], align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP34:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP35:%.*]] = atomicrmw umax i64* [[ULX]], i64 [[TMP34]] acq_rel, align 8
+// CHECK-NEXT:    [[TMP36:%.*]] = icmp ugt i64 [[TMP35]], [[TMP34]]
+// CHECK-NEXT:    [[TMP37:%.*]] = select i1 [[TMP36]], i64 [[TMP34]], i64 [[TMP35]]
+// CHECK-NEXT:    store i64 [[TMP37]], i64* [[ULV]], align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP38:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP39:%.*]] = load i64, i64* [[ULD]], align 8
+// CHECK-NEXT:    [[TMP40:%.*]] = cmpxchg i64* [[ULX]], i64 [[TMP38]], i64 [[TMP39]] acq_rel acquire, align 8
+// CHECK-NEXT:    [[TMP41:%.*]] = extractvalue { i64, i1 } [[TMP40]], 0
+// CHECK-NEXT:    [[TMP42:%.*]] = extractvalue { i64, i1 } [[TMP40]], 1
+// CHECK-NEXT:    [[TMP43:%.*]] = select i1 [[TMP42]], i64 [[TMP38]], i64 [[TMP41]]
+// CHECK-NEXT:    store i64 [[TMP43]], i64* [[ULV]], align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP44:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP45:%.*]] = atomicrmw umin i64* [[ULX]], i64 [[TMP44]] acquire, align 8
+// CHECK-NEXT:    store i64 [[TMP45]], i64* [[ULV]], align 8
+// CHECK-NEXT:    [[TMP46:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP47:%.*]] = atomicrmw umax i64* [[ULX]], i64 [[TMP46]] acquire, align 8
+// CHECK-NEXT:    store i64 [[TMP47]], i64* [[ULV]], align 8
+// CHECK-NEXT:    [[TMP48:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP49:%.*]] = load i64, i64* [[ULD]], align 8
+// CHECK-NEXT:    [[TMP50:%.*]] = cmpxchg i64* [[ULX]], i64 [[TMP48]], i64 [[TMP49]] acquire acquire, align 8
+// CHECK-NEXT:    [[TMP51:%.*]] = extractvalue { i64, i1 } [[TMP50]], 0
+// CHECK-NEXT:    store i64 [[TMP51]], i64* [[ULV]], align 8
+// CHECK-NEXT:    [[TMP52:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP53:%.*]] = atomicrmw umin i64* [[ULX]], i64 [[TMP52]] acquire, align 8
+// CHECK-NEXT:    [[TMP54:%.*]] = icmp ult i64 [[TMP53]], [[TMP52]]
+// CHECK-NEXT:    [[TMP55:%.*]] = select i1 [[TMP54]], i64 [[TMP52]], i64 [[TMP53]]
+// CHECK-NEXT:    store i64 [[TMP55]], i64* [[ULV]], align 8
+// CHECK-NEXT:    [[TMP56:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP57:%.*]] = atomicrmw umax i64* [[ULX]], i64 [[TMP56]] acquire, align 8
+// CHECK-NEXT:    [[TMP58:%.*]] = icmp ugt i64 [[TMP57]], [[TMP56]]
+// CHECK-NEXT:    [[TMP59:%.*]] = select i1 [[TMP58]], i64 [[TMP56]], i64 [[TMP57]]
+// CHECK-NEXT:    store i64 [[TMP59]], i64* [[ULV]], align 8
+// CHECK-NEXT:    [[TMP60:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP61:%.*]] = load i64, i64* [[ULD]], align 8
+// CHECK-NEXT:    [[TMP62:%.*]] = cmpxchg i64* [[ULX]], i64 [[TMP60]], i64 [[TMP61]] acquire acquire, align 8
+// CHECK-NEXT:    [[TMP63:%.*]] = extractvalue { i64, i1 } [[TMP62]], 0
+// CHECK-NEXT:    [[TMP64:%.*]] = extractvalue { i64, i1 } [[TMP62]], 1
+// CHECK-NEXT:    [[TMP65:%.*]] = select i1 [[TMP64]], i64 [[TMP60]], i64 [[TMP63]]
+// CHECK-NEXT:    store i64 [[TMP65]], i64* [[ULV]], align 8
+// CHECK-NEXT:    [[TMP66:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP67:%.*]] = atomicrmw umin i64* [[ULX]], i64 [[TMP66]] monotonic, align 8
+// CHECK-NEXT:    store i64 [[TMP67]], i64* [[ULV]], align 8
+// CHECK-NEXT:    [[TMP68:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP69:%.*]] = atomicrmw umax i64* [[ULX]], i64 [[TMP68]] monotonic, align 8
+// CHECK-NEXT:    store i64 [[TMP69]], i64* [[ULV]], align 8
+// CHECK-NEXT:    [[TMP70:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP71:%.*]] = load i64, i64* [[ULD]], align 8
+// CHECK-NEXT:    [[TMP72:%.*]] = cmpxchg i64* [[ULX]], i64 [[TMP70]], i64 [[TMP71]] monotonic monotonic, align 8
+// CHECK-NEXT:    [[TMP73:%.*]] = extractvalue { i64, i1 } [[TMP72]], 0
+// CHECK-NEXT:    store i64 [[TMP73]], i64* [[ULV]], align 8
+// CHECK-NEXT:    [[TMP74:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP75:%.*]] = atomicrmw umin i64* [[ULX]], i64 [[TMP74]] monotonic, align 8
+// CHECK-NEXT:    [[TMP76:%.*]] = icmp ult i64 [[TMP75]], [[TMP74]]
+// CHECK-NEXT:    [[TMP77:%.*]] = select i1 [[TMP76]], i64 [[TMP74]], i64 [[TMP75]]
+// CHECK-NEXT:    store i64 [[TMP77]], i64* [[ULV]], align 8
+// CHECK-NEXT:    [[TMP78:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP79:%.*]] = atomicrmw umax i64* [[ULX]], i64 [[TMP78]] monotonic, align 8
+// CHECK-NEXT:    [[TMP80:%.*]] = icmp ugt i64 [[TMP79]], [[TMP78]]
+// CHECK-NEXT:    [[TMP81:%.*]] = select i1 [[TMP80]], i64 [[TMP78]], i64 [[TMP79]]
+// CHECK-NEXT:    store i64 [[TMP81]], i64* [[ULV]], align 8
+// CHECK-NEXT:    [[TMP82:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP83:%.*]] = load i64, i64* [[ULD]], align 8
+// CHECK-NEXT:    [[TMP84:%.*]] = cmpxchg i64* [[ULX]], i64 [[TMP82]], i64 [[TMP83]] monotonic monotonic, align 8
+// CHECK-NEXT:    [[TMP85:%.*]] = extractvalue { i64, i1 } [[TMP84]], 0
+// CHECK-NEXT:    [[TMP86:%.*]] = extractvalue { i64, i1 } [[TMP84]], 1
+// CHECK-NEXT:    [[TMP87:%.*]] = select i1 [[TMP86]], i64 [[TMP82]], i64 [[TMP85]]
+// CHECK-NEXT:    store i64 [[TMP87]], i64* [[ULV]], align 8
+// CHECK-NEXT:    [[TMP88:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP89:%.*]] = atomicrmw umin i64* [[ULX]], i64 [[TMP88]] release, align 8
+// CHECK-NEXT:    store i64 [[TMP89]], i64* [[ULV]], align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP90:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP91:%.*]] = atomicrmw umax i64* [[ULX]], i64 [[TMP90]] release, align 8
+// CHECK-NEXT:    store i64 [[TMP91]], i64* [[ULV]], align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP92:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP93:%.*]] = load i64, i64* [[ULD]], align 8
+// CHECK-NEXT:    [[TMP94:%.*]] = cmpxchg i64* [[ULX]], i64 [[TMP92]], i64 [[TMP93]] release monotonic, align 8
+// CHECK-NEXT:    [[TMP95:%.*]] = extractvalue { i64, i1 } [[TMP94]], 0
+// CHECK-NEXT:    store i64 [[TMP95]], i64* [[ULV]], align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP96:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP97:%.*]] = atomicrmw umin i64* [[ULX]], i64 [[TMP96]] release, align 8
+// CHECK-NEXT:    [[TMP98:%.*]] = icmp ult i64 [[TMP97]], [[TMP96]]
+// CHECK-NEXT:    [[TMP99:%.*]] = select i1 [[TMP98]], i64 [[TMP96]], i64 [[TMP97]]
+// CHECK-NEXT:    store i64 [[TMP99]], i64* [[ULV]], align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP100:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP101:%.*]] = atomicrmw umax i64* [[ULX]], i64 [[TMP100]] release, align 8
+// CHECK-NEXT:    [[TMP102:%.*]] = icmp ugt i64 [[TMP101]], [[TMP100]]
+// CHECK-NEXT:    [[TMP103:%.*]] = select i1 [[TMP102]], i64 [[TMP100]], i64 [[TMP101]]
+// CHECK-NEXT:    store i64 [[TMP103]], i64* [[ULV]], align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP104:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP105:%.*]] = load i64, i64* [[ULD]], align 8
+// CHECK-NEXT:    [[TMP106:%.*]] = cmpxchg i64* [[ULX]], i64 [[TMP104]], i64 [[TMP105]] release monotonic, align 8
+// CHECK-NEXT:    [[TMP107:%.*]] = extractvalue { i64, i1 } [[TMP106]], 0
+// CHECK-NEXT:    [[TMP108:%.*]] = extractvalue { i64, i1 } [[TMP106]], 1
+// CHECK-NEXT:    [[TMP109:%.*]] = select i1 [[TMP108]], i64 [[TMP104]], i64 [[TMP107]]
+// CHECK-NEXT:    store i64 [[TMP109]], i64* [[ULV]], align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP110:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP111:%.*]] = atomicrmw umin i64* [[ULX]], i64 [[TMP110]] seq_cst, align 8
+// CHECK-NEXT:    store i64 [[TMP111]], i64* [[ULV]], align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP112:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP113:%.*]] = atomicrmw umax i64* [[ULX]], i64 [[TMP112]] seq_cst, align 8
+// CHECK-NEXT:    store i64 [[TMP113]], i64* [[ULV]], align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP114:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP115:%.*]] = load i64, i64* [[ULD]], align 8
+// CHECK-NEXT:    [[TMP116:%.*]] = cmpxchg i64* [[ULX]], i64 [[TMP114]], i64 [[TMP115]] seq_cst seq_cst, align 8
+// CHECK-NEXT:    [[TMP117:%.*]] = extractvalue { i64, i1 } [[TMP116]], 0
+// CHECK-NEXT:    store i64 [[TMP117]], i64* [[ULV]], align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP118:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP119:%.*]] = atomicrmw umin i64* [[ULX]], i64 [[TMP118]] seq_cst, align 8
+// CHECK-NEXT:    [[TMP120:%.*]] = icmp ult i64 [[TMP119]], [[TMP118]]
+// CHECK-NEXT:    [[TMP121:%.*]] = select i1 [[TMP120]], i64 [[TMP118]], i64 [[TMP119]]
+// CHECK-NEXT:    store i64 [[TMP121]], i64* [[ULV]], align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP122:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP123:%.*]] = atomicrmw umax i64* [[ULX]], i64 [[TMP122]] seq_cst, align 8
+// CHECK-NEXT:    [[TMP124:%.*]] = icmp ugt i64 [[TMP123]], [[TMP122]]
+// CHECK-NEXT:    [[TMP125:%.*]] = select i1 [[TMP124]], i64 [[TMP122]], i64 [[TMP123]]
+// CHECK-NEXT:    store i64 [[TMP125]], i64* [[ULV]], align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP126:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP127:%.*]] = load i64, i64* [[ULD]], align 8
+// CHECK-NEXT:    [[TMP128:%.*]] = cmpxchg i64* [[ULX]], i64 [[TMP126]], i64 [[TMP127]] seq_cst seq_cst, align 8
+// CHECK-NEXT:    [[TMP129:%.*]] = extractvalue { i64, i1 } [[TMP128]], 0
+// CHECK-NEXT:    [[TMP130:%.*]] = extractvalue { i64, i1 } [[TMP128]], 1
+// CHECK-NEXT:    [[TMP131:%.*]] = select i1 [[TMP130]], i64 [[TMP126]], i64 [[TMP129]]
+// CHECK-NEXT:    store i64 [[TMP131]], i64* [[ULV]], align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP132:%.*]] = load i64, i64* [[ULV]], align 8
+// CHECK-NEXT:    ret i64 [[TMP132]]
+//
+//
+// CHECK-LABEL: define {{[^@]+}}@llxevd
+// CHECK-SAME: () #[[ATTR0]] {
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[LLX:%.*]] = alloca i64, align 8
+// CHECK-NEXT:    [[LLV:%.*]] = alloca i64, align 8
+// CHECK-NEXT:    [[LLE:%.*]] = alloca i64, align 8
+// CHECK-NEXT:    [[LLD:%.*]] = alloca i64, align 8
+// CHECK-NEXT:    [[TMP0:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP1:%.*]] = atomicrmw min i64* [[LLX]], i64 [[TMP0]] monotonic, align 8
+// CHECK-NEXT:    store i64 [[TMP1]], i64* [[LLV]], align 8
+// CHECK-NEXT:    [[TMP2:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP3:%.*]] = atomicrmw max i64* [[LLX]], i64 [[TMP2]] monotonic, align 8
+// CHECK-NEXT:    store i64 [[TMP3]], i64* [[LLV]], align 8
+// CHECK-NEXT:    [[TMP4:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP5:%.*]] = load i64, i64* [[LLD]], align 8
+// CHECK-NEXT:    [[TMP6:%.*]] = cmpxchg i64* [[LLX]], i64 [[TMP4]], i64 [[TMP5]] monotonic monotonic, align 8
+// CHECK-NEXT:    [[TMP7:%.*]] = extractvalue { i64, i1 } [[TMP6]], 0
+// CHECK-NEXT:    store i64 [[TMP7]], i64* [[LLV]], align 8
+// CHECK-NEXT:    [[TMP8:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP9:%.*]] = atomicrmw min i64* [[LLX]], i64 [[TMP8]] monotonic, align 8
+// CHECK-NEXT:    [[TMP10:%.*]] = icmp slt i64 [[TMP9]], [[TMP8]]
+// CHECK-NEXT:    [[TMP11:%.*]] = select i1 [[TMP10]], i64 [[TMP8]], i64 [[TMP9]]
+// CHECK-NEXT:    store i64 [[TMP11]], i64* [[LLV]], align 8
+// CHECK-NEXT:    [[TMP12:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP13:%.*]] = atomicrmw max i64* [[LLX]], i64 [[TMP12]] monotonic, align 8
+// CHECK-NEXT:    [[TMP14:%.*]] = icmp sgt i64 [[TMP13]], [[TMP12]]
+// CHECK-NEXT:    [[TMP15:%.*]] = select i1 [[TMP14]], i64 [[TMP12]], i64 [[TMP13]]
+// CHECK-NEXT:    store i64 [[TMP15]], i64* [[LLV]], align 8
+// CHECK-NEXT:    [[TMP16:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP17:%.*]] = load i64, i64* [[LLD]], align 8
+// CHECK-NEXT:    [[TMP18:%.*]] = cmpxchg i64* [[LLX]], i64 [[TMP16]], i64 [[TMP17]] monotonic monotonic, align 8
+// CHECK-NEXT:    [[TMP19:%.*]] = extractvalue { i64, i1 } [[TMP18]], 0
+// CHECK-NEXT:    [[TMP20:%.*]] = extractvalue { i64, i1 } [[TMP18]], 1
+// CHECK-NEXT:    [[TMP21:%.*]] = select i1 [[TMP20]], i64 [[TMP16]], i64 [[TMP19]]
+// CHECK-NEXT:    store i64 [[TMP21]], i64* [[LLV]], align 8
+// CHECK-NEXT:    [[TMP22:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP23:%.*]] = atomicrmw min i64* [[LLX]], i64 [[TMP22]] acq_rel, align 8
+// CHECK-NEXT:    store i64 [[TMP23]], i64* [[LLV]], align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP24:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP25:%.*]] = atomicrmw max i64* [[LLX]], i64 [[TMP24]] acq_rel, align 8
+// CHECK-NEXT:    store i64 [[TMP25]], i64* [[LLV]], align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP26:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP27:%.*]] = load i64, i64* [[LLD]], align 8
+// CHECK-NEXT:    [[TMP28:%.*]] = cmpxchg i64* [[LLX]], i64 [[TMP26]], i64 [[TMP27]] acq_rel acquire, align 8
+// CHECK-NEXT:    [[TMP29:%.*]] = extractvalue { i64, i1 } [[TMP28]], 0
+// CHECK-NEXT:    store i64 [[TMP29]], i64* [[LLV]], align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP30:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP31:%.*]] = atomicrmw min i64* [[LLX]], i64 [[TMP30]] acq_rel, align 8
+// CHECK-NEXT:    [[TMP32:%.*]] = icmp slt i64 [[TMP31]], [[TMP30]]
+// CHECK-NEXT:    [[TMP33:%.*]] = select i1 [[TMP32]], i64 [[TMP30]], i64 [[TMP31]]
+// CHECK-NEXT:    store i64 [[TMP33]], i64* [[LLV]], align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP34:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP35:%.*]] = atomicrmw max i64* [[LLX]], i64 [[TMP34]] acq_rel, align 8
+// CHECK-NEXT:    [[TMP36:%.*]] = icmp sgt i64 [[TMP35]], [[TMP34]]
+// CHECK-NEXT:    [[TMP37:%.*]] = select i1 [[TMP36]], i64 [[TMP34]], i64 [[TMP35]]
+// CHECK-NEXT:    store i64 [[TMP37]], i64* [[LLV]], align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP38:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP39:%.*]] = load i64, i64* [[LLD]], align 8
+// CHECK-NEXT:    [[TMP40:%.*]] = cmpxchg i64* [[LLX]], i64 [[TMP38]], i64 [[TMP39]] acq_rel acquire, align 8
+// CHECK-NEXT:    [[TMP41:%.*]] = extractvalue { i64, i1 } [[TMP40]], 0
+// CHECK-NEXT:    [[TMP42:%.*]] = extractvalue { i64, i1 } [[TMP40]], 1
+// CHECK-NEXT:    [[TMP43:%.*]] = select i1 [[TMP42]], i64 [[TMP38]], i64 [[TMP41]]
+// CHECK-NEXT:    store i64 [[TMP43]], i64* [[LLV]], align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP44:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP45:%.*]] = atomicrmw min i64* [[LLX]], i64 [[TMP44]] acquire, align 8
+// CHECK-NEXT:    store i64 [[TMP45]], i64* [[LLV]], align 8
+// CHECK-NEXT:    [[TMP46:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP47:%.*]] = atomicrmw max i64* [[LLX]], i64 [[TMP46]] acquire, align 8
+// CHECK-NEXT:    store i64 [[TMP47]], i64* [[LLV]], align 8
+// CHECK-NEXT:    [[TMP48:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP49:%.*]] = load i64, i64* [[LLD]], align 8
+// CHECK-NEXT:    [[TMP50:%.*]] = cmpxchg i64* [[LLX]], i64 [[TMP48]], i64 [[TMP49]] acquire acquire, align 8
+// CHECK-NEXT:    [[TMP51:%.*]] = extractvalue { i64, i1 } [[TMP50]], 0
+// CHECK-NEXT:    store i64 [[TMP51]], i64* [[LLV]], align 8
+// CHECK-NEXT:    [[TMP52:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP53:%.*]] = atomicrmw min i64* [[LLX]], i64 [[TMP52]] acquire, align 8
+// CHECK-NEXT:    [[TMP54:%.*]] = icmp slt i64 [[TMP53]], [[TMP52]]
+// CHECK-NEXT:    [[TMP55:%.*]] = select i1 [[TMP54]], i64 [[TMP52]], i64 [[TMP53]]
+// CHECK-NEXT:    store i64 [[TMP55]], i64* [[LLV]], align 8
+// CHECK-NEXT:    [[TMP56:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP57:%.*]] = atomicrmw max i64* [[LLX]], i64 [[TMP56]] acquire, align 8
+// CHECK-NEXT:    [[TMP58:%.*]] = icmp sgt i64 [[TMP57]], [[TMP56]]
+// CHECK-NEXT:    [[TMP59:%.*]] = select i1 [[TMP58]], i64 [[TMP56]], i64 [[TMP57]]
+// CHECK-NEXT:    store i64 [[TMP59]], i64* [[LLV]], align 8
+// CHECK-NEXT:    [[TMP60:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP61:%.*]] = load i64, i64* [[LLD]], align 8
+// CHECK-NEXT:    [[TMP62:%.*]] = cmpxchg i64* [[LLX]], i64 [[TMP60]], i64 [[TMP61]] acquire acquire, align 8
+// CHECK-NEXT:    [[TMP63:%.*]] = extractvalue { i64, i1 } [[TMP62]], 0
+// CHECK-NEXT:    [[TMP64:%.*]] = extractvalue { i64, i1 } [[TMP62]], 1
+// CHECK-NEXT:    [[TMP65:%.*]] = select i1 [[TMP64]], i64 [[TMP60]], i64 [[TMP63]]
+// CHECK-NEXT:    store i64 [[TMP65]], i64* [[LLV]], align 8
+// CHECK-NEXT:    [[TMP66:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP67:%.*]] = atomicrmw min i64* [[LLX]], i64 [[TMP66]] monotonic, align 8
+// CHECK-NEXT:    store i64 [[TMP67]], i64* [[LLV]], align 8
+// CHECK-NEXT:    [[TMP68:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP69:%.*]] = atomicrmw max i64* [[LLX]], i64 [[TMP68]] monotonic, align 8
+// CHECK-NEXT:    store i64 [[TMP69]], i64* [[LLV]], align 8
+// CHECK-NEXT:    [[TMP70:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP71:%.*]] = load i64, i64* [[LLD]], align 8
+// CHECK-NEXT:    [[TMP72:%.*]] = cmpxchg i64* [[LLX]], i64 [[TMP70]], i64 [[TMP71]] monotonic monotonic, align 8
+// CHECK-NEXT:    [[TMP73:%.*]] = extractvalue { i64, i1 } [[TMP72]], 0
+// CHECK-NEXT:    store i64 [[TMP73]], i64* [[LLV]], align 8
+// CHECK-NEXT:    [[TMP74:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP75:%.*]] = atomicrmw min i64* [[LLX]], i64 [[TMP74]] monotonic, align 8
+// CHECK-NEXT:    [[TMP76:%.*]] = icmp slt i64 [[TMP75]], [[TMP74]]
+// CHECK-NEXT:    [[TMP77:%.*]] = select i1 [[TMP76]], i64 [[TMP74]], i64 [[TMP75]]
+// CHECK-NEXT:    store i64 [[TMP77]], i64* [[LLV]], align 8
+// CHECK-NEXT:    [[TMP78:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP79:%.*]] = atomicrmw max i64* [[LLX]], i64 [[TMP78]] monotonic, align 8
+// CHECK-NEXT:    [[TMP80:%.*]] = icmp sgt i64 [[TMP79]], [[TMP78]]
+// CHECK-NEXT:    [[TMP81:%.*]] = select i1 [[TMP80]], i64 [[TMP78]], i64 [[TMP79]]
+// CHECK-NEXT:    store i64 [[TMP81]], i64* [[LLV]], align 8
+// CHECK-NEXT:    [[TMP82:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP83:%.*]] = load i64, i64* [[LLD]], align 8
+// CHECK-NEXT:    [[TMP84:%.*]] = cmpxchg i64* [[LLX]], i64 [[TMP82]], i64 [[TMP83]] monotonic monotonic, align 8
+// CHECK-NEXT:    [[TMP85:%.*]] = extractvalue { i64, i1 } [[TMP84]], 0
+// CHECK-NEXT:    [[TMP86:%.*]] = extractvalue { i64, i1 } [[TMP84]], 1
+// CHECK-NEXT:    [[TMP87:%.*]] = select i1 [[TMP86]], i64 [[TMP82]], i64 [[TMP85]]
+// CHECK-NEXT:    store i64 [[TMP87]], i64* [[LLV]], align 8
+// CHECK-NEXT:    [[TMP88:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP89:%.*]] = atomicrmw min i64* [[LLX]], i64 [[TMP88]] release, align 8
+// CHECK-NEXT:    store i64 [[TMP89]], i64* [[LLV]], align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP90:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP91:%.*]] = atomicrmw max i64* [[LLX]], i64 [[TMP90]] release, align 8
+// CHECK-NEXT:    store i64 [[TMP91]], i64* [[LLV]], align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP92:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP93:%.*]] = load i64, i64* [[LLD]], align 8
+// CHECK-NEXT:    [[TMP94:%.*]] = cmpxchg i64* [[LLX]], i64 [[TMP92]], i64 [[TMP93]] release monotonic, align 8
+// CHECK-NEXT:    [[TMP95:%.*]] = extractvalue { i64, i1 } [[TMP94]], 0
+// CHECK-NEXT:    store i64 [[TMP95]], i64* [[LLV]], align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP96:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP97:%.*]] = atomicrmw min i64* [[LLX]], i64 [[TMP96]] release, align 8
+// CHECK-NEXT:    [[TMP98:%.*]] = icmp slt i64 [[TMP97]], [[TMP96]]
+// CHECK-NEXT:    [[TMP99:%.*]] = select i1 [[TMP98]], i64 [[TMP96]], i64 [[TMP97]]
+// CHECK-NEXT:    store i64 [[TMP99]], i64* [[LLV]], align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP100:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP101:%.*]] = atomicrmw max i64* [[LLX]], i64 [[TMP100]] release, align 8
+// CHECK-NEXT:    [[TMP102:%.*]] = icmp sgt i64 [[TMP101]], [[TMP100]]
+// CHECK-NEXT:    [[TMP103:%.*]] = select i1 [[TMP102]], i64 [[TMP100]], i64 [[TMP101]]
+// CHECK-NEXT:    store i64 [[TMP103]], i64* [[LLV]], align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP104:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP105:%.*]] = load i64, i64* [[LLD]], align 8
+// CHECK-NEXT:    [[TMP106:%.*]] = cmpxchg i64* [[LLX]], i64 [[TMP104]], i64 [[TMP105]] release monotonic, align 8
+// CHECK-NEXT:    [[TMP107:%.*]] = extractvalue { i64, i1 } [[TMP106]], 0
+// CHECK-NEXT:    [[TMP108:%.*]] = extractvalue { i64, i1 } [[TMP106]], 1
+// CHECK-NEXT:    [[TMP109:%.*]] = select i1 [[TMP108]], i64 [[TMP104]], i64 [[TMP107]]
+// CHECK-NEXT:    store i64 [[TMP109]], i64* [[LLV]], align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP110:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP111:%.*]] = atomicrmw min i64* [[LLX]], i64 [[TMP110]] seq_cst, align 8
+// CHECK-NEXT:    store i64 [[TMP111]], i64* [[LLV]], align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP112:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP113:%.*]] = atomicrmw max i64* [[LLX]], i64 [[TMP112]] seq_cst, align 8
+// CHECK-NEXT:    store i64 [[TMP113]], i64* [[LLV]], align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP114:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP115:%.*]] = load i64, i64* [[LLD]], align 8
+// CHECK-NEXT:    [[TMP116:%.*]] = cmpxchg i64* [[LLX]], i64 [[TMP114]], i64 [[TMP115]] seq_cst seq_cst, align 8
+// CHECK-NEXT:    [[TMP117:%.*]] = extractvalue { i64, i1 } [[TMP116]], 0
+// CHECK-NEXT:    store i64 [[TMP117]], i64* [[LLV]], align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP118:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP119:%.*]] = atomicrmw min i64* [[LLX]], i64 [[TMP118]] seq_cst, align 8
+// CHECK-NEXT:    [[TMP120:%.*]] = icmp slt i64 [[TMP119]], [[TMP118]]
+// CHECK-NEXT:    [[TMP121:%.*]] = select i1 [[TMP120]], i64 [[TMP118]], i64 [[TMP119]]
+// CHECK-NEXT:    store i64 [[TMP121]], i64* [[LLV]], align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP122:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP123:%.*]] = atomicrmw max i64* [[LLX]], i64 [[TMP122]] seq_cst, align 8
+// CHECK-NEXT:    [[TMP124:%.*]] = icmp sgt i64 [[TMP123]], [[TMP122]]
+// CHECK-NEXT:    [[TMP125:%.*]] = select i1 [[TMP124]], i64 [[TMP122]], i64 [[TMP123]]
+// CHECK-NEXT:    store i64 [[TMP125]], i64* [[LLV]], align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP126:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP127:%.*]] = load i64, i64* [[LLD]], align 8
+// CHECK-NEXT:    [[TMP128:%.*]] = cmpxchg i64* [[LLX]], i64 [[TMP126]], i64 [[TMP127]] seq_cst seq_cst, align 8
+// CHECK-NEXT:    [[TMP129:%.*]] = extractvalue { i64, i1 } [[TMP128]], 0
+// CHECK-NEXT:    [[TMP130:%.*]] = extractvalue { i64, i1 } [[TMP128]], 1
+// CHECK-NEXT:    [[TMP131:%.*]] = select i1 [[TMP130]], i64 [[TMP126]], i64 [[TMP129]]
+// CHECK-NEXT:    store i64 [[TMP131]], i64* [[LLV]], align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP132:%.*]] = load i64, i64* [[LLV]], align 8
+// CHECK-NEXT:    ret i64 [[TMP132]]
+//
+//
+// CHECK-LABEL: define {{[^@]+}}@ullxevd
+// CHECK-SAME: () #[[ATTR0]] {
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[ULLX:%.*]] = alloca i64, align 8
+// CHECK-NEXT:    [[ULLV:%.*]] = alloca i64, align 8
+// CHECK-NEXT:    [[ULLE:%.*]] = alloca i64, align 8
+// CHECK-NEXT:    [[ULLD:%.*]] = alloca i64, align 8
+// CHECK-NEXT:    [[TMP0:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP1:%.*]] = atomicrmw umin i64* [[ULLX]], i64 [[TMP0]] monotonic, align 8
+// CHECK-NEXT:    store i64 [[TMP1]], i64* [[ULLV]], align 8
+// CHECK-NEXT:    [[TMP2:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP3:%.*]] = atomicrmw umax i64* [[ULLX]], i64 [[TMP2]] monotonic, align 8
+// CHECK-NEXT:    store i64 [[TMP3]], i64* [[ULLV]], align 8
+// CHECK-NEXT:    [[TMP4:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP5:%.*]] = load i64, i64* [[ULLD]], align 8
+// CHECK-NEXT:    [[TMP6:%.*]] = cmpxchg i64* [[ULLX]], i64 [[TMP4]], i64 [[TMP5]] monotonic monotonic, align 8
+// CHECK-NEXT:    [[TMP7:%.*]] = extractvalue { i64, i1 } [[TMP6]], 0
+// CHECK-NEXT:    store i64 [[TMP7]], i64* [[ULLV]], align 8
+// CHECK-NEXT:    [[TMP8:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP9:%.*]] = atomicrmw umin i64* [[ULLX]], i64 [[TMP8]] monotonic, align 8
+// CHECK-NEXT:    [[TMP10:%.*]] = icmp ult i64 [[TMP9]], [[TMP8]]
+// CHECK-NEXT:    [[TMP11:%.*]] = select i1 [[TMP10]], i64 [[TMP8]], i64 [[TMP9]]
+// CHECK-NEXT:    store i64 [[TMP11]], i64* [[ULLV]], align 8
+// CHECK-NEXT:    [[TMP12:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP13:%.*]] = atomicrmw umax i64* [[ULLX]], i64 [[TMP12]] monotonic, align 8
+// CHECK-NEXT:    [[TMP14:%.*]] = icmp ugt i64 [[TMP13]], [[TMP12]]
+// CHECK-NEXT:    [[TMP15:%.*]] = select i1 [[TMP14]], i64 [[TMP12]], i64 [[TMP13]]
+// CHECK-NEXT:    store i64 [[TMP15]], i64* [[ULLV]], align 8
+// CHECK-NEXT:    [[TMP16:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP17:%.*]] = load i64, i64* [[ULLD]], align 8
+// CHECK-NEXT:    [[TMP18:%.*]] = cmpxchg i64* [[ULLX]], i64 [[TMP16]], i64 [[TMP17]] monotonic monotonic, align 8
+// CHECK-NEXT:    [[TMP19:%.*]] = extractvalue { i64, i1 } [[TMP18]], 0
+// CHECK-NEXT:    [[TMP20:%.*]] = extractvalue { i64, i1 } [[TMP18]], 1
+// CHECK-NEXT:    [[TMP21:%.*]] = select i1 [[TMP20]], i64 [[TMP16]], i64 [[TMP19]]
+// CHECK-NEXT:    store i64 [[TMP21]], i64* [[ULLV]], align 8
+// CHECK-NEXT:    [[TMP22:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP23:%.*]] = atomicrmw umin i64* [[ULLX]], i64 [[TMP22]] acq_rel, align 8
+// CHECK-NEXT:    store i64 [[TMP23]], i64* [[ULLV]], align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP24:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP25:%.*]] = atomicrmw umax i64* [[ULLX]], i64 [[TMP24]] acq_rel, align 8
+// CHECK-NEXT:    store i64 [[TMP25]], i64* [[ULLV]], align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP26:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP27:%.*]] = load i64, i64* [[ULLD]], align 8
+// CHECK-NEXT:    [[TMP28:%.*]] = cmpxchg i64* [[ULLX]], i64 [[TMP26]], i64 [[TMP27]] acq_rel acquire, align 8
+// CHECK-NEXT:    [[TMP29:%.*]] = extractvalue { i64, i1 } [[TMP28]], 0
+// CHECK-NEXT:    store i64 [[TMP29]], i64* [[ULLV]], align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP30:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP31:%.*]] = atomicrmw umin i64* [[ULLX]], i64 [[TMP30]] acq_rel, align 8
+// CHECK-NEXT:    [[TMP32:%.*]] = icmp ult i64 [[TMP31]], [[TMP30]]
+// CHECK-NEXT:    [[TMP33:%.*]] = select i1 [[TMP32]], i64 [[TMP30]], i64 [[TMP31]]
+// CHECK-NEXT:    store i64 [[TMP33]], i64* [[ULLV]], align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP34:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP35:%.*]] = atomicrmw umax i64* [[ULLX]], i64 [[TMP34]] acq_rel, align 8
+// CHECK-NEXT:    [[TMP36:%.*]] = icmp ugt i64 [[TMP35]], [[TMP34]]
+// CHECK-NEXT:    [[TMP37:%.*]] = select i1 [[TMP36]], i64 [[TMP34]], i64 [[TMP35]]
+// CHECK-NEXT:    store i64 [[TMP37]], i64* [[ULLV]], align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP38:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP39:%.*]] = load i64, i64* [[ULLD]], align 8
+// CHECK-NEXT:    [[TMP40:%.*]] = cmpxchg i64* [[ULLX]], i64 [[TMP38]], i64 [[TMP39]] acq_rel acquire, align 8
+// CHECK-NEXT:    [[TMP41:%.*]] = extractvalue { i64, i1 } [[TMP40]], 0
+// CHECK-NEXT:    [[TMP42:%.*]] = extractvalue { i64, i1 } [[TMP40]], 1
+// CHECK-NEXT:    [[TMP43:%.*]] = select i1 [[TMP42]], i64 [[TMP38]], i64 [[TMP41]]
+// CHECK-NEXT:    store i64 [[TMP43]], i64* [[ULLV]], align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP44:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP45:%.*]] = atomicrmw umin i64* [[ULLX]], i64 [[TMP44]] acquire, align 8
+// CHECK-NEXT:    store i64 [[TMP45]], i64* [[ULLV]], align 8
+// CHECK-NEXT:    [[TMP46:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP47:%.*]] = atomicrmw umax i64* [[ULLX]], i64 [[TMP46]] acquire, align 8
+// CHECK-NEXT:    store i64 [[TMP47]], i64* [[ULLV]], align 8
+// CHECK-NEXT:    [[TMP48:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP49:%.*]] = load i64, i64* [[ULLD]], align 8
+// CHECK-NEXT:    [[TMP50:%.*]] = cmpxchg i64* [[ULLX]], i64 [[TMP48]], i64 [[TMP49]] acquire acquire, align 8
+// CHECK-NEXT:    [[TMP51:%.*]] = extractvalue { i64, i1 } [[TMP50]], 0
+// CHECK-NEXT:    store i64 [[TMP51]], i64* [[ULLV]], align 8
+// CHECK-NEXT:    [[TMP52:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP53:%.*]] = atomicrmw umin i64* [[ULLX]], i64 [[TMP52]] acquire, align 8
+// CHECK-NEXT:    [[TMP54:%.*]] = icmp ult i64 [[TMP53]], [[TMP52]]
+// CHECK-NEXT:    [[TMP55:%.*]] = select i1 [[TMP54]], i64 [[TMP52]], i64 [[TMP53]]
+// CHECK-NEXT:    store i64 [[TMP55]], i64* [[ULLV]], align 8
+// CHECK-NEXT:    [[TMP56:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP57:%.*]] = atomicrmw umax i64* [[ULLX]], i64 [[TMP56]] acquire, align 8
+// CHECK-NEXT:    [[TMP58:%.*]] = icmp ugt i64 [[TMP57]], [[TMP56]]
+// CHECK-NEXT:    [[TMP59:%.*]] = select i1 [[TMP58]], i64 [[TMP56]], i64 [[TMP57]]
+// CHECK-NEXT:    store i64 [[TMP59]], i64* [[ULLV]], align 8
+// CHECK-NEXT:    [[TMP60:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP61:%.*]] = load i64, i64* [[ULLD]], align 8
+// CHECK-NEXT:    [[TMP62:%.*]] = cmpxchg i64* [[ULLX]], i64 [[TMP60]], i64 [[TMP61]] acquire acquire, align 8
+// CHECK-NEXT:    [[TMP63:%.*]] = extractvalue { i64, i1 } [[TMP62]], 0
+// CHECK-NEXT:    [[TMP64:%.*]] = extractvalue { i64, i1 } [[TMP62]], 1
+// CHECK-NEXT:    [[TMP65:%.*]] = select i1 [[TMP64]], i64 [[TMP60]], i64 [[TMP63]]
+// CHECK-NEXT:    store i64 [[TMP65]], i64* [[ULLV]], align 8
+// CHECK-NEXT:    [[TMP66:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP67:%.*]] = atomicrmw umin i64* [[ULLX]], i64 [[TMP66]] monotonic, align 8
+// CHECK-NEXT:    store i64 [[TMP67]], i64* [[ULLV]], align 8
+// CHECK-NEXT:    [[TMP68:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP69:%.*]] = atomicrmw umax i64* [[ULLX]], i64 [[TMP68]] monotonic, align 8
+// CHECK-NEXT:    store i64 [[TMP69]], i64* [[ULLV]], align 8
+// CHECK-NEXT:    [[TMP70:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP71:%.*]] = load i64, i64* [[ULLD]], align 8
+// CHECK-NEXT:    [[TMP72:%.*]] = cmpxchg i64* [[ULLX]], i64 [[TMP70]], i64 [[TMP71]] monotonic monotonic, align 8
+// CHECK-NEXT:    [[TMP73:%.*]] = extractvalue { i64, i1 } [[TMP72]], 0
+// CHECK-NEXT:    store i64 [[TMP73]], i64* [[ULLV]], align 8
+// CHECK-NEXT:    [[TMP74:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP75:%.*]] = atomicrmw umin i64* [[ULLX]], i64 [[TMP74]] monotonic, align 8
+// CHECK-NEXT:    [[TMP76:%.*]] = icmp ult i64 [[TMP75]], [[TMP74]]
+// CHECK-NEXT:    [[TMP77:%.*]] = select i1 [[TMP76]], i64 [[TMP74]], i64 [[TMP75]]
+// CHECK-NEXT:    store i64 [[TMP77]], i64* [[ULLV]], align 8
+// CHECK-NEXT:    [[TMP78:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP79:%.*]] = atomicrmw umax i64* [[ULLX]], i64 [[TMP78]] monotonic, align 8
+// CHECK-NEXT:    [[TMP80:%.*]] = icmp ugt i64 [[TMP79]], [[TMP78]]
+// CHECK-NEXT:    [[TMP81:%.*]] = select i1 [[TMP80]], i64 [[TMP78]], i64 [[TMP79]]
+// CHECK-NEXT:    store i64 [[TMP81]], i64* [[ULLV]], align 8
+// CHECK-NEXT:    [[TMP82:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP83:%.*]] = load i64, i64* [[ULLD]], align 8
+// CHECK-NEXT:    [[TMP84:%.*]] = cmpxchg i64* [[ULLX]], i64 [[TMP82]], i64 [[TMP83]] monotonic monotonic, align 8
+// CHECK-NEXT:    [[TMP85:%.*]] = extractvalue { i64, i1 } [[TMP84]], 0
+// CHECK-NEXT:    [[TMP86:%.*]] = extractvalue { i64, i1 } [[TMP84]], 1
+// CHECK-NEXT:    [[TMP87:%.*]] = select i1 [[TMP86]], i64 [[TMP82]], i64 [[TMP85]]
+// CHECK-NEXT:    store i64 [[TMP87]], i64* [[ULLV]], align 8
+// CHECK-NEXT:    [[TMP88:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP89:%.*]] = atomicrmw umin i64* [[ULLX]], i64 [[TMP88]] release, align 8
+// CHECK-NEXT:    store i64 [[TMP89]], i64* [[ULLV]], align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP90:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP91:%.*]] = atomicrmw umax i64* [[ULLX]], i64 [[TMP90]] release, align 8
+// CHECK-NEXT:    store i64 [[TMP91]], i64* [[ULLV]], align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP92:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP93:%.*]] = load i64, i64* [[ULLD]], align 8
+// CHECK-NEXT:    [[TMP94:%.*]] = cmpxchg i64* [[ULLX]], i64 [[TMP92]], i64 [[TMP93]] release monotonic, align 8
+// CHECK-NEXT:    [[TMP95:%.*]] = extractvalue { i64, i1 } [[TMP94]], 0
+// CHECK-NEXT:    store i64 [[TMP95]], i64* [[ULLV]], align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP96:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP97:%.*]] = atomicrmw umin i64* [[ULLX]], i64 [[TMP96]] release, align 8
+// CHECK-NEXT:    [[TMP98:%.*]] = icmp ult i64 [[TMP97]], [[TMP96]]
+// CHECK-NEXT:    [[TMP99:%.*]] = select i1 [[TMP98]], i64 [[TMP96]], i64 [[TMP97]]
+// CHECK-NEXT:    store i64 [[TMP99]], i64* [[ULLV]], align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP100:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP101:%.*]] = atomicrmw umax i64* [[ULLX]], i64 [[TMP100]] release, align 8
+// CHECK-NEXT:    [[TMP102:%.*]] = icmp ugt i64 [[TMP101]], [[TMP100]]
+// CHECK-NEXT:    [[TMP103:%.*]] = select i1 [[TMP102]], i64 [[TMP100]], i64 [[TMP101]]
+// CHECK-NEXT:    store i64 [[TMP103]], i64* [[ULLV]], align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP104:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP105:%.*]] = load i64, i64* [[ULLD]], align 8
+// CHECK-NEXT:    [[TMP106:%.*]] = cmpxchg i64* [[ULLX]], i64 [[TMP104]], i64 [[TMP105]] release monotonic, align 8
+// CHECK-NEXT:    [[TMP107:%.*]] = extractvalue { i64, i1 } [[TMP106]], 0
+// CHECK-NEXT:    [[TMP108:%.*]] = extractvalue { i64, i1 } [[TMP106]], 1
+// CHECK-NEXT:    [[TMP109:%.*]] = select i1 [[TMP108]], i64 [[TMP104]], i64 [[TMP107]]
+// CHECK-NEXT:    store i64 [[TMP109]], i64* [[ULLV]], align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP110:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP111:%.*]] = atomicrmw umin i64* [[ULLX]], i64 [[TMP110]] seq_cst, align 8
+// CHECK-NEXT:    store i64 [[TMP111]], i64* [[ULLV]], align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP112:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP113:%.*]] = atomicrmw umax i64* [[ULLX]], i64 [[TMP112]] seq_cst, align 8
+// CHECK-NEXT:    store i64 [[TMP113]], i64* [[ULLV]], align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP114:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP115:%.*]] = load i64, i64* [[ULLD]], align 8
+// CHECK-NEXT:    [[TMP116:%.*]] = cmpxchg i64* [[ULLX]], i64 [[TMP114]], i64 [[TMP115]] seq_cst seq_cst, align 8
+// CHECK-NEXT:    [[TMP117:%.*]] = extractvalue { i64, i1 } [[TMP116]], 0
+// CHECK-NEXT:    store i64 [[TMP117]], i64* [[ULLV]], align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP118:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP119:%.*]] = atomicrmw umin i64* [[ULLX]], i64 [[TMP118]] seq_cst, align 8
+// CHECK-NEXT:    [[TMP120:%.*]] = icmp ult i64 [[TMP119]], [[TMP118]]
+// CHECK-NEXT:    [[TMP121:%.*]] = select i1 [[TMP120]], i64 [[TMP118]], i64 [[TMP119]]
+// CHECK-NEXT:    store i64 [[TMP121]], i64* [[ULLV]], align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP122:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP123:%.*]] = atomicrmw umax i64* [[ULLX]], i64 [[TMP122]] seq_cst, align 8
+// CHECK-NEXT:    [[TMP124:%.*]] = icmp ugt i64 [[TMP123]], [[TMP122]]
+// CHECK-NEXT:    [[TMP125:%.*]] = select i1 [[TMP124]], i64 [[TMP122]], i64 [[TMP123]]
+// CHECK-NEXT:    store i64 [[TMP125]], i64* [[ULLV]], align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP126:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP127:%.*]] = load i64, i64* [[ULLD]], align 8
+// CHECK-NEXT:    [[TMP128:%.*]] = cmpxchg i64* [[ULLX]], i64 [[TMP126]], i64 [[TMP127]] seq_cst seq_cst, align 8
+// CHECK-NEXT:    [[TMP129:%.*]] = extractvalue { i64, i1 } [[TMP128]], 0
+// CHECK-NEXT:    [[TMP130:%.*]] = extractvalue { i64, i1 } [[TMP128]], 1
+// CHECK-NEXT:    [[TMP131:%.*]] = select i1 [[TMP130]], i64 [[TMP126]], i64 [[TMP129]]
+// CHECK-NEXT:    store i64 [[TMP131]], i64* [[ULLV]], align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP132:%.*]] = load i64, i64* [[ULLV]], align 8
+// CHECK-NEXT:    ret i64 [[TMP132]]
+//
+//
+// CHECK-LABEL: define {{[^@]+}}@fxevd
+// CHECK-SAME: () #[[ATTR0]] {
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[FX:%.*]] = alloca float, align 4
+// CHECK-NEXT:    [[FV:%.*]] = alloca float, align 4
+// CHECK-NEXT:    [[FE:%.*]] = alloca float, align 4
+// CHECK-NEXT:    [[FD:%.*]] = alloca float, align 4
+// CHECK-NEXT:    [[TMP0:%.*]] = load float, float* [[FE]], align 4
+// CHECK-NEXT:    [[TMP1:%.*]] = atomicrmw fmin float* [[FX]], float [[TMP0]] monotonic, align 4
+// CHECK-NEXT:    store float [[TMP1]], float* [[FV]], align 4
+// CHECK-NEXT:    [[TMP2:%.*]] = load float, float* [[FE]], align 4
+// CHECK-NEXT:    [[TMP3:%.*]] = atomicrmw fmax float* [[FX]], float [[TMP2]] monotonic, align 4
+// CHECK-NEXT:    store float [[TMP3]], float* [[FV]], align 4
+// CHECK-NEXT:    [[TMP4:%.*]] = load float, float* [[FE]], align 4
+// CHECK-NEXT:    [[TMP5:%.*]] = load float, float* [[FD]], align 4
+// CHECK-NEXT:    [[TMP6:%.*]] = bitcast float* [[FX]] to i32*
+// CHECK-NEXT:    [[TMP7:%.*]] = bitcast float [[TMP4]] to i32
+// CHECK-NEXT:    [[TMP8:%.*]] = bitcast float [[TMP5]] to i32
+// CHECK-NEXT:    [[TMP9:%.*]] = cmpxchg i32* [[TMP6]], i32 [[TMP7]], i32 [[TMP8]] monotonic monotonic, align 4
+// CHECK-NEXT:    [[TMP10:%.*]] = extractvalue { i32, i1 } [[TMP9]], 0
+// CHECK-NEXT:    [[TMP11:%.*]] = bitcast i32 [[TMP10]] to float
+// CHECK-NEXT:    store float [[TMP11]], float* [[FV]], align 4
+// CHECK-NEXT:    [[TMP12:%.*]] = load float, float* [[FE]], align 4
+// CHECK-NEXT:    [[TMP13:%.*]] = atomicrmw fmin float* [[FX]], float [[TMP12]] monotonic, align 4
+// CHECK-NEXT:    [[TMP14:%.*]] = fcmp olt float [[TMP13]], [[TMP12]]
+// CHECK-NEXT:    [[TMP15:%.*]] = select i1 [[TMP14]], float [[TMP12]], float [[TMP13]]
+// CHECK-NEXT:    store float [[TMP15]], float* [[FV]], align 4
+// CHECK-NEXT:    [[TMP16:%.*]] = load float, float* [[FE]], align 4
+// CHECK-NEXT:    [[TMP17:%.*]] = atomicrmw fmax float* [[FX]], float [[TMP16]] monotonic, align 4
+// CHECK-NEXT:    [[TMP18:%.*]] = fcmp ogt float [[TMP17]], [[TMP16]]
+// CHECK-NEXT:    [[TMP19:%.*]] = select i1 [[TMP18]], float [[TMP16]], float [[TMP17]]
+// CHECK-NEXT:    store float [[TMP19]], float* [[FV]], align 4
+// CHECK-NEXT:    [[TMP20:%.*]] = load float, float* [[FE]], align 4
+// CHECK-NEXT:    [[TMP21:%.*]] = load float, float* [[FD]], align 4
+// CHECK-NEXT:    [[TMP22:%.*]] = bitcast float* [[FX]] to i32*
+// CHECK-NEXT:    [[TMP23:%.*]] = bitcast float [[TMP20]] to i32
+// CHECK-NEXT:    [[TMP24:%.*]] = bitcast float [[TMP21]] to i32
+// CHECK-NEXT:    [[TMP25:%.*]] = cmpxchg i32* [[TMP22]], i32 [[TMP23]], i32 [[TMP24]] monotonic monotonic, align 4
+// CHECK-NEXT:    [[TMP26:%.*]] = extractvalue { i32, i1 } [[TMP25]], 0
+// CHECK-NEXT:    [[TMP27:%.*]] = bitcast i32 [[TMP26]] to float
+// CHECK-NEXT:    [[TMP28:%.*]] = extractvalue { i32, i1 } [[TMP25]], 1
+// CHECK-NEXT:    [[TMP29:%.*]] = select i1 [[TMP28]], float [[TMP20]], float [[TMP27]]
+// CHECK-NEXT:    store float [[TMP29]], float* [[FV]], align 4
+// CHECK-NEXT:    [[TMP30:%.*]] = load float, float* [[FE]], align 4
+// CHECK-NEXT:    [[TMP31:%.*]] = atomicrmw fmin float* [[FX]], float [[TMP30]] acq_rel, align 4
+// CHECK-NEXT:    store float [[TMP31]], float* [[FV]], align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP32:%.*]] = load float, float* [[FE]], align 4
+// CHECK-NEXT:    [[TMP33:%.*]] = atomicrmw fmax float* [[FX]], float [[TMP32]] acq_rel, align 4
+// CHECK-NEXT:    store float [[TMP33]], float* [[FV]], align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP34:%.*]] = load float, float* [[FE]], align 4
+// CHECK-NEXT:    [[TMP35:%.*]] = load float, float* [[FD]], align 4
+// CHECK-NEXT:    [[TMP36:%.*]] = bitcast float* [[FX]] to i32*
+// CHECK-NEXT:    [[TMP37:%.*]] = bitcast float [[TMP34]] to i32
+// CHECK-NEXT:    [[TMP38:%.*]] = bitcast float [[TMP35]] to i32
+// CHECK-NEXT:    [[TMP39:%.*]] = cmpxchg i32* [[TMP36]], i32 [[TMP37]], i32 [[TMP38]] acq_rel acquire, align 4
+// CHECK-NEXT:    [[TMP40:%.*]] = extractvalue { i32, i1 } [[TMP39]], 0
+// CHECK-NEXT:    [[TMP41:%.*]] = bitcast i32 [[TMP40]] to float
+// CHECK-NEXT:    store float [[TMP41]], float* [[FV]], align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP42:%.*]] = load float, float* [[FE]], align 4
+// CHECK-NEXT:    [[TMP43:%.*]] = atomicrmw fmin float* [[FX]], float [[TMP42]] acq_rel, align 4
+// CHECK-NEXT:    [[TMP44:%.*]] = fcmp olt float [[TMP43]], [[TMP42]]
+// CHECK-NEXT:    [[TMP45:%.*]] = select i1 [[TMP44]], float [[TMP42]], float [[TMP43]]
+// CHECK-NEXT:    store float [[TMP45]], float* [[FV]], align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP46:%.*]] = load float, float* [[FE]], align 4
+// CHECK-NEXT:    [[TMP47:%.*]] = atomicrmw fmax float* [[FX]], float [[TMP46]] acq_rel, align 4
+// CHECK-NEXT:    [[TMP48:%.*]] = fcmp ogt float [[TMP47]], [[TMP46]]
+// CHECK-NEXT:    [[TMP49:%.*]] = select i1 [[TMP48]], float [[TMP46]], float [[TMP47]]
+// CHECK-NEXT:    store float [[TMP49]], float* [[FV]], align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP50:%.*]] = load float, float* [[FE]], align 4
+// CHECK-NEXT:    [[TMP51:%.*]] = load float, float* [[FD]], align 4
+// CHECK-NEXT:    [[TMP52:%.*]] = bitcast float* [[FX]] to i32*
+// CHECK-NEXT:    [[TMP53:%.*]] = bitcast float [[TMP50]] to i32
+// CHECK-NEXT:    [[TMP54:%.*]] = bitcast float [[TMP51]] to i32
+// CHECK-NEXT:    [[TMP55:%.*]] = cmpxchg i32* [[TMP52]], i32 [[TMP53]], i32 [[TMP54]] acq_rel acquire, align 4
+// CHECK-NEXT:    [[TMP56:%.*]] = extractvalue { i32, i1 } [[TMP55]], 0
+// CHECK-NEXT:    [[TMP57:%.*]] = bitcast i32 [[TMP56]] to float
+// CHECK-NEXT:    [[TMP58:%.*]] = extractvalue { i32, i1 } [[TMP55]], 1
+// CHECK-NEXT:    [[TMP59:%.*]] = select i1 [[TMP58]], float [[TMP50]], float [[TMP57]]
+// CHECK-NEXT:    store float [[TMP59]], float* [[FV]], align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP60:%.*]] = load float, float* [[FE]], align 4
+// CHECK-NEXT:    [[TMP61:%.*]] = atomicrmw fmin float* [[FX]], float [[TMP60]] acquire, align 4
+// CHECK-NEXT:    store float [[TMP61]], float* [[FV]], align 4
+// CHECK-NEXT:    [[TMP62:%.*]] = load float, float* [[FE]], align 4
+// CHECK-NEXT:    [[TMP63:%.*]] = atomicrmw fmax float* [[FX]], float [[TMP62]] acquire, align 4
+// CHECK-NEXT:    store float [[TMP63]], float* [[FV]], align 4
+// CHECK-NEXT:    [[TMP64:%.*]] = load float, float* [[FE]], align 4
+// CHECK-NEXT:    [[TMP65:%.*]] = load float, float* [[FD]], align 4
+// CHECK-NEXT:    [[TMP66:%.*]] = bitcast float* [[FX]] to i32*
+// CHECK-NEXT:    [[TMP67:%.*]] = bitcast float [[TMP64]] to i32
+// CHECK-NEXT:    [[TMP68:%.*]] = bitcast float [[TMP65]] to i32
+// CHECK-NEXT:    [[TMP69:%.*]] = cmpxchg i32* [[TMP66]], i32 [[TMP67]], i32 [[TMP68]] acquire acquire, align 4
+// CHECK-NEXT:    [[TMP70:%.*]] = extractvalue { i32, i1 } [[TMP69]], 0
+// CHECK-NEXT:    [[TMP71:%.*]] = bitcast i32 [[TMP70]] to float
+// CHECK-NEXT:    store float [[TMP71]], float* [[FV]], align 4
+// CHECK-NEXT:    [[TMP72:%.*]] = load float, float* [[FE]], align 4
+// CHECK-NEXT:    [[TMP73:%.*]] = atomicrmw fmin float* [[FX]], float [[TMP72]] acquire, align 4
+// CHECK-NEXT:    [[TMP74:%.*]] = fcmp olt float [[TMP73]], [[TMP72]]
+// CHECK-NEXT:    [[TMP75:%.*]] = select i1 [[TMP74]], float [[TMP72]], float [[TMP73]]
+// CHECK-NEXT:    store float [[TMP75]], float* [[FV]], align 4
+// CHECK-NEXT:    [[TMP76:%.*]] = load float, float* [[FE]], align 4
+// CHECK-NEXT:    [[TMP77:%.*]] = atomicrmw fmax float* [[FX]], float [[TMP76]] acquire, align 4
+// CHECK-NEXT:    [[TMP78:%.*]] = fcmp ogt float [[TMP77]], [[TMP76]]
+// CHECK-NEXT:    [[TMP79:%.*]] = select i1 [[TMP78]], float [[TMP76]], float [[TMP77]]
+// CHECK-NEXT:    store float [[TMP79]], float* [[FV]], align 4
+// CHECK-NEXT:    [[TMP80:%.*]] = load float, float* [[FE]], align 4
+// CHECK-NEXT:    [[TMP81:%.*]] = load float, float* [[FD]], align 4
+// CHECK-NEXT:    [[TMP82:%.*]] = bitcast float* [[FX]] to i32*
+// CHECK-NEXT:    [[TMP83:%.*]] = bitcast float [[TMP80]] to i32
+// CHECK-NEXT:    [[TMP84:%.*]] = bitcast float [[TMP81]] to i32
+// CHECK-NEXT:    [[TMP85:%.*]] = cmpxchg i32* [[TMP82]], i32 [[TMP83]], i32 [[TMP84]] acquire acquire, align 4
+// CHECK-NEXT:    [[TMP86:%.*]] = extractvalue { i32, i1 } [[TMP85]], 0
+// CHECK-NEXT:    [[TMP87:%.*]] = bitcast i32 [[TMP86]] to float
+// CHECK-NEXT:    [[TMP88:%.*]] = extractvalue { i32, i1 } [[TMP85]], 1
+// CHECK-NEXT:    [[TMP89:%.*]] = select i1 [[TMP88]], float [[TMP80]], float [[TMP87]]
+// CHECK-NEXT:    store float [[TMP89]], float* [[FV]], align 4
+// CHECK-NEXT:    [[TMP90:%.*]] = load float, float* [[FE]], align 4
+// CHECK-NEXT:    [[TMP91:%.*]] = atomicrmw fmin float* [[FX]], float [[TMP90]] monotonic, align 4
+// CHECK-NEXT:    store float [[TMP91]], float* [[FV]], align 4
+// CHECK-NEXT:    [[TMP92:%.*]] = load float, float* [[FE]], align 4
+// CHECK-NEXT:    [[TMP93:%.*]] = atomicrmw fmax float* [[FX]], float [[TMP92]] monotonic, align 4
+// CHECK-NEXT:    store float [[TMP93]], float* [[FV]], align 4
+// CHECK-NEXT:    [[TMP94:%.*]] = load float, float* [[FE]], align 4
+// CHECK-NEXT:    [[TMP95:%.*]] = load float, float* [[FD]], align 4
+// CHECK-NEXT:    [[TMP96:%.*]] = bitcast float* [[FX]] to i32*
+// CHECK-NEXT:    [[TMP97:%.*]] = bitcast float [[TMP94]] to i32
+// CHECK-NEXT:    [[TMP98:%.*]] = bitcast float [[TMP95]] to i32
+// CHECK-NEXT:    [[TMP99:%.*]] = cmpxchg i32* [[TMP96]], i32 [[TMP97]], i32 [[TMP98]] monotonic monotonic, align 4
+// CHECK-NEXT:    [[TMP100:%.*]] = extractvalue { i32, i1 } [[TMP99]], 0
+// CHECK-NEXT:    [[TMP101:%.*]] = bitcast i32 [[TMP100]] to float
+// CHECK-NEXT:    store float [[TMP101]], float* [[FV]], align 4
+// CHECK-NEXT:    [[TMP102:%.*]] = load float, float* [[FE]], align 4
+// CHECK-NEXT:    [[TMP103:%.*]] = atomicrmw fmin float* [[FX]], float [[TMP102]] monotonic, align 4
+// CHECK-NEXT:    [[TMP104:%.*]] = fcmp olt float [[TMP103]], [[TMP102]]
+// CHECK-NEXT:    [[TMP105:%.*]] = select i1 [[TMP104]], float [[TMP102]], float [[TMP103]]
+// CHECK-NEXT:    store float [[TMP105]], float* [[FV]], align 4
+// CHECK-NEXT:    [[TMP106:%.*]] = load float, float* [[FE]], align 4
+// CHECK-NEXT:    [[TMP107:%.*]] = atomicrmw fmax float* [[FX]], float [[TMP106]] monotonic, align 4
+// CHECK-NEXT:    [[TMP108:%.*]] = fcmp ogt float [[TMP107]], [[TMP106]]
+// CHECK-NEXT:    [[TMP109:%.*]] = select i1 [[TMP108]], float [[TMP106]], float [[TMP107]]
+// CHECK-NEXT:    store float [[TMP109]], float* [[FV]], align 4
+// CHECK-NEXT:    [[TMP110:%.*]] = load float, float* [[FE]], align 4
+// CHECK-NEXT:    [[TMP111:%.*]] = load float, float* [[FD]], align 4
+// CHECK-NEXT:    [[TMP112:%.*]] = bitcast float* [[FX]] to i32*
+// CHECK-NEXT:    [[TMP113:%.*]] = bitcast float [[TMP110]] to i32
+// CHECK-NEXT:    [[TMP114:%.*]] = bitcast float [[TMP111]] to i32
+// CHECK-NEXT:    [[TMP115:%.*]] = cmpxchg i32* [[TMP112]], i32 [[TMP113]], i32 [[TMP114]] monotonic monotonic, align 4
+// CHECK-NEXT:    [[TMP116:%.*]] = extractvalue { i32, i1 } [[TMP115]], 0
+// CHECK-NEXT:    [[TMP117:%.*]] = bitcast i32 [[TMP116]] to float
+// CHECK-NEXT:    [[TMP118:%.*]] = extractvalue { i32, i1 } [[TMP115]], 1
+// CHECK-NEXT:    [[TMP119:%.*]] = select i1 [[TMP118]], float [[TMP110]], float [[TMP117]]
+// CHECK-NEXT:    store float [[TMP119]], float* [[FV]], align 4
+// CHECK-NEXT:    [[TMP120:%.*]] = load float, float* [[FE]], align 4
+// CHECK-NEXT:    [[TMP121:%.*]] = atomicrmw fmin float* [[FX]], float [[TMP120]] release, align 4
+// CHECK-NEXT:    store float [[TMP121]], float* [[FV]], align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP122:%.*]] = load float, float* [[FE]], align 4
+// CHECK-NEXT:    [[TMP123:%.*]] = atomicrmw fmax float* [[FX]], float [[TMP122]] release, align 4
+// CHECK-NEXT:    store float [[TMP123]], float* [[FV]], align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP124:%.*]] = load float, float* [[FE]], align 4
+// CHECK-NEXT:    [[TMP125:%.*]] = load float, float* [[FD]], align 4
+// CHECK-NEXT:    [[TMP126:%.*]] = bitcast float* [[FX]] to i32*
+// CHECK-NEXT:    [[TMP127:%.*]] = bitcast float [[TMP124]] to i32
+// CHECK-NEXT:    [[TMP128:%.*]] = bitcast float [[TMP125]] to i32
+// CHECK-NEXT:    [[TMP129:%.*]] = cmpxchg i32* [[TMP126]], i32 [[TMP127]], i32 [[TMP128]] release monotonic, align 4
+// CHECK-NEXT:    [[TMP130:%.*]] = extractvalue { i32, i1 } [[TMP129]], 0
+// CHECK-NEXT:    [[TMP131:%.*]] = bitcast i32 [[TMP130]] to float
+// CHECK-NEXT:    store float [[TMP131]], float* [[FV]], align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP132:%.*]] = load float, float* [[FE]], align 4
+// CHECK-NEXT:    [[TMP133:%.*]] = atomicrmw fmin float* [[FX]], float [[TMP132]] release, align 4
+// CHECK-NEXT:    [[TMP134:%.*]] = fcmp olt float [[TMP133]], [[TMP132]]
+// CHECK-NEXT:    [[TMP135:%.*]] = select i1 [[TMP134]], float [[TMP132]], float [[TMP133]]
+// CHECK-NEXT:    store float [[TMP135]], float* [[FV]], align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP136:%.*]] = load float, float* [[FE]], align 4
+// CHECK-NEXT:    [[TMP137:%.*]] = atomicrmw fmax float* [[FX]], float [[TMP136]] release, align 4
+// CHECK-NEXT:    [[TMP138:%.*]] = fcmp ogt float [[TMP137]], [[TMP136]]
+// CHECK-NEXT:    [[TMP139:%.*]] = select i1 [[TMP138]], float [[TMP136]], float [[TMP137]]
+// CHECK-NEXT:    store float [[TMP139]], float* [[FV]], align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP140:%.*]] = load float, float* [[FE]], align 4
+// CHECK-NEXT:    [[TMP141:%.*]] = load float, float* [[FD]], align 4
+// CHECK-NEXT:    [[TMP142:%.*]] = bitcast float* [[FX]] to i32*
+// CHECK-NEXT:    [[TMP143:%.*]] = bitcast float [[TMP140]] to i32
+// CHECK-NEXT:    [[TMP144:%.*]] = bitcast float [[TMP141]] to i32
+// CHECK-NEXT:    [[TMP145:%.*]] = cmpxchg i32* [[TMP142]], i32 [[TMP143]], i32 [[TMP144]] release monotonic, align 4
+// CHECK-NEXT:    [[TMP146:%.*]] = extractvalue { i32, i1 } [[TMP145]], 0
+// CHECK-NEXT:    [[TMP147:%.*]] = bitcast i32 [[TMP146]] to float
+// CHECK-NEXT:    [[TMP148:%.*]] = extractvalue { i32, i1 } [[TMP145]], 1
+// CHECK-NEXT:    [[TMP149:%.*]] = select i1 [[TMP148]], float [[TMP140]], float [[TMP147]]
+// CHECK-NEXT:    store float [[TMP149]], float* [[FV]], align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP150:%.*]] = load float, float* [[FE]], align 4
+// CHECK-NEXT:    [[TMP151:%.*]] = atomicrmw fmin float* [[FX]], float [[TMP150]] seq_cst, align 4
+// CHECK-NEXT:    store float [[TMP151]], float* [[FV]], align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP152:%.*]] = load float, float* [[FE]], align 4
+// CHECK-NEXT:    [[TMP153:%.*]] = atomicrmw fmax float* [[FX]], float [[TMP152]] seq_cst, align 4
+// CHECK-NEXT:    store float [[TMP153]], float* [[FV]], align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP154:%.*]] = load float, float* [[FE]], align 4
+// CHECK-NEXT:    [[TMP155:%.*]] = load float, float* [[FD]], align 4
+// CHECK-NEXT:    [[TMP156:%.*]] = bitcast float* [[FX]] to i32*
+// CHECK-NEXT:    [[TMP157:%.*]] = bitcast float [[TMP154]] to i32
+// CHECK-NEXT:    [[TMP158:%.*]] = bitcast float [[TMP155]] to i32
+// CHECK-NEXT:    [[TMP159:%.*]] = cmpxchg i32* [[TMP156]], i32 [[TMP157]], i32 [[TMP158]] seq_cst seq_cst, align 4
+// CHECK-NEXT:    [[TMP160:%.*]] = extractvalue { i32, i1 } [[TMP159]], 0
+// CHECK-NEXT:    [[TMP161:%.*]] = bitcast i32 [[TMP160]] to float
+// CHECK-NEXT:    store float [[TMP161]], float* [[FV]], align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP162:%.*]] = load float, float* [[FE]], align 4
+// CHECK-NEXT:    [[TMP163:%.*]] = atomicrmw fmin float* [[FX]], float [[TMP162]] seq_cst, align 4
+// CHECK-NEXT:    [[TMP164:%.*]] = fcmp olt float [[TMP163]], [[TMP162]]
+// CHECK-NEXT:    [[TMP165:%.*]] = select i1 [[TMP164]], float [[TMP162]], float [[TMP163]]
+// CHECK-NEXT:    store float [[TMP165]], float* [[FV]], align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP166:%.*]] = load float, float* [[FE]], align 4
+// CHECK-NEXT:    [[TMP167:%.*]] = atomicrmw fmax float* [[FX]], float [[TMP166]] seq_cst, align 4
+// CHECK-NEXT:    [[TMP168:%.*]] = fcmp ogt float [[TMP167]], [[TMP166]]
+// CHECK-NEXT:    [[TMP169:%.*]] = select i1 [[TMP168]], float [[TMP166]], float [[TMP167]]
+// CHECK-NEXT:    store float [[TMP169]], float* [[FV]], align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP170:%.*]] = load float, float* [[FE]], align 4
+// CHECK-NEXT:    [[TMP171:%.*]] = load float, float* [[FD]], align 4
+// CHECK-NEXT:    [[TMP172:%.*]] = bitcast float* [[FX]] to i32*
+// CHECK-NEXT:    [[TMP173:%.*]] = bitcast float [[TMP170]] to i32
+// CHECK-NEXT:    [[TMP174:%.*]] = bitcast float [[TMP171]] to i32
+// CHECK-NEXT:    [[TMP175:%.*]] = cmpxchg i32* [[TMP172]], i32 [[TMP173]], i32 [[TMP174]] seq_cst seq_cst, align 4
+// CHECK-NEXT:    [[TMP176:%.*]] = extractvalue { i32, i1 } [[TMP175]], 0
+// CHECK-NEXT:    [[TMP177:%.*]] = bitcast i32 [[TMP176]] to float
+// CHECK-NEXT:    [[TMP178:%.*]] = extractvalue { i32, i1 } [[TMP175]], 1
+// CHECK-NEXT:    [[TMP179:%.*]] = select i1 [[TMP178]], float [[TMP170]], float [[TMP177]]
+// CHECK-NEXT:    store float [[TMP179]], float* [[FV]], align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP180:%.*]] = load float, float* [[FV]], align 4
+// CHECK-NEXT:    ret float [[TMP180]]
+//
+//
+// CHECK-LABEL: define {{[^@]+}}@dxevd
+// CHECK-SAME: () #[[ATTR0]] {
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[DX:%.*]] = alloca double, align 8
+// CHECK-NEXT:    [[DV:%.*]] = alloca double, align 8
+// CHECK-NEXT:    [[DE:%.*]] = alloca double, align 8
+// CHECK-NEXT:    [[DD:%.*]] = alloca double, align 8
+// CHECK-NEXT:    [[TMP0:%.*]] = load double, double* [[DE]], align 8
+// CHECK-NEXT:    [[TMP1:%.*]] = atomicrmw fmin double* [[DX]], double [[TMP0]] monotonic, align 8
+// CHECK-NEXT:    store double [[TMP1]], double* [[DV]], align 8
+// CHECK-NEXT:    [[TMP2:%.*]] = load double, double* [[DE]], align 8
+// CHECK-NEXT:    [[TMP3:%.*]] = atomicrmw fmax double* [[DX]], double [[TMP2]] monotonic, align 8
+// CHECK-NEXT:    store double [[TMP3]], double* [[DV]], align 8
+// CHECK-NEXT:    [[TMP4:%.*]] = load double, double* [[DE]], align 8
+// CHECK-NEXT:    [[TMP5:%.*]] = load double, double* [[DD]], align 8
+// CHECK-NEXT:    [[TMP6:%.*]] = bitcast double* [[DX]] to i64*
+// CHECK-NEXT:    [[TMP7:%.*]] = bitcast double [[TMP4]] to i64
+// CHECK-NEXT:    [[TMP8:%.*]] = bitcast double [[TMP5]] to i64
+// CHECK-NEXT:    [[TMP9:%.*]] = cmpxchg i64* [[TMP6]], i64 [[TMP7]], i64 [[TMP8]] monotonic monotonic, align 8
+// CHECK-NEXT:    [[TMP10:%.*]] = extractvalue { i64, i1 } [[TMP9]], 0
+// CHECK-NEXT:    [[TMP11:%.*]] = bitcast i64 [[TMP10]] to double
+// CHECK-NEXT:    store double [[TMP11]], double* [[DV]], align 8
+// CHECK-NEXT:    [[TMP12:%.*]] = load double, double* [[DE]], align 8
+// CHECK-NEXT:    [[TMP13:%.*]] = atomicrmw fmin double* [[DX]], double [[TMP12]] monotonic, align 8
+// CHECK-NEXT:    [[TMP14:%.*]] = fcmp olt double [[TMP13]], [[TMP12]]
+// CHECK-NEXT:    [[TMP15:%.*]] = select i1 [[TMP14]], double [[TMP12]], double [[TMP13]]
+// CHECK-NEXT:    store double [[TMP15]], double* [[DV]], align 8
+// CHECK-NEXT:    [[TMP16:%.*]] = load double, double* [[DE]], align 8
+// CHECK-NEXT:    [[TMP17:%.*]] = atomicrmw fmax double* [[DX]], double [[TMP16]] monotonic, align 8
+// CHECK-NEXT:    [[TMP18:%.*]] = fcmp ogt double [[TMP17]], [[TMP16]]
+// CHECK-NEXT:    [[TMP19:%.*]] = select i1 [[TMP18]], double [[TMP16]], double [[TMP17]]
+// CHECK-NEXT:    store double [[TMP19]], double* [[DV]], align 8
+// CHECK-NEXT:    [[TMP20:%.*]] = load double, double* [[DE]], align 8
+// CHECK-NEXT:    [[TMP21:%.*]] = load double, double* [[DD]], align 8
+// CHECK-NEXT:    [[TMP22:%.*]] = bitcast double* [[DX]] to i64*
+// CHECK-NEXT:    [[TMP23:%.*]] = bitcast double [[TMP20]] to i64
+// CHECK-NEXT:    [[TMP24:%.*]] = bitcast double [[TMP21]] to i64
+// CHECK-NEXT:    [[TMP25:%.*]] = cmpxchg i64* [[TMP22]], i64 [[TMP23]], i64 [[TMP24]] monotonic monotonic, align 8
+// CHECK-NEXT:    [[TMP26:%.*]] = extractvalue { i64, i1 } [[TMP25]], 0
+// CHECK-NEXT:    [[TMP27:%.*]] = bitcast i64 [[TMP26]] to double
+// CHECK-NEXT:    [[TMP28:%.*]] = extractvalue { i64, i1 } [[TMP25]], 1
+// CHECK-NEXT:    [[TMP29:%.*]] = select i1 [[TMP28]], double [[TMP20]], double [[TMP27]]
+// CHECK-NEXT:    store double [[TMP29]], double* [[DV]], align 8
+// CHECK-NEXT:    [[TMP30:%.*]] = load double, double* [[DE]], align 8
+// CHECK-NEXT:    [[TMP31:%.*]] = atomicrmw fmin double* [[DX]], double [[TMP30]] acq_rel, align 8
+// CHECK-NEXT:    store double [[TMP31]], double* [[DV]], align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP32:%.*]] = load double, double* [[DE]], align 8
+// CHECK-NEXT:    [[TMP33:%.*]] = atomicrmw fmax double* [[DX]], double [[TMP32]] acq_rel, align 8
+// CHECK-NEXT:    store double [[TMP33]], double* [[DV]], align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP34:%.*]] = load double, double* [[DE]], align 8
+// CHECK-NEXT:    [[TMP35:%.*]] = load double, double* [[DD]], align 8
+// CHECK-NEXT:    [[TMP36:%.*]] = bitcast double* [[DX]] to i64*
+// CHECK-NEXT:    [[TMP37:%.*]] = bitcast double [[TMP34]] to i64
+// CHECK-NEXT:    [[TMP38:%.*]] = bitcast double [[TMP35]] to i64
+// CHECK-NEXT:    [[TMP39:%.*]] = cmpxchg i64* [[TMP36]], i64 [[TMP37]], i64 [[TMP38]] acq_rel acquire, align 8
+// CHECK-NEXT:    [[TMP40:%.*]] = extractvalue { i64, i1 } [[TMP39]], 0
+// CHECK-NEXT:    [[TMP41:%.*]] = bitcast i64 [[TMP40]] to double
+// CHECK-NEXT:    store double [[TMP41]], double* [[DV]], align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP42:%.*]] = load double, double* [[DE]], align 8
+// CHECK-NEXT:    [[TMP43:%.*]] = atomicrmw fmin double* [[DX]], double [[TMP42]] acq_rel, align 8
+// CHECK-NEXT:    [[TMP44:%.*]] = fcmp olt double [[TMP43]], [[TMP42]]
+// CHECK-NEXT:    [[TMP45:%.*]] = select i1 [[TMP44]], double [[TMP42]], double [[TMP43]]
+// CHECK-NEXT:    store double [[TMP45]], double* [[DV]], align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP46:%.*]] = load double, double* [[DE]], align 8
+// CHECK-NEXT:    [[TMP47:%.*]] = atomicrmw fmax double* [[DX]], double [[TMP46]] acq_rel, align 8
+// CHECK-NEXT:    [[TMP48:%.*]] = fcmp ogt double [[TMP47]], [[TMP46]]
+// CHECK-NEXT:    [[TMP49:%.*]] = select i1 [[TMP48]], double [[TMP46]], double [[TMP47]]
+// CHECK-NEXT:    store double [[TMP49]], double* [[DV]], align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP50:%.*]] = load double, double* [[DE]], align 8
+// CHECK-NEXT:    [[TMP51:%.*]] = load double, double* [[DD]], align 8
+// CHECK-NEXT:    [[TMP52:%.*]] = bitcast double* [[DX]] to i64*
+// CHECK-NEXT:    [[TMP53:%.*]] = bitcast double [[TMP50]] to i64
+// CHECK-NEXT:    [[TMP54:%.*]] = bitcast double [[TMP51]] to i64
+// CHECK-NEXT:    [[TMP55:%.*]] = cmpxchg i64* [[TMP52]], i64 [[TMP53]], i64 [[TMP54]] acq_rel acquire, align 8
+// CHECK-NEXT:    [[TMP56:%.*]] = extractvalue { i64, i1 } [[TMP55]], 0
+// CHECK-NEXT:    [[TMP57:%.*]] = bitcast i64 [[TMP56]] to double
+// CHECK-NEXT:    [[TMP58:%.*]] = extractvalue { i64, i1 } [[TMP55]], 1
+// CHECK-NEXT:    [[TMP59:%.*]] = select i1 [[TMP58]], double [[TMP50]], double [[TMP57]]
+// CHECK-NEXT:    store double [[TMP59]], double* [[DV]], align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP60:%.*]] = load double, double* [[DE]], align 8
+// CHECK-NEXT:    [[TMP61:%.*]] = atomicrmw fmin double* [[DX]], double [[TMP60]] acquire, align 8
+// CHECK-NEXT:    store double [[TMP61]], double* [[DV]], align 8
+// CHECK-NEXT:    [[TMP62:%.*]] = load double, double* [[DE]], align 8
+// CHECK-NEXT:    [[TMP63:%.*]] = atomicrmw fmax double* [[DX]], double [[TMP62]] acquire, align 8
+// CHECK-NEXT:    store double [[TMP63]], double* [[DV]], align 8
+// CHECK-NEXT:    [[TMP64:%.*]] = load double, double* [[DE]], align 8
+// CHECK-NEXT:    [[TMP65:%.*]] = load double, double* [[DD]], align 8
+// CHECK-NEXT:    [[TMP66:%.*]] = bitcast double* [[DX]] to i64*
+// CHECK-NEXT:    [[TMP67:%.*]] = bitcast double [[TMP64]] to i64
+// CHECK-NEXT:    [[TMP68:%.*]] = bitcast double [[TMP65]] to i64
+// CHECK-NEXT:    [[TMP69:%.*]] = cmpxchg i64* [[TMP66]], i64 [[TMP67]], i64 [[TMP68]] acquire acquire, align 8
+// CHECK-NEXT:    [[TMP70:%.*]] = extractvalue { i64, i1 } [[TMP69]], 0
+// CHECK-NEXT:    [[TMP71:%.*]] = bitcast i64 [[TMP70]] to double
+// CHECK-NEXT:    store double [[TMP71]], double* [[DV]], align 8
+// CHECK-NEXT:    [[TMP72:%.*]] = load double, double* [[DE]], align 8
+// CHECK-NEXT:    [[TMP73:%.*]] = atomicrmw fmin double* [[DX]], double [[TMP72]] acquire, align 8
+// CHECK-NEXT:    [[TMP74:%.*]] = fcmp olt double [[TMP73]], [[TMP72]]
+// CHECK-NEXT:    [[TMP75:%.*]] = select i1 [[TMP74]], double [[TMP72]], double [[TMP73]]
+// CHECK-NEXT:    store double [[TMP75]], double* [[DV]], align 8
+// CHECK-NEXT:    [[TMP76:%.*]] = load double, double* [[DE]], align 8
+// CHECK-NEXT:    [[TMP77:%.*]] = atomicrmw fmax double* [[DX]], double [[TMP76]] acquire, align 8
+// CHECK-NEXT:    [[TMP78:%.*]] = fcmp ogt double [[TMP77]], [[TMP76]]
+// CHECK-NEXT:    [[TMP79:%.*]] = select i1 [[TMP78]], double [[TMP76]], double [[TMP77]]
+// CHECK-NEXT:    store double [[TMP79]], double* [[DV]], align 8
+// CHECK-NEXT:    [[TMP80:%.*]] = load double, double* [[DE]], align 8
+// CHECK-NEXT:    [[TMP81:%.*]] = load double, double* [[DD]], align 8
+// CHECK-NEXT:    [[TMP82:%.*]] = bitcast double* [[DX]] to i64*
+// CHECK-NEXT:    [[TMP83:%.*]] = bitcast double [[TMP80]] to i64
+// CHECK-NEXT:    [[TMP84:%.*]] = bitcast double [[TMP81]] to i64
+// CHECK-NEXT:    [[TMP85:%.*]] = cmpxchg i64* [[TMP82]], i64 [[TMP83]], i64 [[TMP84]] acquire acquire, align 8
+// CHECK-NEXT:    [[TMP86:%.*]] = extractvalue { i64, i1 } [[TMP85]], 0
+// CHECK-NEXT:    [[TMP87:%.*]] = bitcast i64 [[TMP86]] to double
+// CHECK-NEXT:    [[TMP88:%.*]] = extractvalue { i64, i1 } [[TMP85]], 1
+// CHECK-NEXT:    [[TMP89:%.*]] = select i1 [[TMP88]], double [[TMP80]], double [[TMP87]]
+// CHECK-NEXT:    store double [[TMP89]], double* [[DV]], align 8
+// CHECK-NEXT:    [[TMP90:%.*]] = load double, double* [[DE]], align 8
+// CHECK-NEXT:    [[TMP91:%.*]] = atomicrmw fmin double* [[DX]], double [[TMP90]] monotonic, align 8
+// CHECK-NEXT:    store double [[TMP91]], double* [[DV]], align 8
+// CHECK-NEXT:    [[TMP92:%.*]] = load double, double* [[DE]], align 8
+// CHECK-NEXT:    [[TMP93:%.*]] = atomicrmw fmax double* [[DX]], double [[TMP92]] monotonic, align 8
+// CHECK-NEXT:    store double [[TMP93]], double* [[DV]], align 8
+// CHECK-NEXT:    [[TMP94:%.*]] = load double, double* [[DE]], align 8
+// CHECK-NEXT:    [[TMP95:%.*]] = load double, double* [[DD]], align 8
+// CHECK-NEXT:    [[TMP96:%.*]] = bitcast double* [[DX]] to i64*
+// CHECK-NEXT:    [[TMP97:%.*]] = bitcast double [[TMP94]] to i64
+// CHECK-NEXT:    [[TMP98:%.*]] = bitcast double [[TMP95]] to i64
+// CHECK-NEXT:    [[TMP99:%.*]] = cmpxchg i64* [[TMP96]], i64 [[TMP97]], i64 [[TMP98]] monotonic monotonic, align 8
+// CHECK-NEXT:    [[TMP100:%.*]] = extractvalue { i64, i1 } [[TMP99]], 0
+// CHECK-NEXT:    [[TMP101:%.*]] = bitcast i64 [[TMP100]] to double
+// CHECK-NEXT:    store double [[TMP101]], double* [[DV]], align 8
+// CHECK-NEXT:    [[TMP102:%.*]] = load double, double* [[DE]], align 8
+// CHECK-NEXT:    [[TMP103:%.*]] = atomicrmw fmin double* [[DX]], double [[TMP102]] monotonic, align 8
+// CHECK-NEXT:    [[TMP104:%.*]] = fcmp olt double [[TMP103]], [[TMP102]]
+// CHECK-NEXT:    [[TMP105:%.*]] = select i1 [[TMP104]], double [[TMP102]], double [[TMP103]]
+// CHECK-NEXT:    store double [[TMP105]], double* [[DV]], align 8
+// CHECK-NEXT:    [[TMP106:%.*]] = load double, double* [[DE]], align 8
+// CHECK-NEXT:    [[TMP107:%.*]] = atomicrmw fmax double* [[DX]], double [[TMP106]] monotonic, align 8
+// CHECK-NEXT:    [[TMP108:%.*]] = fcmp ogt double [[TMP107]], [[TMP106]]
+// CHECK-NEXT:    [[TMP109:%.*]] = select i1 [[TMP108]], double [[TMP106]], double [[TMP107]]
+// CHECK-NEXT:    store double [[TMP109]], double* [[DV]], align 8
+// CHECK-NEXT:    [[TMP110:%.*]] = load double, double* [[DE]], align 8
+// CHECK-NEXT:    [[TMP111:%.*]] = load double, double* [[DD]], align 8
+// CHECK-NEXT:    [[TMP112:%.*]] = bitcast double* [[DX]] to i64*
+// CHECK-NEXT:    [[TMP113:%.*]] = bitcast double [[TMP110]] to i64
+// CHECK-NEXT:    [[TMP114:%.*]] = bitcast double [[TMP111]] to i64
+// CHECK-NEXT:    [[TMP115:%.*]] = cmpxchg i64* [[TMP112]], i64 [[TMP113]], i64 [[TMP114]] monotonic monotonic, align 8
+// CHECK-NEXT:    [[TMP116:%.*]] = extractvalue { i64, i1 } [[TMP115]], 0
+// CHECK-NEXT:    [[TMP117:%.*]] = bitcast i64 [[TMP116]] to double
+// CHECK-NEXT:    [[TMP118:%.*]] = extractvalue { i64, i1 } [[TMP115]], 1
+// CHECK-NEXT:    [[TMP119:%.*]] = select i1 [[TMP118]], double [[TMP110]], double [[TMP117]]
+// CHECK-NEXT:    store double [[TMP119]], double* [[DV]], align 8
+// CHECK-NEXT:    [[TMP120:%.*]] = load double, double* [[DE]], align 8
+// CHECK-NEXT:    [[TMP121:%.*]] = atomicrmw fmin double* [[DX]], double [[TMP120]] release, align 8
+// CHECK-NEXT:    store double [[TMP121]], double* [[DV]], align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP122:%.*]] = load double, double* [[DE]], align 8
+// CHECK-NEXT:    [[TMP123:%.*]] = atomicrmw fmax double* [[DX]], double [[TMP122]] release, align 8
+// CHECK-NEXT:    store double [[TMP123]], double* [[DV]], align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP124:%.*]] = load double, double* [[DE]], align 8
+// CHECK-NEXT:    [[TMP125:%.*]] = load double, double* [[DD]], align 8
+// CHECK-NEXT:    [[TMP126:%.*]] = bitcast double* [[DX]] to i64*
+// CHECK-NEXT:    [[TMP127:%.*]] = bitcast double [[TMP124]] to i64
+// CHECK-NEXT:    [[TMP128:%.*]] = bitcast double [[TMP125]] to i64
+// CHECK-NEXT:    [[TMP129:%.*]] = cmpxchg i64* [[TMP126]], i64 [[TMP127]], i64 [[TMP128]] release monotonic, align 8
+// CHECK-NEXT:    [[TMP130:%.*]] = extractvalue { i64, i1 } [[TMP129]], 0
+// CHECK-NEXT:    [[TMP131:%.*]] = bitcast i64 [[TMP130]] to double
+// CHECK-NEXT:    store double [[TMP131]], double* [[DV]], align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP132:%.*]] = load double, double* [[DE]], align 8
+// CHECK-NEXT:    [[TMP133:%.*]] = atomicrmw fmin double* [[DX]], double [[TMP132]] release, align 8
+// CHECK-NEXT:    [[TMP134:%.*]] = fcmp olt double [[TMP133]], [[TMP132]]
+// CHECK-NEXT:    [[TMP135:%.*]] = select i1 [[TMP134]], double [[TMP132]], double [[TMP133]]
+// CHECK-NEXT:    store double [[TMP135]], double* [[DV]], align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP136:%.*]] = load double, double* [[DE]], align 8
+// CHECK-NEXT:    [[TMP137:%.*]] = atomicrmw fmax double* [[DX]], double [[TMP136]] release, align 8
+// CHECK-NEXT:    [[TMP138:%.*]] = fcmp ogt double [[TMP137]], [[TMP136]]
+// CHECK-NEXT:    [[TMP139:%.*]] = select i1 [[TMP138]], double [[TMP136]], double [[TMP137]]
+// CHECK-NEXT:    store double [[TMP139]], double* [[DV]], align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP140:%.*]] = load double, double* [[DE]], align 8
+// CHECK-NEXT:    [[TMP141:%.*]] = load double, double* [[DD]], align 8
+// CHECK-NEXT:    [[TMP142:%.*]] = bitcast double* [[DX]] to i64*
+// CHECK-NEXT:    [[TMP143:%.*]] = bitcast double [[TMP140]] to i64
+// CHECK-NEXT:    [[TMP144:%.*]] = bitcast double [[TMP141]] to i64
+// CHECK-NEXT:    [[TMP145:%.*]] = cmpxchg i64* [[TMP142]], i64 [[TMP143]], i64 [[TMP144]] release monotonic, align 8
+// CHECK-NEXT:    [[TMP146:%.*]] = extractvalue { i64, i1 } [[TMP145]], 0
+// CHECK-NEXT:    [[TMP147:%.*]] = bitcast i64 [[TMP146]] to double
+// CHECK-NEXT:    [[TMP148:%.*]] = extractvalue { i64, i1 } [[TMP145]], 1
+// CHECK-NEXT:    [[TMP149:%.*]] = select i1 [[TMP148]], double [[TMP140]], double [[TMP147]]
+// CHECK-NEXT:    store double [[TMP149]], double* [[DV]], align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP150:%.*]] = load double, double* [[DE]], align 8
+// CHECK-NEXT:    [[TMP151:%.*]] = atomicrmw fmin double* [[DX]], double [[TMP150]] seq_cst, align 8
+// CHECK-NEXT:    store double [[TMP151]], double* [[DV]], align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP152:%.*]] = load double, double* [[DE]], align 8
+// CHECK-NEXT:    [[TMP153:%.*]] = atomicrmw fmax double* [[DX]], double [[TMP152]] seq_cst, align 8
+// CHECK-NEXT:    store double [[TMP153]], double* [[DV]], align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP154:%.*]] = load double, double* [[DE]], align 8
+// CHECK-NEXT:    [[TMP155:%.*]] = load double, double* [[DD]], align 8
+// CHECK-NEXT:    [[TMP156:%.*]] = bitcast double* [[DX]] to i64*
+// CHECK-NEXT:    [[TMP157:%.*]] = bitcast double [[TMP154]] to i64
+// CHECK-NEXT:    [[TMP158:%.*]] = bitcast double [[TMP155]] to i64
+// CHECK-NEXT:    [[TMP159:%.*]] = cmpxchg i64* [[TMP156]], i64 [[TMP157]], i64 [[TMP158]] seq_cst seq_cst, align 8
+// CHECK-NEXT:    [[TMP160:%.*]] = extractvalue { i64, i1 } [[TMP159]], 0
+// CHECK-NEXT:    [[TMP161:%.*]] = bitcast i64 [[TMP160]] to double
+// CHECK-NEXT:    store double [[TMP161]], double* [[DV]], align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP162:%.*]] = load double, double* [[DE]], align 8
+// CHECK-NEXT:    [[TMP163:%.*]] = atomicrmw fmin double* [[DX]], double [[TMP162]] seq_cst, align 8
+// CHECK-NEXT:    [[TMP164:%.*]] = fcmp olt double [[TMP163]], [[TMP162]]
+// CHECK-NEXT:    [[TMP165:%.*]] = select i1 [[TMP164]], double [[TMP162]], double [[TMP163]]
+// CHECK-NEXT:    store double [[TMP165]], double* [[DV]], align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP166:%.*]] = load double, double* [[DE]], align 8
+// CHECK-NEXT:    [[TMP167:%.*]] = atomicrmw fmax double* [[DX]], double [[TMP166]] seq_cst, align 8
+// CHECK-NEXT:    [[TMP168:%.*]] = fcmp ogt double [[TMP167]], [[TMP166]]
+// CHECK-NEXT:    [[TMP169:%.*]] = select i1 [[TMP168]], double [[TMP166]], double [[TMP167]]
+// CHECK-NEXT:    store double [[TMP169]], double* [[DV]], align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP170:%.*]] = load double, double* [[DE]], align 8
+// CHECK-NEXT:    [[TMP171:%.*]] = load double, double* [[DD]], align 8
+// CHECK-NEXT:    [[TMP172:%.*]] = bitcast double* [[DX]] to i64*
+// CHECK-NEXT:    [[TMP173:%.*]] = bitcast double [[TMP170]] to i64
+// CHECK-NEXT:    [[TMP174:%.*]] = bitcast double [[TMP171]] to i64
+// CHECK-NEXT:    [[TMP175:%.*]] = cmpxchg i64* [[TMP172]], i64 [[TMP173]], i64 [[TMP174]] seq_cst seq_cst, align 8
+// CHECK-NEXT:    [[TMP176:%.*]] = extractvalue { i64, i1 } [[TMP175]], 0
+// CHECK-NEXT:    [[TMP177:%.*]] = bitcast i64 [[TMP176]] to double
+// CHECK-NEXT:    [[TMP178:%.*]] = extractvalue { i64, i1 } [[TMP175]], 1
+// CHECK-NEXT:    [[TMP179:%.*]] = select i1 [[TMP178]], double [[TMP170]], double [[TMP177]]
+// CHECK-NEXT:    store double [[TMP179]], double* [[DV]], align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP180:%.*]] = load double, double* [[DV]], align 8
+// CHECK-NEXT:    ret double [[TMP180]]

clang/test/OpenMP/atomic_messages.c

 // omp51-note@+2 {{expect an assignment statement 'v = x'}}
 #pragma omp atomic compare capture
   { v = d; if (x == e) { x = d; } }
 // omp51-error@+3 {{the statement for 'atomic compare capture' must be a compound statement of form '{v = x; cond-up-stmt}', ''{cond-up-stmt v = x;}', '{if(x == e) {x = d;} else {v = x;}}', '{r = x == e; if(r) {x = d;}}', or '{r = x == e; if(r) {x = d;} else {v = x;}}', where 'cond-update-stmt' can have one of the following forms: 'if(expr ordop x) {x = expr;}', 'if(x ordop expr) {x = expr;}', 'if(x == e) {x = d;}', or 'if(e == x) {x = d;}' where 'x' is an lvalue expression with scalar type, 'expr', 'e', and 'd' are expressions with scalar type, and 'ordop' is one of '<' or '>'.}}
 // omp51-note@+2 {{expect an assignment statement 'v = x'}}
 #pragma omp atomic compare capture
   { if (x == e) { x = d; } v = d; }
 // omp51-error@+3 {{the statement for 'atomic compare capture' must be a compound statement of form '{v = x; cond-up-stmt}', ''{cond-up-stmt v = x;}', '{if(x == e) {x = d;} else {v = x;}}', '{r = x == e; if(r) {x = d;}}', or '{r = x == e; if(r) {x = d;} else {v = x;}}', where 'cond-update-stmt' can have one of the following forms: 'if(expr ordop x) {x = expr;}', 'if(x ordop expr) {x = expr;}', 'if(x == e) {x = d;}', or 'if(e == x) {x = d;}' where 'x' is an lvalue expression with scalar type, 'expr', 'e', and 'd' are expressions with scalar type, and 'ordop' is one of '<' or '>'.}}
-// omp51-note@+2 {{expect a 'if' statement}}
+// omp51-note@+2 {{expected assignment statement}}
 #pragma omp atomic compare capture
   { v = x; bbar(); }
 
 // omp51-error@+3 {{the statement for 'atomic compare capture' must be a compound statement of form '{v = x; cond-up-stmt}', ''{cond-up-stmt v = x;}', '{if(x == e) {x = d;} else {v = x;}}', '{r = x == e; if(r) {x = d;}}', or '{r = x == e; if(r) {x = d;} else {v = x;}}', where 'cond-update-stmt' can have one of the following forms: 'if(expr ordop x) {x = expr;}', 'if(x ordop expr) {x = expr;}', 'if(x == e) {x = d;}', or 'if(e == x) {x = d;}' where 'x' is an lvalue expression with scalar type, 'expr', 'e', and 'd' are expressions with scalar type, and 'ordop' is one of '<' or '>'.}}
 // omp51-note@+2 {{expect integer value}}
 #pragma omp atomic compare capture
   { dr = x == e; if (dr) { x = d; } }
 }
 #endif