Add f16 nearbyint support.

[Leonc]

Summary

Enable lowering of FNEARBYINT for f16 and extend existing tests.

[arsenm]

llvm/test/CodeGen/AMDGPU/fnearbyint.ll

6–7

This test is missing checks somehow

[Leonc]

llvm/test/CodeGen/AMDGPU/fnearbyint.ll

6–7

Do we want checks for all of the functions? The comment on lines 5-6 suggests the checks were left out intentionally.

[Leonc]

Comments on SWDEV-353076 suggested there was a related issue with roundeven but I wasn't able to find any.

[arsenm]

llvm/test/CodeGen/AMDGPU/fnearbyint.ll

6–7

The comment is nonsense and it's bad practice to have no checks

[Leonc]

llvm/test/CodeGen/AMDGPU/fnearbyint.ll

6–7

I'm happy to add the checks. If I only add them for nearbyint.f16 people might argue that the new code is inconsistent. If I add them for every function the changes would be out of scope for the task. What's the preferred option here?

[arsenm]

llvm/test/CodeGen/AMDGPU/fnearbyint.ll

6–7

Fix the test by adding checks in a pre commit before this patch

[Leonc]

• Add FileCheck directives.

[arsenm]

LGTM

llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

setOperationAction({ISD::FCEIL, ISD::FEXP2, ISD::FPOW, ISD::FLOG2, ISD::FABS,
                       ISD::FFLOOR, ISD::FRINT, ISD::FTRUNC, ISD::FMINNUM,
                       ISD::FMAXNUM},
                      MVT::f32, Legal);
 
   setOperationAction(ISD::FROUND, {MVT::f32, MVT::f64}, Custom);
 
   setOperationAction({ISD::FLOG, ISD::FLOG10, ISD::FEXP}, MVT::f32, Custom);
 
-  setOperationAction(ISD::FNEARBYINT, {MVT::f32, MVT::f64}, Custom);
+  setOperationAction(ISD::FNEARBYINT, {MVT::f16, MVT::f32, MVT::f64}, Custom);
 
   setOperationAction(ISD::FREM, {MVT::f16, MVT::f32, MVT::f64}, Custom);
 
   // Expand to fneg + fadd.
   setOperationAction(ISD::FSUB, MVT::f64, Expand);
 
   setOperationAction(ISD::CONCAT_VECTORS,
                      {MVT::v3i32, MVT::v3f32, MVT::v4i32, MVT::v4f32,

llvm/test/CodeGen/AMDGPU/fnearbyint.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefixes=SI %s
 ; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefixes=CI %s
 ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=VI %s
 
 
+declare half @llvm.nearbyint.f16(half) #0
 declare float @llvm.nearbyint.f32(float) #0
 declare <2 x float> @llvm.nearbyint.v2f32(<2 x float>) #0
 declare <4 x float> @llvm.nearbyint.v4f32(<4 x float>) #0
 declare double @llvm.nearbyint.f64(double) #0
 declare <2 x double> @llvm.nearbyint.v2f64(<2 x double>) #0
 declare <4 x double> @llvm.nearbyint.v4f64(<4 x double>) #0
 
 
+define amdgpu_kernel void @fnearbyint_f16(half addrspace(1)* %out, half %in) #1 {
+; SI-LABEL: fnearbyint_f16:
+; SI:       ; %bb.0:
+; SI-NEXT:    s_load_dword s4, s[0:1], 0xb
+; SI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
+; SI-NEXT:    s_mov_b32 s3, 0xf000
+; SI-NEXT:    s_mov_b32 s2, -1
+; SI-NEXT:    s_waitcnt lgkmcnt(0)
+; SI-NEXT:    v_cvt_f32_f16_e32 v0, s4
+; SI-NEXT:    v_rndne_f32_e32 v0, v0
+; SI-NEXT:    v_cvt_f16_f32_e32 v0, v0
+; SI-NEXT:    buffer_store_short v0, off, s[0:3], 0
+; SI-NEXT:    s_endpgm
+;
+; CI-LABEL: fnearbyint_f16:
+; CI:       ; %bb.0:
+; CI-NEXT:    s_load_dword s2, s[0:1], 0xb
+; CI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
+; CI-NEXT:    s_mov_b32 s3, 0xf000
+; CI-NEXT:    s_waitcnt lgkmcnt(0)
+; CI-NEXT:    v_cvt_f32_f16_e32 v0, s2
+; CI-NEXT:    s_mov_b32 s2, -1
+; CI-NEXT:    v_rndne_f32_e32 v0, v0
+; CI-NEXT:    v_cvt_f16_f32_e32 v0, v0
+; CI-NEXT:    buffer_store_short v0, off, s[0:3], 0
+; CI-NEXT:    s_endpgm
+;
+; VI-LABEL: fnearbyint_f16:
+; VI:       ; %bb.0:
+; VI-NEXT:    s_load_dword s4, s[0:1], 0x2c
+; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; VI-NEXT:    s_mov_b32 s3, 0xf000
+; VI-NEXT:    s_mov_b32 s2, -1
+; VI-NEXT:    s_waitcnt lgkmcnt(0)
+; VI-NEXT:    v_rndne_f16_e32 v0, s4
+; VI-NEXT:    buffer_store_short v0, off, s[0:3], 0
+; VI-NEXT:    s_endpgm
+  %1 = call half @llvm.nearbyint.f16(half %in)
+  store half %1, half addrspace(1)* %out
+  ret void
+}
+
 define amdgpu_kernel void @fnearbyint_f32(float addrspace(1)* %out, float %in) #1 {
 ; SI-LABEL: fnearbyint_f32:
 ; SI:       ; %bb.0: ; %entry
 ; SI-NEXT:    s_load_dword s4, s[0:1], 0xb
 ; SI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
 ; SI-NEXT:    s_mov_b32 s3, 0xf000
 ; SI-NEXT:    s_mov_b32 s2, -1
 ; SI-NEXT:    s_waitcnt lgkmcnt(0)