[AMDGPU][GISel] Add Identity BUILD_VECTOR Combines

[Pierre-vh]

Summary

Folds-away BUILD_VECTOR-related noops in the post-legalizer combiner.

Depends on D134433

[arsenm]

llvm/lib/Target/AMDGPU/AMDGPUCombine.td

48–52

Can move this to the generic combiner

llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp

333

Shouldn't need to bother with getDefIgnoringCopies, copy of copy is folded out during combining. We should have an m_Undef or m_ImplicitDef too if there isn't one already

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.1d.d16.ll

947–949

Should remove this and remove the unused prefixes

llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-buildvector-identities.mir

2

Don't need -global-isel with -run-pass

llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-trunc-bitcast-buildvector.mir

2

Don't need -global-isel with -run-pass

[Pierre-vh]

Comments

[arsenm]

llvm/lib/Target/AMDGPU/AMDGPUCombine.td

48

Left behind AMDGPU copy

llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp

308–309

Left behind the AMDGPU copy

[arsenm]

LGTM except for the leftover copy

[Pierre-vh]

Comment

llvm/lib/Target/AMDGPU/AMDGPUCombine.td

48

That's another combine for (G_TRUNC (G_BITCAST (G_BUILD_VECTOR x, y), unless that one can also go in the generic combiner?

[arsenm]

llvm/lib/Target/AMDGPU/AMDGPUCombine.td

48

Yes, all of this can. It's not doing anything that target specific and uses no custom opcodes

[Pierre-vh]

Move all to Helper

llvm/include/llvm/CodeGen/GlobalISel/MIPatternMatch.h

 
 template <typename LHS, typename RHS>
 inline BinaryOp_match<LHS, RHS, TargetOpcode::G_ADD, true>
 m_GAdd(const LHS &L, const RHS &R) {
   return BinaryOp_match<LHS, RHS, TargetOpcode::G_ADD, true>(L, R);
 }
 
 template <typename LHS, typename RHS>
+inline BinaryOp_match<LHS, RHS, TargetOpcode::G_BUILD_VECTOR, false>
+m_GBuildVector(const LHS &L, const RHS &R) {
+  return BinaryOp_match<LHS, RHS, TargetOpcode::G_BUILD_VECTOR, false>(L, R);
+}
+
+template <typename LHS, typename RHS>
+inline BinaryOp_match<LHS, RHS, TargetOpcode::G_BUILD_VECTOR_TRUNC, false>
+m_GBuildVectorTrunc(const LHS &L, const RHS &R) {
+  return BinaryOp_match<LHS, RHS, TargetOpcode::G_BUILD_VECTOR_TRUNC, false>(L,
+                                                                             R);
+}
+
+template <typename LHS, typename RHS>
 inline BinaryOp_match<LHS, RHS, TargetOpcode::G_PTR_ADD, false>
 m_GPtrAdd(const LHS &L, const RHS &R) {
   return BinaryOp_match<LHS, RHS, TargetOpcode::G_PTR_ADD, false>(L, R);
 }
 
 template <typename LHS, typename RHS>
 inline BinaryOp_match<LHS, RHS, TargetOpcode::G_SUB> m_GSub(const LHS &L,
                                                             const RHS &R) {

llvm/lib/Target/AMDGPU/AMDGPUCombine.td

def cvt_f32_ubyteN : GICombineRule<
   (defs root:$cvt_f32_ubyteN, cvt_f32_ubyteN_matchdata:$matchinfo),
   (match (wip_match_opcode G_AMDGPU_CVT_F32_UBYTE0,
                            G_AMDGPU_CVT_F32_UBYTE1,
                            G_AMDGPU_CVT_F32_UBYTE2,
                            G_AMDGPU_CVT_F32_UBYTE3):$cvt_f32_ubyteN,
          [{ return PostLegalizerHelper.matchCvtF32UByteN(*${cvt_f32_ubyteN}, ${matchinfo}); }]),
   (apply [{ PostLegalizerHelper.applyCvtF32UByteN(*${cvt_f32_ubyteN}, ${matchinfo}); }])>;
 
+def buildvector_identity_fold : GICombineRule<
+  (defs root:$build_vector, register_matchinfo:$matchinfo),
+  (match (wip_match_opcode G_BUILD_VECTOR_TRUNC, G_BUILD_VECTOR):$build_vector,
+         [{ return PostLegalizerHelper.matchBuildVectorIdentityFold(*${build_vector}, ${matchinfo}); }]),
+  (apply [{ Helper.replaceSingleDefInstWithReg(*${build_vector}, ${matchinfo}); }])>;
+
+
+def trunc_buildvector_fold : GICombineRule<
+  (defs root:$op, register_matchinfo:$matchinfo),
+  (match (wip_match_opcode G_TRUNC):$op,
+      [{ return PostLegalizerHelper.matchTruncBuildVectorFold(*${op}, ${matchinfo}); }]),
+  (apply [{ Helper.replaceSingleDefInstWithReg(*${op}, ${matchinfo}); }])>;
+
 def clamp_i64_to_i16_matchdata : GIDefMatchData<"AMDGPUPreLegalizerCombinerHelper::ClampI64ToI16MatchInfo">;
 
 def clamp_i64_to_i16 : GICombineRule<
   (defs root:$clamp_i64_to_i16, clamp_i64_to_i16_matchdata:$matchinfo),
   (match (wip_match_opcode G_TRUNC):$clamp_i64_to_i16,
       [{ return PreLegalizerHelper.matchClampI64ToI16(*${clamp_i64_to_i16}, MRI, *MF, ${matchinfo}); }]),
   (apply [{ PreLegalizerHelper.applyClampI64ToI16(*${clamp_i64_to_i16}, ${matchinfo}); }])>;
 
def AMDGPUPreLegalizerCombinerHelper: GICombinerHelper<
   let StateClass = "AMDGPUPreLegalizerCombinerHelperState";
   let AdditionalArguments = [];
 }
 
 def AMDGPUPostLegalizerCombinerHelper: GICombinerHelper<
   "AMDGPUGenPostLegalizerCombinerHelper",
   [all_combines, gfx6gfx7_combines,
    uchar_to_float, cvt_f32_ubyteN, remove_fcanonicalize, foldable_fneg,
-   rcp_sqrt_to_rsq]> {
+   rcp_sqrt_to_rsq, buildvector_identity_fold, trunc_buildvector_fold]> {
   let DisableRuleOption = "amdgpupostlegalizercombiner-disable-rule";
   let StateClass = "AMDGPUPostLegalizerCombinerHelperState";
   let AdditionalArguments = [];
 }
 
 def AMDGPURegBankCombinerHelper : GICombinerHelper<
   "AMDGPUGenRegBankCombinerHelper",
   [zext_trunc_fold, int_minmax_to_med3, ptr_add_immed_chain,
    fp_minmax_to_clamp, fp_minmax_to_med3, fmed3_intrinsic_to_clamp]> {
   let DisableRuleOption = "amdgpuregbankcombiner-disable-rule";
   let StateClass = "AMDGPURegBankCombinerHelperState";
   let AdditionalArguments = [];
 }

llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp

struct CvtF32UByteMatchInfo {
     unsigned ShiftOffset;
   };
 
   bool matchCvtF32UByteN(MachineInstr &MI, CvtF32UByteMatchInfo &MatchInfo);
   void applyCvtF32UByteN(MachineInstr &MI,
                          const CvtF32UByteMatchInfo &MatchInfo);
 
   bool matchRemoveFcanonicalize(MachineInstr &MI, Register &Reg);
+  bool matchBuildVectorIdentityFold(MachineInstr &MI, Register &MatchInfo);
+  bool matchTruncBuildVectorFold(MachineInstr &MI, Register &MatchInfo);
 };
 
 bool AMDGPUPostLegalizerCombinerHelper::matchFMinFMaxLegacy(
     MachineInstr &MI, FMinFMaxLegacyInfo &Info) {
   // FIXME: Combines should have subtarget predicates, and we shouldn't need
   // this here.
   if (!MF.getSubtarget<GCNSubtarget>().hasFminFmaxLegacy())
     return false;

 bool AMDGPUPostLegalizerCombinerHelper::matchRemoveFcanonicalize(
     MachineInstr &MI, Register &Reg) {
   const SITargetLowering *TLI = static_cast<const SITargetLowering *>(
       MF.getSubtarget().getTargetLowering());
   Reg = MI.getOperand(1).getReg();
   return TLI->isCanonicalized(Reg, MF);
 }
 
+bool AMDGPUPostLegalizerCombinerHelper::matchBuildVectorIdentityFold(
+    MachineInstr &MI, Register &MatchInfo) {
+  // This combine folds the following patterns:
+  //
+  //  G_BUILD_VECTOR_TRUNC (G_BITCAST(x), G_LSHR(G_BITCAST(x), k))
+  //  G_BUILD_VECTOR(G_TRUNC(G_BITCAST(x)), G_TRUNC(G_LSHR(G_BITCAST(x), k)))
+  //    into
+  //      x
+  //    if
+  //      k == sizeof(VecEltTy)/2
+  //      type(x) == type(dst)
+  //
+  //  G_BUILD_VECTOR(G_TRUNC(G_BITCAST(x)), undef)
+  //    into
+  //      x
+  //    if
+  //      type(x) == type(dst)
+
+  LLT DstVecTy = MRI.getType(MI.getOperand(0).getReg());
+  LLT DstEltTy = DstVecTy.getElementType();
+
+  Register Lo, Hi;
+
+  if (mi_match(MI, MRI,
+               m_GBuildVector(m_GTrunc(m_GBitcast(m_Reg(Lo))), m_Reg(Hi)))) {
+    if (getDefIgnoringCopies(Hi, MRI)->getOpcode() == AMDGPU::G_IMPLICIT_DEF) {
+      MatchInfo = Lo;
+      return MRI.getType(MatchInfo) == DstVecTy;
+    }
+  }
+
+  Optional<ValueAndVReg> ShiftAmount;
+  const auto LoPattern = m_GBitcast(m_Reg(Lo));
+  const auto HiPattern = m_GLShr(m_GBitcast(m_Reg(Hi)), m_GCst(ShiftAmount));
+  if (mi_match(
+          MI, MRI,
+          m_any_of(m_GBuildVectorTrunc(LoPattern, HiPattern),
+                   m_GBuildVector(m_GTrunc(LoPattern), m_GTrunc(HiPattern))))) {
+    if (Lo == Hi && ShiftAmount->Value == DstEltTy.getSizeInBits()) {
+      MatchInfo = Lo;
+      return MRI.getType(MatchInfo) == DstVecTy;
+    }
+  }
+
+  return false;
+}
+
+bool AMDGPUPostLegalizerCombinerHelper::matchTruncBuildVectorFold(
+    MachineInstr &MI, Register &MatchInfo) {
+  assert(MI.getOpcode() == AMDGPU::G_TRUNC);
+
+  // Replace (G_TRUNC (G_BITCAST (G_BUILD_VECTOR x, y)) with just x
+  // if type(x) == type(G_TRUNC)
+  if (!mi_match(MI.getOperand(1).getReg(), MRI,
+                m_GBitcast(m_GBuildVector(m_Reg(MatchInfo), m_Reg()))))
+    return false;
+
+  return MRI.getType(MatchInfo) == MRI.getType(MI.getOperand(0).getReg());
+}
+
 class AMDGPUPostLegalizerCombinerHelperState {
 protected:
   AMDGPUCombinerHelper &Helper;
   AMDGPUPostLegalizerCombinerHelper &PostLegalizerHelper;
 
 public:
   AMDGPUPostLegalizerCombinerHelperState(
       AMDGPUCombinerHelper &Helper,

llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-ext-mul.ll

.entry:
     %b = fpext half %a to float
     %c = fadd fast float %z, %b
     ret float %c
 }
 
 define amdgpu_vs <5 x float> @test_5xf16_5xf32_add_ext_mul(<5 x half> inreg %x, <5 x half> inreg %y, <5 x float> inreg %z) {
 ; GFX9-FAST-DENORM-LABEL: test_5xf16_5xf32_add_ext_mul:
 ; GFX9-FAST-DENORM:       ; %bb.0: ; %.entry
-; GFX9-FAST-DENORM-NEXT:    s_pack_lh_b32_b16 s3, s3, s3
-; GFX9-FAST-DENORM-NEXT:    s_pack_lh_b32_b16 s4, s4, s4
-; GFX9-FAST-DENORM-NEXT:    s_pack_lh_b32_b16 s0, s0, s0
-; GFX9-FAST-DENORM-NEXT:    s_pack_lh_b32_b16 s1, s1, s1
 ; GFX9-FAST-DENORM-NEXT:    v_mov_b32_e32 v0, s3
 ; GFX9-FAST-DENORM-NEXT:    v_mov_b32_e32 v1, s4
 ; GFX9-FAST-DENORM-NEXT:    v_mov_b32_e32 v2, s5
 ; GFX9-FAST-DENORM-NEXT:    v_pk_mul_f16 v0, s0, v0
 ; GFX9-FAST-DENORM-NEXT:    v_pk_mul_f16 v1, s1, v1
 ; GFX9-FAST-DENORM-NEXT:    v_pk_mul_f16 v2, s2, v2
 ; GFX9-FAST-DENORM-NEXT:    v_cvt_f32_f16_e32 v3, v0
 ; GFX9-FAST-DENORM-NEXT:    v_cvt_f32_f16_sdwa v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1

llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-mul.ll

.entry:
   %b = fadd <4 x half> %a, %z
   ret <4 x half> %b
 }
 
 define <3 x half> @test_3xhalf_add_mul_rhs(<3 x half> %x, <3 x half> %y, <3 x half> %z) {
 ; GFX9-LABEL: test_3xhalf_add_mul_rhs:
 ; GFX9:       ; %bb.0: ; %.entry
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:    v_lshrrev_b32_e32 v6, 16, v0
-; GFX9-NEXT:    v_lshrrev_b32_e32 v7, 16, v2
-; GFX9-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX9-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX9-NEXT:    v_lshl_or_b32 v0, v6, 16, v0
-; GFX9-NEXT:    v_lshl_or_b32 v2, v7, 16, v2
 ; GFX9-NEXT:    v_pk_mul_f16 v0, v0, v2
-; GFX9-NEXT:    v_lshrrev_b32_e32 v8, 16, v4
 ; GFX9-NEXT:    v_pk_mul_f16 v1, v1, v3
-; GFX9-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX9-NEXT:    v_and_b32_e32 v3, 0xffff, v4
-; GFX9-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX9-NEXT:    v_lshl_or_b32 v3, v8, 16, v3
-; GFX9-NEXT:    v_lshl_or_b32 v0, v2, 16, v0
-; GFX9-NEXT:    v_pk_add_f16 v0, v3, v0
-; GFX9-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX9-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX9-NEXT:    v_pk_add_f16 v0, v4, v0
 ; GFX9-NEXT:    v_pk_add_f16 v1, v5, v1
-; GFX9-NEXT:    v_lshl_or_b32 v0, v2, 16, v0
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-CONTRACT-LABEL: test_3xhalf_add_mul_rhs:
 ; GFX9-CONTRACT:       ; %bb.0: ; %.entry
 ; GFX9-CONTRACT-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-CONTRACT-NEXT:    v_lshrrev_b32_e32 v6, 16, v0
-; GFX9-CONTRACT-NEXT:    v_lshrrev_b32_e32 v7, 16, v2
-; GFX9-CONTRACT-NEXT:    v_lshrrev_b32_e32 v8, 16, v4
-; GFX9-CONTRACT-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX9-CONTRACT-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX9-CONTRACT-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GFX9-CONTRACT-NEXT:    v_lshl_or_b32 v0, v6, 16, v0
-; GFX9-CONTRACT-NEXT:    v_lshl_or_b32 v2, v7, 16, v2
-; GFX9-CONTRACT-NEXT:    v_lshl_or_b32 v4, v8, 16, v4
 ; GFX9-CONTRACT-NEXT:    v_pk_fma_f16 v0, v0, v2, v4
-; GFX9-CONTRACT-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX9-CONTRACT-NEXT:    v_and_b32_e32 v0, 0xffff, v0
 ; GFX9-CONTRACT-NEXT:    v_pk_fma_f16 v1, v1, v3, v5
-; GFX9-CONTRACT-NEXT:    v_lshl_or_b32 v0, v2, 16, v0
 ; GFX9-CONTRACT-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-DENORM-LABEL: test_3xhalf_add_mul_rhs:
 ; GFX9-DENORM:       ; %bb.0: ; %.entry
 ; GFX9-DENORM-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-DENORM-NEXT:    v_lshrrev_b32_e32 v6, 16, v0
-; GFX9-DENORM-NEXT:    v_lshrrev_b32_e32 v7, 16, v2
-; GFX9-DENORM-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX9-DENORM-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX9-DENORM-NEXT:    v_lshl_or_b32 v0, v6, 16, v0
-; GFX9-DENORM-NEXT:    v_lshl_or_b32 v2, v7, 16, v2
 ; GFX9-DENORM-NEXT:    v_pk_mul_f16 v0, v0, v2
-; GFX9-DENORM-NEXT:    v_lshrrev_b32_e32 v8, 16, v4
 ; GFX9-DENORM-NEXT:    v_pk_mul_f16 v1, v1, v3
-; GFX9-DENORM-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX9-DENORM-NEXT:    v_and_b32_e32 v3, 0xffff, v4
-; GFX9-DENORM-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX9-DENORM-NEXT:    v_lshl_or_b32 v3, v8, 16, v3
-; GFX9-DENORM-NEXT:    v_lshl_or_b32 v0, v2, 16, v0
-; GFX9-DENORM-NEXT:    v_pk_add_f16 v0, v3, v0
-; GFX9-DENORM-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX9-DENORM-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX9-DENORM-NEXT:    v_pk_add_f16 v0, v4, v0
 ; GFX9-DENORM-NEXT:    v_pk_add_f16 v1, v5, v1
-; GFX9-DENORM-NEXT:    v_lshl_or_b32 v0, v2, 16, v0
 ; GFX9-DENORM-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-UNSAFE-LABEL: test_3xhalf_add_mul_rhs:
 ; GFX9-UNSAFE:       ; %bb.0: ; %.entry
 ; GFX9-UNSAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-UNSAFE-NEXT:    v_lshrrev_b32_e32 v6, 16, v0
-; GFX9-UNSAFE-NEXT:    v_lshrrev_b32_e32 v7, 16, v2
-; GFX9-UNSAFE-NEXT:    v_lshrrev_b32_e32 v8, 16, v4
-; GFX9-UNSAFE-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX9-UNSAFE-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX9-UNSAFE-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GFX9-UNSAFE-NEXT:    v_lshl_or_b32 v0, v6, 16, v0
-; GFX9-UNSAFE-NEXT:    v_lshl_or_b32 v2, v7, 16, v2
-; GFX9-UNSAFE-NEXT:    v_lshl_or_b32 v4, v8, 16, v4
 ; GFX9-UNSAFE-NEXT:    v_pk_fma_f16 v0, v0, v2, v4
-; GFX9-UNSAFE-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX9-UNSAFE-NEXT:    v_and_b32_e32 v0, 0xffff, v0
 ; GFX9-UNSAFE-NEXT:    v_pk_fma_f16 v1, v1, v3, v5
-; GFX9-UNSAFE-NEXT:    v_lshl_or_b32 v0, v2, 16, v0
 ; GFX9-UNSAFE-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: test_3xhalf_add_mul_rhs:
 ; GFX10:       ; %bb.0: ; %.entry
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_lshrrev_b32_e32 v6, 16, v0
-; GFX10-NEXT:    v_lshrrev_b32_e32 v7, 16, v2
-; GFX10-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX10-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX10-NEXT:    v_pk_mul_f16 v0, v0, v2
 ; GFX10-NEXT:    v_pk_mul_f16 v1, v1, v3
-; GFX10-NEXT:    v_lshl_or_b32 v0, v6, 16, v0
-; GFX10-NEXT:    v_lshl_or_b32 v2, v7, 16, v2
+; GFX10-NEXT:    v_pk_add_f16 v0, v4, v0
 ; GFX10-NEXT:    v_pk_add_f16 v1, v5, v1
-; GFX10-NEXT:    v_pk_mul_f16 v0, v0, v2
-; GFX10-NEXT:    v_lshrrev_b32_e32 v2, 16, v4
-; GFX10-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GFX10-NEXT:    v_lshrrev_b32_e32 v6, 16, v0
-; GFX10-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX10-NEXT:    v_lshl_or_b32 v2, v2, 16, v4
-; GFX10-NEXT:    v_lshl_or_b32 v0, v6, 16, v0
-; GFX10-NEXT:    v_pk_add_f16 v0, v2, v0
-; GFX10-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX10-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX10-NEXT:    v_lshl_or_b32 v0, v2, 16, v0
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-CONTRACT-LABEL: test_3xhalf_add_mul_rhs:
 ; GFX10-CONTRACT:       ; %bb.0: ; %.entry
 ; GFX10-CONTRACT-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-CONTRACT-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-CONTRACT-NEXT:    v_lshrrev_b32_e32 v6, 16, v0
-; GFX10-CONTRACT-NEXT:    v_lshrrev_b32_e32 v7, 16, v2
-; GFX10-CONTRACT-NEXT:    v_lshrrev_b32_e32 v8, 16, v4
-; GFX10-CONTRACT-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX10-CONTRACT-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX10-CONTRACT-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GFX10-CONTRACT-NEXT:    v_pk_fma_f16 v1, v1, v3, v5
-; GFX10-CONTRACT-NEXT:    v_lshl_or_b32 v0, v6, 16, v0
-; GFX10-CONTRACT-NEXT:    v_lshl_or_b32 v2, v7, 16, v2
-; GFX10-CONTRACT-NEXT:    v_lshl_or_b32 v4, v8, 16, v4
 ; GFX10-CONTRACT-NEXT:    v_pk_fma_f16 v0, v0, v2, v4
-; GFX10-CONTRACT-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX10-CONTRACT-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX10-CONTRACT-NEXT:    v_lshl_or_b32 v0, v2, 16, v0
+; GFX10-CONTRACT-NEXT:    v_pk_fma_f16 v1, v1, v3, v5
 ; GFX10-CONTRACT-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-DENORM-LABEL: test_3xhalf_add_mul_rhs:
 ; GFX10-DENORM:       ; %bb.0: ; %.entry
 ; GFX10-DENORM-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-DENORM-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-DENORM-NEXT:    v_lshrrev_b32_e32 v6, 16, v0
-; GFX10-DENORM-NEXT:    v_lshrrev_b32_e32 v7, 16, v2
-; GFX10-DENORM-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX10-DENORM-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX10-DENORM-NEXT:    v_pk_mul_f16 v0, v0, v2
 ; GFX10-DENORM-NEXT:    v_pk_mul_f16 v1, v1, v3
-; GFX10-DENORM-NEXT:    v_lshl_or_b32 v0, v6, 16, v0
-; GFX10-DENORM-NEXT:    v_lshl_or_b32 v2, v7, 16, v2
+; GFX10-DENORM-NEXT:    v_pk_add_f16 v0, v4, v0
 ; GFX10-DENORM-NEXT:    v_pk_add_f16 v1, v5, v1
-; GFX10-DENORM-NEXT:    v_pk_mul_f16 v0, v0, v2
-; GFX10-DENORM-NEXT:    v_lshrrev_b32_e32 v2, 16, v4
-; GFX10-DENORM-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GFX10-DENORM-NEXT:    v_lshrrev_b32_e32 v6, 16, v0
-; GFX10-DENORM-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX10-DENORM-NEXT:    v_lshl_or_b32 v2, v2, 16, v4
-; GFX10-DENORM-NEXT:    v_lshl_or_b32 v0, v6, 16, v0
-; GFX10-DENORM-NEXT:    v_pk_add_f16 v0, v2, v0
-; GFX10-DENORM-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX10-DENORM-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX10-DENORM-NEXT:    v_lshl_or_b32 v0, v2, 16, v0
 ; GFX10-DENORM-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-UNSAFE-LABEL: test_3xhalf_add_mul_rhs:
 ; GFX10-UNSAFE:       ; %bb.0: ; %.entry
 ; GFX10-UNSAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-UNSAFE-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-UNSAFE-NEXT:    v_lshrrev_b32_e32 v6, 16, v0
-; GFX10-UNSAFE-NEXT:    v_lshrrev_b32_e32 v7, 16, v2
-; GFX10-UNSAFE-NEXT:    v_lshrrev_b32_e32 v8, 16, v4
-; GFX10-UNSAFE-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX10-UNSAFE-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX10-UNSAFE-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GFX10-UNSAFE-NEXT:    v_pk_fma_f16 v1, v1, v3, v5
-; GFX10-UNSAFE-NEXT:    v_lshl_or_b32 v0, v6, 16, v0
-; GFX10-UNSAFE-NEXT:    v_lshl_or_b32 v2, v7, 16, v2
-; GFX10-UNSAFE-NEXT:    v_lshl_or_b32 v4, v8, 16, v4
 ; GFX10-UNSAFE-NEXT:    v_pk_fma_f16 v0, v0, v2, v4
-; GFX10-UNSAFE-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX10-UNSAFE-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX10-UNSAFE-NEXT:    v_lshl_or_b32 v0, v2, 16, v0
+; GFX10-UNSAFE-NEXT:    v_pk_fma_f16 v1, v1, v3, v5
 ; GFX10-UNSAFE-NEXT:    s_setpc_b64 s[30:31]
 .entry:
   %a = fmul <3 x half> %x, %y
   %b = fadd <3 x half> %z, %a
   ret <3 x half> %b
 }
 
 define <4 x double> @test_4xdouble_add_mul(<4 x double> %x, <4 x double> %y, <4 x double> %z) {

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.1d.d16.ll

 ; GFX9-NEXT:    s_mov_b32 s2, s4
 ; GFX9-NEXT:    s_mov_b32 s3, s5
 ; GFX9-NEXT:    s_mov_b32 s4, s6
 ; GFX9-NEXT:    s_mov_b32 s5, s7
 ; GFX9-NEXT:    s_mov_b32 s6, s8
 ; GFX9-NEXT:    s_mov_b32 s7, s9
 ; GFX9-NEXT:    image_load v[0:1], v0, s[0:7] dmask:0x7 unorm d16
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
-; GFX9-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX9-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX9-NEXT:    v_lshl_or_b32 v0, v2, 16, v0
-; GFX9-NEXT:    ; return to shader part epilog
-;
-; GFX10-LABEL: load_1d_v3f16_xyz:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_mov_b32 s0, s2
-; GFX10-NEXT:    s_mov_b32 s1, s3
-; GFX10-NEXT:    s_mov_b32 s2, s4
-; GFX10-NEXT:    s_mov_b32 s3, s5
-; GFX10-NEXT:    s_mov_b32 s4, s6
-; GFX10-NEXT:    s_mov_b32 s5, s7
-; GFX10-NEXT:    s_mov_b32 s6, s8
-; GFX10-NEXT:    s_mov_b32 s7, s9
-; GFX10-NEXT:    image_load v[0:1], v0, s[0:7] dmask:0x7 dim:SQ_RSRC_IMG_1D unorm d16
-; GFX10-NEXT:    s_waitcnt vmcnt(0)
-; GFX10-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX10-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX10-NEXT:    v_lshl_or_b32 v0, v2, 16, v0
-; GFX10-NEXT:    ; return to shader part epilog
-;
-; GFX11-LABEL: load_1d_v3f16_xyz:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_mov_b32 s0, s2
-; GFX11-NEXT:    s_mov_b32 s1, s3
-; GFX11-NEXT:    s_mov_b32 s2, s4
-; GFX11-NEXT:    s_mov_b32 s3, s5
-; GFX11-NEXT:    s_mov_b32 s4, s6
-; GFX11-NEXT:    s_mov_b32 s5, s7
-; GFX11-NEXT:    s_mov_b32 s6, s8
-; GFX11-NEXT:    s_mov_b32 s7, s9
-; GFX11-NEXT:    image_load v[0:1], v0, s[0:7] dmask:0x7 dim:SQ_RSRC_IMG_1D unorm d16
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_lshl_or_b32 v0, v2, 16, v0
-; GFX11-NEXT:    ; return to shader part epilog
+; GFX9-NEXT:    ; return to shader part epilog
+;
+; GFX10PLUS-LABEL: load_1d_v3f16_xyz:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_mov_b32 s0, s2
+; GFX10PLUS-NEXT:    s_mov_b32 s1, s3
+; GFX10PLUS-NEXT:    s_mov_b32 s2, s4
+; GFX10PLUS-NEXT:    s_mov_b32 s3, s5
+; GFX10PLUS-NEXT:    s_mov_b32 s4, s6
+; GFX10PLUS-NEXT:    s_mov_b32 s5, s7
+; GFX10PLUS-NEXT:    s_mov_b32 s6, s8
+; GFX10PLUS-NEXT:    s_mov_b32 s7, s9
+; GFX10PLUS-NEXT:    image_load v[0:1], v0, s[0:7] dmask:0x7 dim:SQ_RSRC_IMG_1D unorm d16
+; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0)
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %v = call <3 x half> @llvm.amdgcn.image.load.1d.v3f16.i32(i32 7, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
   ret <3 x half> %v
 }
 
 define amdgpu_ps <4 x half> @load_1d_v4f16_xyzw(<8 x i32> inreg %rsrc, i32 %s) {
 ; GFX8-UNPACKED-LABEL: load_1d_v4f16_xyzw:
 ; GFX8-UNPACKED:       ; %bb.0:
 ; GFX8-UNPACKED-NEXT:    s_mov_b32 s0, s2

 declare <4 x half> @llvm.amdgcn.image.load.1d.v4f16.i32(i32 immarg, i32, <8 x i32>, i32 immarg, i32 immarg) #0
 
 declare { half, i32 } @llvm.amdgcn.image.load.1d.sl_f16i32s.i32(i32 immarg, i32, <8 x i32>, i32 immarg, i32 immarg) #0
 declare { <2 x half>, i32 } @llvm.amdgcn.image.load.1d.sl_v2f16i32s.i32(i32 immarg, i32, <8 x i32>, i32 immarg, i32 immarg) #0
 declare { <3 x half>, i32 } @llvm.amdgcn.image.load.1d.sl_v3f16i32s.i32(i32 immarg, i32, <8 x i32>, i32 immarg, i32 immarg) #0
 declare { <4 x half>, i32 } @llvm.amdgcn.image.load.1d.sl_v4f16i32s.i32(i32 immarg, i32, <8 x i32>, i32 immarg, i32 immarg) #0
 
 attributes #0 = { nounwind readonly }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GFX10: {{.*}}
+; GFX11: {{.*}}

llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-buildvector-identities.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=amdgpu-postlegalizer-combiner -verify-machineinstrs -o - %s | FileCheck %s
+
+---
+name: v2s16_trunc_same_bitcast_lshr16
+tracksRegLiveness: true
+legalized: true
+body: |
+  bb.0:
+    liveins: $vgpr0
+    ; CHECK-LABEL: name: v2s16_trunc_same_bitcast_lshr16
+    ; CHECK: liveins: $vgpr0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: %src:_(<2 x s16>) = COPY $vgpr0
+    ; CHECK-NEXT: $vgpr0 = COPY %src(<2 x s16>)
+    %src:_(<2 x s16>) = COPY $vgpr0
+    %bitcast:_(s32) = G_BITCAST %src
+    %lshr_amount:_(s32) = G_CONSTANT i32 16
+    %lshr:_(s32) = G_LSHR %bitcast, %lshr_amount
+    %root:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC %bitcast, %lshr
+    $vgpr0 = COPY %root
+...
+
+---
+name: v2s16_trunc_different_bitcast_lshr16
+tracksRegLiveness: true
+legalized: true
+body: |
+  bb.0:
+    liveins: $vgpr0
+    ; CHECK-LABEL: name: v2s16_trunc_different_bitcast_lshr16
+    ; CHECK: liveins: $vgpr0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: %src:_(<2 x s16>) = COPY $vgpr0
+    ; CHECK-NEXT: $vgpr0 = COPY %src(<2 x s16>)
+    %src:_(<2 x s16>) = COPY $vgpr0
+    %bitcast0:_(s32) = G_BITCAST %src
+    %bitcast1:_(s32) = G_BITCAST %src
+    %lshr_amount:_(s32) = G_CONSTANT i32 16
+    %lshr:_(s32) = G_LSHR %bitcast1, %lshr_amount
+    %root:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC %bitcast0, %lshr
+    $vgpr0 = COPY %root
+...
+
+---
+name: v2s16_trunc_same_bitcast_lshr8_nocombine
+tracksRegLiveness: true
+legalized: true
+body: |
+  bb.0:
+    liveins: $vgpr0
+    ; CHECK-LABEL: name: v2s16_trunc_same_bitcast_lshr8_nocombine
+    ; CHECK: liveins: $vgpr0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: %src:_(<2 x s16>) = COPY $vgpr0
+    ; CHECK-NEXT: %bitcast:_(s32) = G_BITCAST %src(<2 x s16>)
+    ; CHECK-NEXT: %lshr_amount:_(s32) = G_CONSTANT i32 8
+    ; CHECK-NEXT: %lshr:_(s32) = G_LSHR %bitcast, %lshr_amount(s32)
+    ; CHECK-NEXT: %root:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC %bitcast(s32), %lshr(s32)
+    ; CHECK-NEXT: $vgpr0 = COPY %root(<2 x s16>)
+    %src:_(<2 x s16>) = COPY $vgpr0
+    %bitcast:_(s32) = G_BITCAST %src
+    %lshr_amount:_(s32) = G_CONSTANT i32 8
+    %lshr:_(s32) = G_LSHR %bitcast, %lshr_amount
+    %root:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC %bitcast, %lshr
+    $vgpr0 = COPY %root
+...
+
+---
+name: v2s16_same_bitcast_lshr16
+tracksRegLiveness: true
+legalized: true
+body: |
+  bb.0:
+    liveins: $vgpr0
+    ; CHECK-LABEL: name: v2s16_same_bitcast_lshr16
+    ; CHECK: liveins: $vgpr0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: %src:_(<2 x s16>) = COPY $vgpr0
+    ; CHECK-NEXT: $vgpr0 = COPY %src(<2 x s16>)
+    %src:_(<2 x s16>) = COPY $vgpr0
+    %bitcast:_(s32) = G_BITCAST %src
+    %lshr_amount:_(s32) = G_CONSTANT i32 16
+    %lshr:_(s32) = G_LSHR %bitcast, %lshr_amount
+    %trunclo:_(s16) = G_TRUNC %bitcast
+    %trunchi:_(s16) = G_TRUNC %lshr
+    %root:_(<2 x s16>) = G_BUILD_VECTOR %trunclo, %trunchi
+    $vgpr0 = COPY %root
+...
+
+---
+name: v2s16_same_bitcast_lshr8_nocombine
+tracksRegLiveness: true
+legalized: true
+body: |
+  bb.0:
+    liveins: $vgpr0
+    ; CHECK-LABEL: name: v2s16_same_bitcast_lshr8_nocombine
+    ; CHECK: liveins: $vgpr0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: %src:_(<2 x s16>) = COPY $vgpr0
+    ; CHECK-NEXT: %bitcast:_(s32) = G_BITCAST %src(<2 x s16>)
+    ; CHECK-NEXT: %lshr_amount:_(s32) = G_CONSTANT i32 8
+    ; CHECK-NEXT: %lshr:_(s32) = G_LSHR %bitcast, %lshr_amount(s32)
+    ; CHECK-NEXT: %trunclo:_(s16) = G_TRUNC %bitcast(s32)
+    ; CHECK-NEXT: %trunchi:_(s16) = G_TRUNC %lshr(s32)
+    ; CHECK-NEXT: %root:_(<2 x s16>) = G_BUILD_VECTOR %trunclo(s16), %trunchi(s16)
+    ; CHECK-NEXT: $vgpr0 = COPY %root(<2 x s16>)
+    %src:_(<2 x s16>) = COPY $vgpr0
+    %bitcast:_(s32) = G_BITCAST %src
+    %lshr_amount:_(s32) = G_CONSTANT i32 8
+    %lshr:_(s32) = G_LSHR %bitcast, %lshr_amount
+    %trunclo:_(s16) = G_TRUNC %bitcast
+    %trunchi:_(s16) = G_TRUNC %lshr
+    %root:_(<2 x s16>) = G_BUILD_VECTOR %trunclo, %trunchi
+    $vgpr0 = COPY %root
+...
+
+---
+name: v2s16_undefhi
+tracksRegLiveness: true
+legalized: true
+body: |
+  bb.0:
+    liveins: $vgpr0
+    ; CHECK-LABEL: name: v2s16_undefhi
+    ; CHECK: liveins: $vgpr0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: %src:_(<2 x s16>) = COPY $vgpr0
+    ; CHECK-NEXT: $vgpr0 = COPY %src(<2 x s16>)
+    %src:_(<2 x s16>) = COPY $vgpr0
+    %bitcast:_(s32) = G_BITCAST %src
+    %trunc:_(s16) = G_TRUNC %bitcast
+    %undef:_(s16) = G_IMPLICIT_DEF
+    %root:_(<2 x s16>) = G_BUILD_VECTOR %trunc, %undef
+    $vgpr0 = COPY %root
+...
+
+---
+name: v2s32_undefhi
+tracksRegLiveness: true
+legalized: true
+body: |
+  bb.0:
+    liveins: $vgpr0_vgpr1
+    ; CHECK-LABEL: name: v2s32_undefhi
+    ; CHECK: liveins: $vgpr0_vgpr1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: %src:_(<2 x s32>) = COPY $vgpr0_vgpr1
+    ; CHECK-NEXT: $vgpr0_vgpr1 = COPY %src(<2 x s32>)
+    %src:_(<2 x s32>) = COPY $vgpr0_vgpr1
+    %bitcast:_(s64) = G_BITCAST %src
+    %trunc:_(s32) = G_TRUNC %bitcast
+    %undef:_(s32) = G_IMPLICIT_DEF
+    %root:_(<2 x s32>) = G_BUILD_VECTOR %trunc, %undef
+    $vgpr0_vgpr1 = COPY %root
+...

llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-trunc-bitcast-buildvector.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=amdgpu-postlegalizer-combiner -verify-machineinstrs -o - %s | FileCheck %s
+
+---
+name: s16_trunc_v2s16_buildvector
+tracksRegLiveness: true
+body: |
+  bb.0:
+    liveins: $vgpr0, $vgpr1
+    ; CHECK-LABEL: name: s16_trunc_v2s16_buildvector
+    ; CHECK: liveins: $vgpr0, $vgpr1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 42
+    ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s16) = G_OR [[C]], [[TRUNC]]
+    ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR]](s16)
+    ; CHECK-NEXT: $vgpr0 = COPY [[ZEXT]](s32)
+    %0:_(s32) = COPY $vgpr0
+    %1:_(s32) = COPY $vgpr1
+    %2:_(s16) = G_TRUNC %0
+    %3:_(s16) = G_TRUNC %1
+    %4:_(<2 x s16>) = G_BUILD_VECTOR %2, %3
+    %5:_(s32) = G_BITCAST %4
+    %6:_(s16) = G_TRUNC %5
+    %7:_(s16) = G_CONSTANT i16 42
+    %8:_(s16) = G_OR %7, %6
+    %9:_(s32) = G_ZEXT %8
+    $vgpr0 = COPY %9
+...
+
+---
+name: s16_trunc_v2s32_buildvector_nofold
+tracksRegLiveness: true
+body: |
+  bb.0:
+    liveins: $vgpr0, $vgpr1
+    ; CHECK-LABEL: name: s16_trunc_v2s32_buildvector_nofold
+    ; CHECK: liveins: $vgpr0, $vgpr1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32)
+    ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(s64) = G_BITCAST [[BUILD_VECTOR]](<2 x s32>)
+    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s64)
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 42
+    ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s16) = G_OR [[C]], [[TRUNC]]
+    ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR]](s16)
+    ; CHECK-NEXT: $vgpr0 = COPY [[ZEXT]](s32)
+    %0:_(s32) = COPY $vgpr0
+    %1:_(s32) = COPY $vgpr1
+    %2:_(<2 x s32>) = G_BUILD_VECTOR %0, %1
+    %3:_(s64) = G_BITCAST %2
+    %4:_(s16) = G_TRUNC %3
+    %5:_(s16) = G_CONSTANT i16 42
+    %6:_(s16) = G_OR %5, %4
+    %7:_(s32) = G_ZEXT %6
+    $vgpr0 = COPY %7
+...
+
+---
+name: s32_trunc_v2s32_buildvector
+tracksRegLiveness: true
+body: |
+  bb.0:
+    liveins: $vgpr0, $vgpr1
+    ; CHECK-LABEL: name: s32_trunc_v2s32_buildvector
+    ; CHECK: liveins: $vgpr0, $vgpr1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+    ; CHECK-NEXT: $vgpr0 = COPY [[COPY]](s32)
+    %0:_(s32) = COPY $vgpr0
+    %1:_(s32) = COPY $vgpr1
+    %2:_(<2 x s32>) = G_BUILD_VECTOR %0, %1
+    %3:_(s64) = G_BITCAST %2
+    %4:_(s32) = G_TRUNC %3
+    $vgpr0 = COPY %4
+...
+
+---
+name: s32_trunc_v2s32_buildvector_multiple_users
+tracksRegLiveness: true
+body: |
+  bb.0:
+    liveins: $vgpr0, $vgpr1
+    ; CHECK-LABEL: name: s32_trunc_v2s32_buildvector_multiple_users
+    ; CHECK: liveins: $vgpr0, $vgpr1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32)
+    ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(s64) = G_BITCAST [[BUILD_VECTOR]](<2 x s32>)
+    ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<2 x s32>), [[COPY1]](s32)
+    ; CHECK-NEXT: $vgpr0 = COPY [[COPY]](s32)
+    ; CHECK-NEXT: $vgpr1 = COPY [[EVEC]](s32)
+    ; CHECK-NEXT: $vgpr2_vgpr3 = COPY [[BITCAST]](s64)
+    %0:_(s32) = COPY $vgpr0
+    %1:_(s32) = COPY $vgpr1
+    %2:_(<2 x s32>) = G_BUILD_VECTOR %0, %1
+    %3:_(s64) = G_BITCAST %2
+    %4:_(s32) = G_TRUNC %3
+    %5:_(s32) = G_EXTRACT_VECTOR_ELT %2, %1
+    $vgpr0 = COPY %4
+    $vgpr1 = COPY %5
+    $vgpr2_vgpr3 = COPY %3
+...