[AMDGPU][MC][GFX11] Disable non-null src0 for s_waitcnt_*cnt

[dp]

Summary

See https://github.com/llvm/llvm-project/issues/56710.

[foad]

Looks OK for GFX11, I just wonder if there is a way to do this that will automatically work for future architectures too? Or will we just have to remember to update the list of opcodes in validateWaitCnt?

[dp]

In D134809#3820905, @foad wrote:

Looks OK for GFX11, I just wonder if there is a way to do this that will automatically work for future architectures too? Or will we just have to remember to update the list of opcodes in validateWaitCnt?

Unfortunately, I do not see how else we can detect these opcodes in the parser. They do not have any distinct feature flags we could use.
I can add a tablegenned function for opcode detection, but this will not automatically work for future architectures.
If we were able to convert MC opcodes to PSEUDO, this might work.

[dp]

As an afterthought, I think this instruction will unlikely exist in future architectures (at least in the current form). I believe src0 will be either removed or repurposed.

[dp]

Fix unexpected disassembler breakage caused by this change. Update disassembler tests.

[Joe_Nash]

LGTM

llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

private:
   bool validateMAIAccWrite(const MCInst &Inst, const OperandVector &Operands);
   bool validateMAISrc2(const MCInst &Inst, const OperandVector &Operands);
   bool validateMFMA(const MCInst &Inst, const OperandVector &Operands);
   bool validateAGPRLdSt(const MCInst &Inst) const;
   bool validateVGPRAlign(const MCInst &Inst) const;
   bool validateBLGP(const MCInst &Inst, const OperandVector &Operands);
   bool validateGWS(const MCInst &Inst, const OperandVector &Operands);
   bool validateDivScale(const MCInst &Inst);
+  bool validateWaitCnt(const MCInst &Inst, const OperandVector &Operands);
   bool validateCoherencyBits(const MCInst &Inst, const OperandVector &Operands,
                              const SMLoc &IDLoc);
   bool validateLdsDMA(uint64_t Enc, const MCInst &Inst,
                       const OperandVector &Operands, const SMLoc &IDLoc);
   bool validateExeczVcczOperands(const OperandVector &Operands);
   Optional<StringRef> validateLdsDirect(const MCInst &Inst);
   unsigned getConstantBusLimit(unsigned Opcode) const;
   bool usesConstantBus(const MCInst &Inst, unsigned OpIdx);
bool AMDGPUAsmParser::validateBLGP(const MCInst &Inst,
 
   Error(BLGPLoc,
         UsesNeg ? "invalid modifier: blgp is not supported"
                 : "invalid modifier: neg is not supported");
 
   return false;
 }
 
+bool AMDGPUAsmParser::validateWaitCnt(const MCInst &Inst,
+                                      const OperandVector &Operands) {
+  if (!isGFX11Plus())
+    return true;
+
+  unsigned Opc = Inst.getOpcode();
+  if (Opc != AMDGPU::S_WAITCNT_EXPCNT_gfx11 &&
+      Opc != AMDGPU::S_WAITCNT_LGKMCNT_gfx11 &&
+      Opc != AMDGPU::S_WAITCNT_VMCNT_gfx11 &&
+      Opc != AMDGPU::S_WAITCNT_VSCNT_gfx11)
+    return true;
+
+  int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::sdst);
+  assert(Src0Idx >= 0 && Inst.getOperand(Src0Idx).isReg());
+  auto Reg = mc2PseudoReg(Inst.getOperand(Src0Idx).getReg());
+  if (Reg == AMDGPU::SGPR_NULL)
+    return true;
+
+  SMLoc RegLoc = getRegLoc(Reg, Operands);
+  Error(RegLoc, "src0 must be null");
+  return false;
+}
+
 // gfx90a has an undocumented limitation:
 // DS_GWS opcodes must use even aligned registers.
 bool AMDGPUAsmParser::validateGWS(const MCInst &Inst,
                                   const OperandVector &Operands) {
   if (!getFeatureBits()[AMDGPU::FeatureGFX90AInsts])
     return true;
 
   int Opc = Inst.getOpcode();
bool AMDGPUAsmParser::validateInstruction(const MCInst &Inst,
   if (!validateBLGP(Inst, Operands)) {
     return false;
   }
 
   if (!validateDivScale(Inst)) {
     Error(IDLoc, "ABS not allowed in VOP3B instructions");
     return false;
   }
+  if (!validateWaitCnt(Inst, Operands)) {
+    return false;
+  }
   if (!validateExeczVcczOperands(Operands)) {
     return false;
   }
 
   if (!validateLdsDMA(SIInstrFlags::FLAT, Inst, Operands, IDLoc)) {
     return false;
   }
 

llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp

if (Tied != -1 && (MI.getNumOperands() <= (unsigned)VDstIn_Idx ||
       insertNamedMCOperand(MI,
         MCOperand::createReg(MI.getOperand(Tied).getReg()),
         AMDGPU::OpName::vdst_in);
     }
   }
 
   int ImmLitIdx =
       AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::imm);
-  if (Res && ImmLitIdx != -1)
+  bool isVOP2 = MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOP2;
+  if (Res && ImmLitIdx != -1 && (isVOP2 || AMDGPU::isVOPD(MI.getOpcode())))
     Res = convertFMAanyK(MI, ImmLitIdx);
 
   // if the opcode was not recognized we'll assume a Size of 4 bytes
   // (unless there are fewer bytes left)
   Size = Res ? (MaxInstBytesNum - Bytes.size())
              : std::min((size_t)4, Bytes_.size());
   return Res;
 }

llvm/lib/Target/AMDGPU/SOPInstructions.td

 
 class SOPK_Real<SOPK_Pseudo ps> :
   InstSI <ps.OutOperandList, ps.InOperandList,
           ps.Mnemonic # " " # ps.AsmOperands, []> {
   let SALU = 1;
   let SOPK = 1;
   let isPseudo = 0;
   let isCodeGenOnly = 0;
+  let UseNamedOperandTable = 1;
 
   // copy relevant pseudo op flags
   let SubtargetPredicate = ps.SubtargetPredicate;
   let AsmMatchConverter  = ps.AsmMatchConverter;
   let DisableEncoding    = ps.DisableEncoding;
   let Constraints        = ps.Constraints;
   let SchedRW            = ps.SchedRW;
   let mayLoad            = ps.mayLoad;

llvm/test/MC/AMDGPU/gfx11_asm_sopk.s

 // GFX11: encoding: [0x34,0x12,0x7e,0xba]
 
 s_call_b64 vcc, 0x1234
 // GFX11: encoding: [0x34,0x12,0x6a,0xba]
 
 s_call_b64 null, 0x1234
 // GFX11: encoding: [0x34,0x12,0x7c,0xba]
 
-s_waitcnt_vscnt s0, 0x1234
-// GFX11: encoding: [0x34,0x12,0x00,0xbc]
+s_waitcnt_vscnt null, 0x1234
+// GFX11: encoding: [0x34,0x12,0x7c,0xbc]
 
-s_waitcnt_vscnt s0, 0xc1d1
-// GFX11: encoding: [0xd1,0xc1,0x00,0xbc]
+s_waitcnt_vscnt null, 0xc1d1
+// GFX11: encoding: [0xd1,0xc1,0x7c,0xbc]
 
-s_waitcnt_vscnt s105, 0x1234
-// GFX11: encoding: [0x34,0x12,0x69,0xbc]
+s_waitcnt_vmcnt null, 0x1234
+// GFX11: encoding: [0x34,0x12,0xfc,0xbc]
 
-s_waitcnt_vscnt exec_lo, 0x1234
-// GFX11: encoding: [0x34,0x12,0x7e,0xbc]
+s_waitcnt_vmcnt null, 0xc1d1
+// GFX11: encoding: [0xd1,0xc1,0xfc,0xbc]
 
-s_waitcnt_vscnt exec_hi, 0x1234
-// GFX11: encoding: [0x34,0x12,0x7f,0xbc]
+s_waitcnt_expcnt null, 0x1234
+// GFX11: encoding: [0x34,0x12,0x7c,0xbd]
 
-s_waitcnt_vscnt vcc_lo, 0x1234
-// GFX11: encoding: [0x34,0x12,0x6a,0xbc]
+s_waitcnt_expcnt null, 0xc1d1
+// GFX11: encoding: [0xd1,0xc1,0x7c,0xbd]
 
-s_waitcnt_vscnt vcc_hi, 0x1234
-// GFX11: encoding: [0x34,0x12,0x6b,0xbc]
+s_waitcnt_lgkmcnt null, 0x1234
+// GFX11: encoding: [0x34,0x12,0xfc,0xbd]
 
-s_waitcnt_vscnt m0, 0x1234
-// GFX11: encoding: [0x34,0x12,0x7d,0xbc]
-
-s_waitcnt_vmcnt s0, 0x1234
-// GFX11: encoding: [0x34,0x12,0x80,0xbc]
-
-s_waitcnt_vmcnt s0, 0xc1d1
-// GFX11: encoding: [0xd1,0xc1,0x80,0xbc]
-
-s_waitcnt_vmcnt s105, 0x1234
-// GFX11: encoding: [0x34,0x12,0xe9,0xbc]
-
-s_waitcnt_vmcnt exec_lo, 0x1234
-// GFX11: encoding: [0x34,0x12,0xfe,0xbc]
-
-s_waitcnt_vmcnt exec_hi, 0x1234
-// GFX11: encoding: [0x34,0x12,0xff,0xbc]
-
-s_waitcnt_vmcnt vcc_lo, 0x1234
-// GFX11: encoding: [0x34,0x12,0xea,0xbc]
-
-s_waitcnt_vmcnt vcc_hi, 0x1234
-// GFX11: encoding: [0x34,0x12,0xeb,0xbc]
-
-s_waitcnt_vmcnt m0, 0x1234
-// GFX11: encoding: [0x34,0x12,0xfd,0xbc]
-
-s_waitcnt_expcnt s0, 0x1234
-// GFX11: encoding: [0x34,0x12,0x00,0xbd]
-
-s_waitcnt_expcnt s0, 0xc1d1
-// GFX11: encoding: [0xd1,0xc1,0x00,0xbd]
-
-s_waitcnt_expcnt s105, 0x1234
-// GFX11: encoding: [0x34,0x12,0x69,0xbd]
-
-s_waitcnt_expcnt exec_lo, 0x1234
-// GFX11: encoding: [0x34,0x12,0x7e,0xbd]
-
-s_waitcnt_expcnt exec_hi, 0x1234
-// GFX11: encoding: [0x34,0x12,0x7f,0xbd]
-
-s_waitcnt_expcnt vcc_lo, 0x1234
-// GFX11: encoding: [0x34,0x12,0x6a,0xbd]
-
-s_waitcnt_expcnt vcc_hi, 0x1234
-// GFX11: encoding: [0x34,0x12,0x6b,0xbd]
-
-s_waitcnt_expcnt m0, 0x1234
-// GFX11: encoding: [0x34,0x12,0x7d,0xbd]
-
-s_waitcnt_lgkmcnt s0, 0x1234
-// GFX11: encoding: [0x34,0x12,0x80,0xbd]
-
-s_waitcnt_lgkmcnt s0, 0xc1d1
-// GFX11: encoding: [0xd1,0xc1,0x80,0xbd]
-
-s_waitcnt_lgkmcnt s105, 0x1234
-// GFX11: encoding: [0x34,0x12,0xe9,0xbd]
-
-s_waitcnt_lgkmcnt exec_lo, 0x1234
-// GFX11: encoding: [0x34,0x12,0xfe,0xbd]
-
-s_waitcnt_lgkmcnt exec_hi, 0x1234
-// GFX11: encoding: [0x34,0x12,0xff,0xbd]
-
-s_waitcnt_lgkmcnt vcc_lo, 0x1234
-// GFX11: encoding: [0x34,0x12,0xea,0xbd]
-
-s_waitcnt_lgkmcnt vcc_hi, 0x1234
-// GFX11: encoding: [0x34,0x12,0xeb,0xbd]
-
-s_waitcnt_lgkmcnt m0, 0x1234
-// GFX11: encoding: [0x34,0x12,0xfd,0xbd]
+s_waitcnt_lgkmcnt null, 0xc1d1
+// GFX11: encoding: [0xd1,0xc1,0xfc,0xbd]
 
 s_subvector_loop_begin s0, 0x1234
 // GFX11: encoding: [0x34,0x12,0x00,0xbb]
 
 s_subvector_loop_begin s105, 0x1234
 // GFX11: encoding: [0x34,0x12,0x69,0xbb]
 
 s_subvector_loop_begin exec_lo, 0x1234

llvm/test/MC/AMDGPU/gfx11_asm_sopk_err.s

+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 %s 2>&1 | FileCheck %s -check-prefix=GFX11 --implicit-check-not=error: --strict-whitespace
+
+s_waitcnt_vscnt s0, 0x1234
+// GFX11: error: src0 must be null
+// GFX11-NEXT:{{^}}s_waitcnt_vscnt s0, 0x1234
+// GFX11-NEXT:{{^}}                ^
+
+s_waitcnt_vmcnt exec_lo, 0x1234
+// GFX11: error: src0 must be null
+// GFX11-NEXT:{{^}}s_waitcnt_vmcnt exec_lo, 0x1234
+// GFX11-NEXT:{{^}}                ^
+
+s_waitcnt_expcnt vcc_lo, 0x1234
+// GFX11: error: src0 must be null
+// GFX11-NEXT:{{^}}s_waitcnt_expcnt vcc_lo, 0x1234
+// GFX11-NEXT:{{^}}                 ^
+
+s_waitcnt_lgkmcnt m0, 0x1234
+// GFX11: error: src0 must be null
+// GFX11-NEXT:{{^}}s_waitcnt_lgkmcnt m0, 0x1234
+// GFX11-NEXT:{{^}}                  ^

llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_sopk.txt

 0x34,0x12,0xea,0xbb
 
 # GFX11: s_version 0x1234                        ; encoding: [0x34,0x12,0x80,0xb0]
 0x34,0x12,0x80,0xb0
 
 # GFX11: s_version 0xc1d1                        ; encoding: [0xd1,0xc1,0x80,0xb0]
 0xd1,0xc1,0x80,0xb0
 
-# GFX11: s_waitcnt_expcnt exec_hi, 0x1234        ; encoding: [0x34,0x12,0x7f,0xbd]
-0x34,0x12,0x7f,0xbd
+# GFX11: s_waitcnt_expcnt null, 0x1234           ; encoding: [0x34,0x12,0x7c,0xbd]
+0x34,0x12,0x7c,0xbd
 
-# GFX11: s_waitcnt_expcnt exec_lo, 0x1234        ; encoding: [0x34,0x12,0x7e,0xbd]
-0x34,0x12,0x7e,0xbd
-
-# GFX11: s_waitcnt_expcnt m0, 0x1234             ; encoding: [0x34,0x12,0x7d,0xbd]
-0x34,0x12,0x7d,0xbd
-
-# GFX11: s_waitcnt_expcnt s0, 0x1234             ; encoding: [0x34,0x12,0x00,0xbd]
-0x34,0x12,0x00,0xbd
-
-# GFX11: s_waitcnt_expcnt s0, 0xc1d1             ; encoding: [0xd1,0xc1,0x00,0xbd]
-0xd1,0xc1,0x00,0xbd
+# GFX11: s_waitcnt_expcnt null, 0xc1d1           ; encoding: [0xd1,0xc1,0x7c,0xbd]
+0xd1,0xc1,0x7c,0xbd
 
 # GFX11: s_waitcnt_expcnt s105, 0x1234           ; encoding: [0x34,0x12,0x69,0xbd]
 0x34,0x12,0x69,0xbd
 
-# GFX11: s_waitcnt_expcnt vcc_hi, 0x1234         ; encoding: [0x34,0x12,0x6b,0xbd]
-0x34,0x12,0x6b,0xbd
-
-# GFX11: s_waitcnt_expcnt vcc_lo, 0x1234         ; encoding: [0x34,0x12,0x6a,0xbd]
-0x34,0x12,0x6a,0xbd
-
-# GFX11: s_waitcnt_lgkmcnt exec_hi, 0x1234       ; encoding: [0x34,0x12,0xff,0xbd]
-0x34,0x12,0xff,0xbd
-
-# GFX11: s_waitcnt_lgkmcnt exec_lo, 0x1234       ; encoding: [0x34,0x12,0xfe,0xbd]
-0x34,0x12,0xfe,0xbd
+# GFX11: s_waitcnt_lgkmcnt null, 0x1234          ; encoding: [0x34,0x12,0xfc,0xbd]
+0x34,0x12,0xfc,0xbd
 
-# GFX11: s_waitcnt_lgkmcnt m0, 0x1234            ; encoding: [0x34,0x12,0xfd,0xbd]
-0x34,0x12,0xfd,0xbd
-
-# GFX11: s_waitcnt_lgkmcnt s0, 0x1234            ; encoding: [0x34,0x12,0x80,0xbd]
-0x34,0x12,0x80,0xbd
-
-# GFX11: s_waitcnt_lgkmcnt s0, 0xc1d1            ; encoding: [0xd1,0xc1,0x80,0xbd]
-0xd1,0xc1,0x80,0xbd
-
-# GFX11: s_waitcnt_lgkmcnt s105, 0x1234          ; encoding: [0x34,0x12,0xe9,0xbd]
-0x34,0x12,0xe9,0xbd
+# GFX11: s_waitcnt_lgkmcnt null, 0xc1d1          ; encoding: [0xd1,0xc1,0xfc,0xbd]
+0xd1,0xc1,0xfc,0xbd
 
 # GFX11: s_waitcnt_lgkmcnt vcc_hi, 0x1234        ; encoding: [0x34,0x12,0xeb,0xbd]
 0x34,0x12,0xeb,0xbd
 
-# GFX11: s_waitcnt_lgkmcnt vcc_lo, 0x1234        ; encoding: [0x34,0x12,0xea,0xbd]
-0x34,0x12,0xea,0xbd
+# GFX11: s_waitcnt_vmcnt null, 0x1234            ; encoding: [0x34,0x12,0xfc,0xbc]
+0x34,0x12,0xfc,0xbc
+
+# GFX11: s_waitcnt_vmcnt null, 0xc1d1            ; encoding: [0xd1,0xc1,0xfc,0xbc]
+0xd1,0xc1,0xfc,0xbc
 
 # GFX11: s_waitcnt_vmcnt exec_hi, 0x1234         ; encoding: [0x34,0x12,0xff,0xbc]
 0x34,0x12,0xff,0xbc
 
-# GFX11: s_waitcnt_vmcnt exec_lo, 0x1234         ; encoding: [0x34,0x12,0xfe,0xbc]
-0x34,0x12,0xfe,0xbc
-
-# GFX11: s_waitcnt_vmcnt m0, 0x1234              ; encoding: [0x34,0x12,0xfd,0xbc]
-0x34,0x12,0xfd,0xbc
+# GFX11: s_waitcnt_vscnt null, 0x1234            ; encoding: [0x34,0x12,0x7c,0xbc]
+0x34,0x12,0x7c,0xbc
 
-# GFX11: s_waitcnt_vmcnt s0, 0x1234              ; encoding: [0x34,0x12,0x80,0xbc]
-0x34,0x12,0x80,0xbc
-
-# GFX11: s_waitcnt_vmcnt s0, 0xc1d1              ; encoding: [0xd1,0xc1,0x80,0xbc]
-0xd1,0xc1,0x80,0xbc
-
-# GFX11: s_waitcnt_vmcnt s105, 0x1234            ; encoding: [0x34,0x12,0xe9,0xbc]
-0x34,0x12,0xe9,0xbc
-
-# GFX11: s_waitcnt_vmcnt vcc_hi, 0x1234          ; encoding: [0x34,0x12,0xeb,0xbc]
-0x34,0x12,0xeb,0xbc
-
-# GFX11: s_waitcnt_vmcnt vcc_lo, 0x1234          ; encoding: [0x34,0x12,0xea,0xbc]
-0x34,0x12,0xea,0xbc
-
-# GFX11: s_waitcnt_vscnt exec_hi, 0x1234         ; encoding: [0x34,0x12,0x7f,0xbc]
-0x34,0x12,0x7f,0xbc
-
-# GFX11: s_waitcnt_vscnt exec_lo, 0x1234         ; encoding: [0x34,0x12,0x7e,0xbc]
-0x34,0x12,0x7e,0xbc
+# GFX11: s_waitcnt_vscnt null, 0xc1d1            ; encoding: [0xd1,0xc1,0x7c,0xbc]
+0xd1,0xc1,0x7c,0xbc
 
 # GFX11: s_waitcnt_vscnt m0, 0x1234              ; encoding: [0x34,0x12,0x7d,0xbc]
 0x34,0x12,0x7d,0xbc
 
-# GFX11: s_waitcnt_vscnt s0, 0x1234              ; encoding: [0x34,0x12,0x00,0xbc]
-0x34,0x12,0x00,0xbc
-
-# GFX11: s_waitcnt_vscnt s0, 0xc1d1              ; encoding: [0xd1,0xc1,0x00,0xbc]
-0xd1,0xc1,0x00,0xbc
-
-# GFX11: s_waitcnt_vscnt s105, 0x1234            ; encoding: [0x34,0x12,0x69,0xbc]
-0x34,0x12,0x69,0xbc
-
-# GFX11: s_waitcnt_vscnt vcc_hi, 0x1234          ; encoding: [0x34,0x12,0x6b,0xbc]
-0x34,0x12,0x6b,0xbc
-
-# GFX11: s_waitcnt_vscnt vcc_lo, 0x1234          ; encoding: [0x34,0x12,0x6a,0xbc]
-0x34,0x12,0x6a,0xbc
-
 # GFX11: s_setreg_imm32_b32 hwreg(HW_REG_MODE), 0xaf123456 ; encoding: [0x01,0xf8,0x80,0xb9,0x56,0x34,0x12,0xaf]
 0x01,0xf8,0x80,0xb9,0x56,0x34,0x12,0xaf
 
 # GFX11: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 31, 1), 0xaf123456 ; encoding: [0xc1,0x07,0x80,0xb9,0x56,0x34,0x12,0xaf]
 0xc1,0x07,0x80,0xb9,0x56,0x34,0x12,0xaf
 
 # GFX11: s_setreg_imm32_b32 hwreg(HW_REG_STATUS), 0xaf123456 ; encoding: [0x02,0xf8,0x80,0xb9,0x56,0x34,0x12,0xaf]
 0x02,0xf8,0x80,0xb9,0x56,0x34,0x12,0xaf