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Differential D134538

[LLDB][ARM] Move instruction emulation to optional GetRegisterInfo
ClosedPublic

Authored by DavidSpickett on Sep 23 2022, 7:57 AM.

Details

Reviewers
clayborg
Commits
rG0a339b3aeba7: [LLDB][ARM] Move instruction emulation to optional GetRegisterInfo
Summary

Depends on D134537

Diff Detail

Revision Contents

PathSize
lldb/
source/
Plugins/
Instruction/
ARM/
684 lines

Diff 462487

lldb/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
//===-- EmulateInstructionARM.cpp -----------------------------------------===// //===-- EmulateInstructionARM.cpp -----------------------------------------===//
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// //
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information. // See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
▲ Show 20 Lines • Show All 956 Lines • ▼ Show 20 Lines default:
return false; return false;
} }
addr_t sp_offset = addr_byte_size * BitCount(registers); addr_t sp_offset = addr_byte_size * BitCount(registers);
addr_t addr = sp - sp_offset; addr_t addr = sp - sp_offset;
uint32_t i; uint32_t i;
EmulateInstruction::Context context; EmulateInstruction::Context context;
context.type = EmulateInstruction::eContextPushRegisterOnStack; context.type = EmulateInstruction::eContextPushRegisterOnStack;
RegisterInfo reg_info; llvm::Optional<RegisterInfo> sp_reg =
RegisterInfo sp_reg; GetRegisterInfo(eRegisterKindDWARF, dwarf_sp);
GetRegisterInfo(eRegisterKindDWARF, dwarf_sp, sp_reg);
for (i = 0; i < 15; ++i) { for (i = 0; i < 15; ++i) {
if (BitIsSet(registers, i)) { if (BitIsSet(registers, i)) {
GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + i, reg_info); llvm::Optional<RegisterInfo> reg_info =
context.SetRegisterToRegisterPlusOffset(reg_info, sp_reg, addr - sp); GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + i);
context.SetRegisterToRegisterPlusOffset(*reg_info, *sp_reg, addr - sp);
uint32_t reg_value = ReadCoreReg(i, &success); uint32_t reg_value = ReadCoreReg(i, &success);
if (!success) if (!success)
return false; return false;
if (!MemAWrite(context, addr, reg_value, addr_byte_size)) if (!MemAWrite(context, addr, reg_value, addr_byte_size))
return false; return false;
addr += addr_byte_size; addr += addr_byte_size;
} }
} }
if (BitIsSet(registers, 15)) { if (BitIsSet(registers, 15)) {
GetRegisterInfo(eRegisterKindDWARF, dwarf_pc, reg_info); llvm::Optional<RegisterInfo> reg_info =
context.SetRegisterToRegisterPlusOffset(reg_info, sp_reg, addr - sp); GetRegisterInfo(eRegisterKindDWARF, dwarf_pc);
context.SetRegisterToRegisterPlusOffset(*reg_info, *sp_reg, addr - sp);
const uint32_t pc = ReadCoreReg(PC_REG, &success); const uint32_t pc = ReadCoreReg(PC_REG, &success);
if (!success) if (!success)
return false; return false;
if (!MemAWrite(context, addr, pc, addr_byte_size)) if (!MemAWrite(context, addr, pc, addr_byte_size))
return false; return false;
} }
context.type = EmulateInstruction::eContextAdjustStackPointer; context.type = EmulateInstruction::eContextAdjustStackPointer;
▲ Show 20 Lines • Show All 93 Lines • ▼ Show 20 Lines if (ConditionPassed(opcode)) {
} }
addr_t sp_offset = addr_byte_size * BitCount(registers); addr_t sp_offset = addr_byte_size * BitCount(registers);
addr_t addr = sp; addr_t addr = sp;
uint32_t i, data; uint32_t i, data;
EmulateInstruction::Context context; EmulateInstruction::Context context;
context.type = EmulateInstruction::eContextPopRegisterOffStack; context.type = EmulateInstruction::eContextPopRegisterOffStack;
RegisterInfo sp_reg; llvm::Optional<RegisterInfo> sp_reg =
GetRegisterInfo(eRegisterKindDWARF, dwarf_sp, sp_reg); GetRegisterInfo(eRegisterKindDWARF, dwarf_sp);
for (i = 0; i < 15; ++i) { for (i = 0; i < 15; ++i) {
if (BitIsSet(registers, i)) { if (BitIsSet(registers, i)) {
context.SetAddress(addr); context.SetAddress(addr);
data = MemARead(context, addr, 4, 0, &success); data = MemARead(context, addr, 4, 0, &success);
if (!success) if (!success)
return false; return false;
if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + i, if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + i,
data)) data))
return false; return false;
addr += addr_byte_size; addr += addr_byte_size;
} }
} }
if (BitIsSet(registers, 15)) { if (BitIsSet(registers, 15)) {
context.SetRegisterPlusOffset(sp_reg, addr - sp); context.SetRegisterPlusOffset(*sp_reg, addr - sp);
data = MemARead(context, addr, 4, 0, &success); data = MemARead(context, addr, 4, 0, &success);
if (!success) if (!success)
return false; return false;
// In ARMv5T and above, this is an interworking branch. // In ARMv5T and above, this is an interworking branch.
if (!LoadWritePC(context, data)) if (!LoadWritePC(context, data))
return false; return false;
// addr += addr_byte_size; // addr += addr_byte_size;
} }
▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Lines if (ConditionPassed(opcode)) {
addr_t sp_offset = imm32; addr_t sp_offset = imm32;
addr_t addr = sp + sp_offset; // a pointer to the stack area addr_t addr = sp + sp_offset; // a pointer to the stack area
EmulateInstruction::Context context; EmulateInstruction::Context context;
if (Rd == GetFramePointerRegisterNumber()) if (Rd == GetFramePointerRegisterNumber())
context.type = eContextSetFramePointer; context.type = eContextSetFramePointer;
else else
context.type = EmulateInstruction::eContextRegisterPlusOffset; context.type = EmulateInstruction::eContextRegisterPlusOffset;
RegisterInfo sp_reg; llvm::Optional<RegisterInfo> sp_reg =
GetRegisterInfo(eRegisterKindDWARF, dwarf_sp, sp_reg); GetRegisterInfo(eRegisterKindDWARF, dwarf_sp);
context.SetRegisterPlusOffset(sp_reg, sp_offset); context.SetRegisterPlusOffset(*sp_reg, sp_offset);
if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + Rd, if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + Rd,
addr)) addr))
return false; return false;
} }
return true; return true;
} }
Show All 37 Lines default:
return false; return false;
} }
EmulateInstruction::Context context; EmulateInstruction::Context context;
if (Rd == GetFramePointerRegisterNumber()) if (Rd == GetFramePointerRegisterNumber())
context.type = EmulateInstruction::eContextSetFramePointer; context.type = EmulateInstruction::eContextSetFramePointer;
else else
context.type = EmulateInstruction::eContextRegisterPlusOffset; context.type = EmulateInstruction::eContextRegisterPlusOffset;
RegisterInfo sp_reg; llvm::Optional<RegisterInfo> sp_reg =
GetRegisterInfo(eRegisterKindDWARF, dwarf_sp, sp_reg); GetRegisterInfo(eRegisterKindDWARF, dwarf_sp);
context.SetRegisterPlusOffset(sp_reg, 0); context.SetRegisterPlusOffset(*sp_reg, 0);
if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + Rd, sp)) if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + Rd, sp))
return false; return false;
} }
return true; return true;
} }
// Move from high register (r8-r15) to low register (r0-r7). // Move from high register (r8-r15) to low register (r0-r7).
▲ Show 20 Lines • Show All 78 Lines • ▼ Show 20 Lines if (ConditionPassed(opcode)) {
// The context specifies that Rm is to be moved into Rd. // The context specifies that Rm is to be moved into Rd.
EmulateInstruction::Context context; EmulateInstruction::Context context;
if (Rd == 13) if (Rd == 13)
context.type = EmulateInstruction::eContextAdjustStackPointer; context.type = EmulateInstruction::eContextAdjustStackPointer;
else if (Rd == GetFramePointerRegisterNumber() && Rm == 13) else if (Rd == GetFramePointerRegisterNumber() && Rm == 13)
context.type = EmulateInstruction::eContextSetFramePointer; context.type = EmulateInstruction::eContextSetFramePointer;
else else
context.type = EmulateInstruction::eContextRegisterPlusOffset; context.type = EmulateInstruction::eContextRegisterPlusOffset;
RegisterInfo dwarf_reg; llvm::Optional<RegisterInfo> dwarf_reg =
GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + Rm, dwarf_reg); GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + Rm);
context.SetRegisterPlusOffset(dwarf_reg, 0); context.SetRegisterPlusOffset(*dwarf_reg, 0);
if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags)) if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags))
return false; return false;
} }
return true; return true;
} }
// Move (immediate) writes an immediate value to the destination register. It // Move (immediate) writes an immediate value to the destination register. It
▲ Show 20 Lines • Show All 200 Lines • ▼ Show 20 Lines uint64_t operand2 =
ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + m, 0, &success); ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + m, 0, &success);
if (!success) if (!success)
return false; return false;
// result = operand1 * operand2; // result = operand1 * operand2;
uint64_t result = operand1 * operand2; uint64_t result = operand1 * operand2;
// R[d] = result<31:0>; // R[d] = result<31:0>;
RegisterInfo op1_reg; llvm::Optional<RegisterInfo> op1_reg =
RegisterInfo op2_reg; GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n);
GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n, op1_reg); llvm::Optional<RegisterInfo> op2_reg =
GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + m, op2_reg); GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + m);
EmulateInstruction::Context context; EmulateInstruction::Context context;
context.type = eContextArithmetic; context.type = eContextArithmetic;
context.SetRegisterRegisterOperands(op1_reg, op2_reg); context.SetRegisterRegisterOperands(*op1_reg, *op2_reg);
if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + d, if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + d,
(0x0000ffff & result))) (0x0000ffff & result)))
return false; return false;
// if setflags then // if setflags then
if (setflags) { if (setflags) {
// APSR.N = result<31>; // APSR.N = result<31>;
▲ Show 20 Lines • Show All 184 Lines • ▼ Show 20 Lines if (ConditionPassed(opcode)) {
bool success = false; bool success = false;
const uint32_t pc = ReadCoreReg(PC_REG, &success); const uint32_t pc = ReadCoreReg(PC_REG, &success);
if (!success) if (!success)
return false; return false;
// PC relative immediate load context // PC relative immediate load context
EmulateInstruction::Context context; EmulateInstruction::Context context;
context.type = EmulateInstruction::eContextRegisterPlusOffset; context.type = EmulateInstruction::eContextRegisterPlusOffset;
RegisterInfo pc_reg; llvm::Optional<RegisterInfo> pc_reg =
GetRegisterInfo(eRegisterKindDWARF, dwarf_pc, pc_reg); GetRegisterInfo(eRegisterKindDWARF, dwarf_pc);
context.SetRegisterPlusOffset(pc_reg, 0); context.SetRegisterPlusOffset(*pc_reg, 0);
uint32_t Rt; // the destination register uint32_t Rt; // the destination register
uint32_t imm32; // immediate offset from the PC uint32_t imm32; // immediate offset from the PC
bool add; // +imm32 or -imm32? bool add; // +imm32 or -imm32?
addr_t base; // the base address addr_t base; // the base address
addr_t address; // the PC relative address addr_t address; // the PC relative address
uint32_t data; // the literal data value from the PC relative load uint32_t data; // the literal data value from the PC relative load
switch (encoding) { switch (encoding) {
Show All 14 Lines if (ConditionPassed(opcode)) {
} }
base = Align(pc, 4); base = Align(pc, 4);
if (add) if (add)
address = base + imm32; address = base + imm32;
else else
address = base - imm32; address = base - imm32;
context.SetRegisterPlusOffset(pc_reg, address - base); context.SetRegisterPlusOffset(*pc_reg, address - base);
data = MemURead(context, address, 4, 0, &success); data = MemURead(context, address, 4, 0, &success);
if (!success) if (!success)
return false; return false;
if (Rt == 15) { if (Rt == 15) {
if (Bits32(address, 1, 0) == 0) { if (Bits32(address, 1, 0) == 0) {
// In ARMv5T and above, this is an interworking branch. // In ARMv5T and above, this is an interworking branch.
if (!LoadWritePC(context, data)) if (!LoadWritePC(context, data))
▲ Show 20 Lines • Show All 94 Lines • ▼ Show 20 Lines if (ConditionPassed(opcode)) {
AddWithCarryResult res = AddWithCarry(sp, imm32, 0); AddWithCarryResult res = AddWithCarry(sp, imm32, 0);
EmulateInstruction::Context context; EmulateInstruction::Context context;
if (d == 13) if (d == 13)
context.type = EmulateInstruction::eContextAdjustStackPointer; context.type = EmulateInstruction::eContextAdjustStackPointer;
else else
context.type = EmulateInstruction::eContextRegisterPlusOffset; context.type = EmulateInstruction::eContextRegisterPlusOffset;
RegisterInfo sp_reg; llvm::Optional<RegisterInfo> sp_reg =
GetRegisterInfo(eRegisterKindDWARF, dwarf_sp, sp_reg); GetRegisterInfo(eRegisterKindDWARF, dwarf_sp);
context.SetRegisterPlusOffset(sp_reg, res.result - sp); context.SetRegisterPlusOffset(*sp_reg, res.result - sp);
if (d == 15) { if (d == 15) {
if (!ALUWritePC(context, res.result)) if (!ALUWritePC(context, res.result))
return false; return false;
} else { } else {
// R[d] = result; // R[d] = result;
// if setflags then // if setflags then
// APSR.N = result<31>; // APSR.N = result<31>;
▲ Show 20 Lines • Show All 48 Lines • ▼ Show 20 Lines if (ConditionPassed(opcode)) {
int32_t reg_value = ReadCoreReg(Rm, &success); int32_t reg_value = ReadCoreReg(Rm, &success);
if (!success) if (!success)
return false; return false;
addr_t addr = (int32_t)sp + reg_value; // the adjusted stack pointer value addr_t addr = (int32_t)sp + reg_value; // the adjusted stack pointer value
EmulateInstruction::Context context; EmulateInstruction::Context context;
context.type = eContextArithmetic; context.type = eContextArithmetic;
RegisterInfo sp_reg; llvm::Optional<RegisterInfo> sp_reg =
GetRegisterInfo(eRegisterKindDWARF, dwarf_sp, sp_reg); GetRegisterInfo(eRegisterKindDWARF, dwarf_sp);
llvm::Optional<RegisterInfo> other_reg =
RegisterInfo other_reg; GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + Rm);
GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + Rm, other_reg); context.SetRegisterRegisterOperands(*sp_reg, *other_reg);
context.SetRegisterRegisterOperands(sp_reg, other_reg);
if (!WriteRegisterUnsigned(context, eRegisterKindGeneric, if (!WriteRegisterUnsigned(context, eRegisterKindGeneric,
LLDB_REGNUM_GENERIC_SP, addr)) LLDB_REGNUM_GENERIC_SP, addr))
return false; return false;
} }
return true; return true;
} }
▲ Show 20 Lines • Show All 151 Lines • ▼ Show 20 Lines case eEncodingA1:
return false; return false;
break; break;
default: default:
return false; return false;
} }
addr_t target = ReadCoreReg(Rm, &success); addr_t target = ReadCoreReg(Rm, &success);
if (!success) if (!success)
return false; return false;
RegisterInfo dwarf_reg; llvm::Optional<RegisterInfo> dwarf_reg =
GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + Rm, dwarf_reg); GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + Rm);
context.SetRegister(dwarf_reg); context.SetRegister(*dwarf_reg);
if (!WriteRegisterUnsigned(context, eRegisterKindGeneric, if (!WriteRegisterUnsigned(context, eRegisterKindGeneric,
LLDB_REGNUM_GENERIC_RA, lr)) LLDB_REGNUM_GENERIC_RA, lr))
return false; return false;
if (!BXWritePC(context, target)) if (!BXWritePC(context, target))
return false; return false;
} }
return true; return true;
} }
Show All 27 Lines if (ConditionPassed(opcode)) {
default: default:
return false; return false;
} }
bool success = false; bool success = false;
addr_t target = ReadCoreReg(Rm, &success); addr_t target = ReadCoreReg(Rm, &success);
if (!success) if (!success)
return false; return false;
RegisterInfo dwarf_reg; llvm::Optional<RegisterInfo> dwarf_reg =
GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + Rm, dwarf_reg); GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + Rm);
context.SetRegister(dwarf_reg); context.SetRegister(*dwarf_reg);
if (!BXWritePC(context, target)) if (!BXWritePC(context, target))
return false; return false;
} }
return true; return true;
} }
// Branch and Exchange Jazelle attempts to change to Jazelle state. If the // Branch and Exchange Jazelle attempts to change to Jazelle state. If the
// attempt fails, it branches to an address and instruction set specified by a // attempt fails, it branches to an address and instruction set specified by a
Show All 39 Lines if (ConditionPassed(opcode)) {
default: default:
return false; return false;
} }
bool success = false; bool success = false;
addr_t target = ReadCoreReg(Rm, &success); addr_t target = ReadCoreReg(Rm, &success);
if (!success) if (!success)
return false; return false;
RegisterInfo dwarf_reg; llvm::Optional<RegisterInfo> dwarf_reg =
GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + Rm, dwarf_reg); GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + Rm);
context.SetRegister(dwarf_reg); context.SetRegister(*dwarf_reg);
if (!BXWritePC(context, target)) if (!BXWritePC(context, target))
return false; return false;
} }
return true; return true;
} }
// Set r7 to point to some ip offset. // Set r7 to point to some ip offset.
// SUB (immediate) // SUB (immediate)
Show All 30 Lines if (ConditionPassed(opcode)) {
default: default:
return false; return false;
} }
addr_t ip_offset = imm32; addr_t ip_offset = imm32;
addr_t addr = ip - ip_offset; // the adjusted ip value addr_t addr = ip - ip_offset; // the adjusted ip value
EmulateInstruction::Context context; EmulateInstruction::Context context;
context.type = EmulateInstruction::eContextRegisterPlusOffset; context.type = EmulateInstruction::eContextRegisterPlusOffset;
RegisterInfo dwarf_reg; llvm::Optional<RegisterInfo> dwarf_reg =
GetRegisterInfo(eRegisterKindDWARF, dwarf_r12, dwarf_reg); GetRegisterInfo(eRegisterKindDWARF, dwarf_r12);
context.SetRegisterPlusOffset(dwarf_reg, -ip_offset); context.SetRegisterPlusOffset(*dwarf_reg, -ip_offset);
if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r7, addr)) if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r7, addr))
return false; return false;
} }
return true; return true;
} }
// Set ip to point to some stack offset. // Set ip to point to some stack offset.
Show All 31 Lines if (ConditionPassed(opcode)) {
default: default:
return false; return false;
} }
addr_t sp_offset = imm32; addr_t sp_offset = imm32;
addr_t addr = sp - sp_offset; // the adjusted stack pointer value addr_t addr = sp - sp_offset; // the adjusted stack pointer value
EmulateInstruction::Context context; EmulateInstruction::Context context;
context.type = EmulateInstruction::eContextRegisterPlusOffset; context.type = EmulateInstruction::eContextRegisterPlusOffset;
RegisterInfo dwarf_reg; llvm::Optional<RegisterInfo> dwarf_reg =
GetRegisterInfo(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, dwarf_reg); GetRegisterInfo(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP);
context.SetRegisterPlusOffset(dwarf_reg, -sp_offset); context.SetRegisterPlusOffset(*dwarf_reg, -sp_offset);
if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r12, addr)) if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r12, addr))
return false; return false;
} }
return true; return true;
} }
// This instruction subtracts an immediate value from the SP value, and writes // This instruction subtracts an immediate value from the SP value, and writes
▲ Show 20 Lines • Show All 143 Lines • ▼ Show 20 Lines if (ConditionPassed(opcode)) {
addr_t addr; addr_t addr;
if (index) if (index)
addr = offset_addr; addr = offset_addr;
else else
addr = sp; addr = sp;
EmulateInstruction::Context context; EmulateInstruction::Context context;
context.type = EmulateInstruction::eContextPushRegisterOnStack; context.type = EmulateInstruction::eContextPushRegisterOnStack;
RegisterInfo sp_reg; llvm::Optional<RegisterInfo> sp_reg =
RegisterInfo dwarf_reg; GetRegisterInfo(eRegisterKindDWARF, dwarf_sp);
llvm::Optional<RegisterInfo> dwarf_reg =
GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + Rt);
GetRegisterInfo(eRegisterKindDWARF, dwarf_sp, sp_reg); context.SetRegisterToRegisterPlusOffset(*dwarf_reg, *sp_reg, addr - sp);
GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + Rt, dwarf_reg);
context.SetRegisterToRegisterPlusOffset(dwarf_reg, sp_reg, addr - sp);
if (Rt != 15) { if (Rt != 15) {
uint32_t reg_value = ReadCoreReg(Rt, &success); uint32_t reg_value = ReadCoreReg(Rt, &success);
if (!success) if (!success)
return false; return false;
if (!MemUWrite(context, addr, reg_value, addr_byte_size)) if (!MemUWrite(context, addr, reg_value, addr_byte_size))
return false; return false;
} else { } else {
const uint32_t pc = ReadCoreReg(PC_REG, &success); const uint32_t pc = ReadCoreReg(PC_REG, &success);
▲ Show 20 Lines • Show All 77 Lines • ▼ Show 20 Lines if (ConditionPassed(opcode)) {
uint32_t reg_byte_size = single_regs ? addr_byte_size : addr_byte_size * 2; uint32_t reg_byte_size = single_regs ? addr_byte_size : addr_byte_size * 2;
addr_t sp_offset = imm32; addr_t sp_offset = imm32;
addr_t addr = sp - sp_offset; addr_t addr = sp - sp_offset;
uint32_t i; uint32_t i;
EmulateInstruction::Context context; EmulateInstruction::Context context;
context.type = EmulateInstruction::eContextPushRegisterOnStack; context.type = EmulateInstruction::eContextPushRegisterOnStack;
RegisterInfo dwarf_reg; llvm::Optional<RegisterInfo> sp_reg =
RegisterInfo sp_reg; GetRegisterInfo(eRegisterKindDWARF, dwarf_sp);
GetRegisterInfo(eRegisterKindDWARF, dwarf_sp, sp_reg);
for (i = 0; i < regs; ++i) { for (i = 0; i < regs; ++i) {
GetRegisterInfo(eRegisterKindDWARF, start_reg + d + i, dwarf_reg); llvm::Optional<RegisterInfo> dwarf_reg =
context.SetRegisterToRegisterPlusOffset(dwarf_reg, sp_reg, addr - sp); GetRegisterInfo(eRegisterKindDWARF, start_reg + d + i);
context.SetRegisterToRegisterPlusOffset(*dwarf_reg, *sp_reg, addr - sp);
// uint64_t to accommodate 64-bit registers. // uint64_t to accommodate 64-bit registers.
uint64_t reg_value = ReadRegisterUnsigned(&dwarf_reg, 0, &success); uint64_t reg_value = ReadRegisterUnsigned(&(*dwarf_reg), 0, &success);
if (!success) if (!success)
return false; return false;
if (!MemAWrite(context, addr, reg_value, reg_byte_size)) if (!MemAWrite(context, addr, reg_value, reg_byte_size))
return false; return false;
addr += reg_byte_size; addr += reg_byte_size;
} }
context.type = EmulateInstruction::eContextAdjustStackPointer; context.type = EmulateInstruction::eContextAdjustStackPointer;
▲ Show 20 Lines • Show All 69 Lines • ▼ Show 20 Lines if (ConditionPassed(opcode)) {
addr_t sp_offset = imm32; addr_t sp_offset = imm32;
addr_t addr = sp; addr_t addr = sp;
uint32_t i; uint32_t i;
uint64_t data; // uint64_t to accommodate 64-bit registers. uint64_t data; // uint64_t to accommodate 64-bit registers.
EmulateInstruction::Context context; EmulateInstruction::Context context;
context.type = EmulateInstruction::eContextPopRegisterOffStack; context.type = EmulateInstruction::eContextPopRegisterOffStack;
RegisterInfo dwarf_reg;
RegisterInfo sp_reg;
GetRegisterInfo(eRegisterKindDWARF, dwarf_sp, sp_reg);
for (i = 0; i < regs; ++i) { for (i = 0; i < regs; ++i) {
GetRegisterInfo(eRegisterKindDWARF, start_reg + d + i, dwarf_reg); llvm::Optional<RegisterInfo> dwarf_reg =
GetRegisterInfo(eRegisterKindDWARF, start_reg + d + i);
context.SetAddress(addr); context.SetAddress(addr);
data = MemARead(context, addr, reg_byte_size, 0, &success); data = MemARead(context, addr, reg_byte_size, 0, &success);
if (!success) if (!success)
return false; return false;
if (!WriteRegisterUnsigned(context, &dwarf_reg, data)) if (!WriteRegisterUnsigned(context, &(*dwarf_reg), data))
return false; return false;
addr += reg_byte_size; addr += reg_byte_size;
} }
context.type = EmulateInstruction::eContextAdjustStackPointer; context.type = EmulateInstruction::eContextAdjustStackPointer;
context.SetImmediateSigned(sp_offset); context.SetImmediateSigned(sp_offset);
if (!WriteRegisterUnsigned(context, eRegisterKindGeneric, if (!WriteRegisterUnsigned(context, eRegisterKindGeneric,
▲ Show 20 Lines • Show All 375 Lines • ▼ Show 20 Lines if (ConditionPassed(opcode)) {
uint64_t Rn = uint64_t Rn =
ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + n, 0, &success); ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
if (!success) if (!success)
return false; return false;
//(result, carry, overflow) = AddWithCarry(R[n], imm32, '0'); //(result, carry, overflow) = AddWithCarry(R[n], imm32, '0');
AddWithCarryResult res = AddWithCarry(Rn, imm32, 0); AddWithCarryResult res = AddWithCarry(Rn, imm32, 0);
RegisterInfo reg_n; llvm::Optional<RegisterInfo> reg_n =
GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n, reg_n); GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n);
EmulateInstruction::Context context; EmulateInstruction::Context context;
context.type = eContextArithmetic; context.type = eContextArithmetic;
context.SetRegisterPlusOffset(reg_n, imm32); context.SetRegisterPlusOffset(*reg_n, imm32);
// R[d] = result; // R[d] = result;
// if setflags then // if setflags then
// APSR.N = result<31>; // APSR.N = result<31>;
// APSR.Z = IsZeroBit(result); // APSR.Z = IsZeroBit(result);
// APSR.C = carry; // APSR.C = carry;
// APSR.V = overflow; // APSR.V = overflow;
if (!WriteCoreRegOptionalFlags(context, res.result, d, setflags, if (!WriteCoreRegOptionalFlags(context, res.result, d, setflags,
▲ Show 20 Lines • Show All 52 Lines • ▼ Show 20 Lines if (ConditionPassed(opcode)) {
EmulateInstruction::Context context; EmulateInstruction::Context context;
if (Rd == 13) if (Rd == 13)
context.type = EmulateInstruction::eContextAdjustStackPointer; context.type = EmulateInstruction::eContextAdjustStackPointer;
else if (Rd == GetFramePointerRegisterNumber()) else if (Rd == GetFramePointerRegisterNumber())
context.type = EmulateInstruction::eContextSetFramePointer; context.type = EmulateInstruction::eContextSetFramePointer;
else else
context.type = EmulateInstruction::eContextRegisterPlusOffset; context.type = EmulateInstruction::eContextRegisterPlusOffset;
RegisterInfo dwarf_reg; llvm::Optional<RegisterInfo> dwarf_reg =
GetRegisterInfo(eRegisterKindDWARF, Rn, dwarf_reg); GetRegisterInfo(eRegisterKindDWARF, Rn);
context.SetRegisterPlusOffset(dwarf_reg, imm32); context.SetRegisterPlusOffset(*dwarf_reg, imm32);
if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags, if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags,
res.carry_out, res.overflow)) res.carry_out, res.overflow))
return false; return false;
} }
return true; return true;
} }
▲ Show 20 Lines • Show All 69 Lines • ▼ Show 20 Lines if (ConditionPassed(opcode)) {
uint32_t shifted = Shift(val2, shift_t, shift_n, APSR_C, &success); uint32_t shifted = Shift(val2, shift_t, shift_n, APSR_C, &success);
if (!success) if (!success)
return false; return false;
AddWithCarryResult res = AddWithCarry(val1, shifted, 0); AddWithCarryResult res = AddWithCarry(val1, shifted, 0);
EmulateInstruction::Context context; EmulateInstruction::Context context;
context.type = eContextArithmetic; context.type = eContextArithmetic;
RegisterInfo op1_reg; llvm::Optional<RegisterInfo> op1_reg =
RegisterInfo op2_reg; GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + Rn);
GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + Rn, op1_reg); llvm::Optional<RegisterInfo> op2_reg =
GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + Rm, op2_reg); GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + Rm);
context.SetRegisterRegisterOperands(op1_reg, op2_reg); context.SetRegisterRegisterOperands(*op1_reg, *op2_reg);
if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags, if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags,
res.carry_out, res.overflow)) res.carry_out, res.overflow))
return false; return false;
} }
return true; return true;
} }
▲ Show 20 Lines • Show All 690 Lines • ▼ Show 20 Lines if (ConditionPassed(opcode)) {
int32_t offset = 0; int32_t offset = 0;
const addr_t base_address = const addr_t base_address =
ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + n, 0, &success); ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
if (!success) if (!success)
return false; return false;
EmulateInstruction::Context context; EmulateInstruction::Context context;
context.type = EmulateInstruction::eContextRegisterPlusOffset; context.type = EmulateInstruction::eContextRegisterPlusOffset;
RegisterInfo dwarf_reg; llvm::Optional<RegisterInfo> dwarf_reg =
GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n, dwarf_reg); GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n);
context.SetRegisterPlusOffset(dwarf_reg, offset); context.SetRegisterPlusOffset(*dwarf_reg, offset);
for (int i = 0; i < 14; ++i) { for (int i = 0; i < 14; ++i) {
if (BitIsSet(registers, i)) { if (BitIsSet(registers, i)) {
context.type = EmulateInstruction::eContextRegisterPlusOffset; context.type = EmulateInstruction::eContextRegisterPlusOffset;
context.SetRegisterPlusOffset(dwarf_reg, offset); context.SetRegisterPlusOffset(*dwarf_reg, offset);
if (wback && (n == 13)) // Pop Instruction if (wback && (n == 13)) // Pop Instruction
{ {
context.type = EmulateInstruction::eContextPopRegisterOffStack; context.type = EmulateInstruction::eContextPopRegisterOffStack;
context.SetAddress(base_address + offset); context.SetAddress(base_address + offset);
} }
// R[i] = MemA [address, 4]; address = address + 4; // R[i] = MemA [address, 4]; address = address + 4;
uint32_t data = MemARead(context, base_address + offset, addr_byte_size, uint32_t data = MemARead(context, base_address + offset, addr_byte_size,
0, &success); 0, &success);
if (!success) if (!success)
return false; return false;
if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + i, if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + i,
data)) data))
return false; return false;
offset += addr_byte_size; offset += addr_byte_size;
} }
} }
if (BitIsSet(registers, 15)) { if (BitIsSet(registers, 15)) {
// LoadWritePC (MemA [address, 4]); // LoadWritePC (MemA [address, 4]);
context.type = EmulateInstruction::eContextRegisterPlusOffset; context.type = EmulateInstruction::eContextRegisterPlusOffset;
context.SetRegisterPlusOffset(dwarf_reg, offset); context.SetRegisterPlusOffset(*dwarf_reg, offset);
uint32_t data = uint32_t data =
MemARead(context, base_address + offset, addr_byte_size, 0, &success); MemARead(context, base_address + offset, addr_byte_size, 0, &success);
if (!success) if (!success)
return false; return false;
// In ARMv5T and above, this is an interworking branch. // In ARMv5T and above, this is an interworking branch.
if (!LoadWritePC(context, data)) if (!LoadWritePC(context, data))
return false; return false;
} }
if (wback && BitIsClear(registers, n)) { if (wback && BitIsClear(registers, n)) {
// R[n] = R[n] + 4 * BitCount (registers) // R[n] = R[n] + 4 * BitCount (registers)
int32_t offset = addr_byte_size * BitCount(registers); int32_t offset = addr_byte_size * BitCount(registers);
context.type = EmulateInstruction::eContextAdjustBaseRegister; context.type = EmulateInstruction::eContextAdjustBaseRegister;
context.SetRegisterPlusOffset(dwarf_reg, offset); context.SetRegisterPlusOffset(*dwarf_reg, offset);
if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + n, if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + n,
base_address + offset)) base_address + offset))
return false; return false;
} }
if (wback && BitIsSet(registers, n)) if (wback && BitIsSet(registers, n))
// R[n] bits(32) UNKNOWN; // R[n] bits(32) UNKNOWN;
return WriteBits32Unknown(n); return WriteBits32Unknown(n);
▲ Show 20 Lines • Show All 58 Lines • ▼ Show 20 Lines if (ConditionPassed(opcode)) {
if (!success) if (!success)
return false; return false;
addr_t address = addr_t address =
Rn - (addr_byte_size * BitCount(registers)) + addr_byte_size; Rn - (addr_byte_size * BitCount(registers)) + addr_byte_size;
EmulateInstruction::Context context; EmulateInstruction::Context context;
context.type = EmulateInstruction::eContextRegisterPlusOffset; context.type = EmulateInstruction::eContextRegisterPlusOffset;
RegisterInfo dwarf_reg; llvm::Optional<RegisterInfo> dwarf_reg =
GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n, dwarf_reg); GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n);
context.SetRegisterPlusOffset(dwarf_reg, offset); context.SetRegisterPlusOffset(*dwarf_reg, offset);
// for i = 0 to 14 // for i = 0 to 14
for (int i = 0; i < 14; ++i) { for (int i = 0; i < 14; ++i) {
// if registers<i> == '1' then // if registers<i> == '1' then
if (BitIsSet(registers, i)) { if (BitIsSet(registers, i)) {
// R[i] = MemA[address,4]; address = address + 4; // R[i] = MemA[address,4]; address = address + 4;
context.SetRegisterPlusOffset(dwarf_reg, Rn - (address + offset)); context.SetRegisterPlusOffset(*dwarf_reg, Rn - (address + offset));
uint32_t data = uint32_t data =
MemARead(context, address + offset, addr_byte_size, 0, &success); MemARead(context, address + offset, addr_byte_size, 0, &success);
if (!success) if (!success)
return false; return false;
if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + i, if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + i,
data)) data))
return false; return false;
offset += addr_byte_size; offset += addr_byte_size;
} }
} }
// if registers<15> == '1' then // if registers<15> == '1' then
// LoadWritePC(MemA[address,4]); // LoadWritePC(MemA[address,4]);
if (BitIsSet(registers, 15)) { if (BitIsSet(registers, 15)) {
context.SetRegisterPlusOffset(dwarf_reg, offset); context.SetRegisterPlusOffset(*dwarf_reg, offset);
uint32_t data = uint32_t data =
MemARead(context, address + offset, addr_byte_size, 0, &success); MemARead(context, address + offset, addr_byte_size, 0, &success);
if (!success) if (!success)
return false; return false;
// In ARMv5T and above, this is an interworking branch. // In ARMv5T and above, this is an interworking branch.
if (!LoadWritePC(context, data)) if (!LoadWritePC(context, data))
return false; return false;
} }
▲ Show 20 Lines • Show All 95 Lines • ▼ Show 20 Lines addr_t Rn =
ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + n, 0, &success); ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
if (!success) if (!success)
return false; return false;
addr_t address = Rn - (addr_byte_size * BitCount(registers)); addr_t address = Rn - (addr_byte_size * BitCount(registers));
EmulateInstruction::Context context; EmulateInstruction::Context context;
context.type = EmulateInstruction::eContextRegisterPlusOffset; context.type = EmulateInstruction::eContextRegisterPlusOffset;
RegisterInfo dwarf_reg; llvm::Optional<RegisterInfo> dwarf_reg =
GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n, dwarf_reg); GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n);
context.SetRegisterPlusOffset(dwarf_reg, Rn - address); context.SetRegisterPlusOffset(*dwarf_reg, Rn - address);
for (int i = 0; i < 14; ++i) { for (int i = 0; i < 14; ++i) {
if (BitIsSet(registers, i)) { if (BitIsSet(registers, i)) {
// R[i] = MemA[address,4]; address = address + 4; // R[i] = MemA[address,4]; address = address + 4;
context.SetRegisterPlusOffset(dwarf_reg, Rn - (address + offset)); context.SetRegisterPlusOffset(*dwarf_reg, Rn - (address + offset));
uint32_t data = uint32_t data =
MemARead(context, address + offset, addr_byte_size, 0, &success); MemARead(context, address + offset, addr_byte_size, 0, &success);
if (!success) if (!success)
return false; return false;
if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + i, if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + i,
data)) data))
return false; return false;
offset += addr_byte_size; offset += addr_byte_size;
} }
} }
// if registers<15> == '1' then // if registers<15> == '1' then
// LoadWritePC(MemA[address,4]); // LoadWritePC(MemA[address,4]);
if (BitIsSet(registers, 15)) { if (BitIsSet(registers, 15)) {
context.SetRegisterPlusOffset(dwarf_reg, offset); context.SetRegisterPlusOffset(*dwarf_reg, offset);
uint32_t data = uint32_t data =
MemARead(context, address + offset, addr_byte_size, 0, &success); MemARead(context, address + offset, addr_byte_size, 0, &success);
if (!success) if (!success)
return false; return false;
// In ARMv5T and above, this is an interworking branch. // In ARMv5T and above, this is an interworking branch.
if (!LoadWritePC(context, data)) if (!LoadWritePC(context, data))
return false; return false;
} }
▲ Show 20 Lines • Show All 70 Lines • ▼ Show 20 Lines if (ConditionPassed(opcode)) {
if (!success) if (!success)
return false; return false;
addr_t address = Rn + addr_byte_size; addr_t address = Rn + addr_byte_size;
EmulateInstruction::Context context; EmulateInstruction::Context context;
context.type = EmulateInstruction::eContextRegisterPlusOffset; context.type = EmulateInstruction::eContextRegisterPlusOffset;
RegisterInfo dwarf_reg; llvm::Optional<RegisterInfo> dwarf_reg =
GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n, dwarf_reg); GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n);
context.SetRegisterPlusOffset(dwarf_reg, offset); context.SetRegisterPlusOffset(*dwarf_reg, offset);
for (int i = 0; i < 14; ++i) { for (int i = 0; i < 14; ++i) {
if (BitIsSet(registers, i)) { if (BitIsSet(registers, i)) {
// R[i] = MemA[address,4]; address = address + 4; // R[i] = MemA[address,4]; address = address + 4;
context.SetRegisterPlusOffset(dwarf_reg, offset + addr_byte_size); context.SetRegisterPlusOffset(*dwarf_reg, offset + addr_byte_size);
uint32_t data = uint32_t data =
MemARead(context, address + offset, addr_byte_size, 0, &success); MemARead(context, address + offset, addr_byte_size, 0, &success);
if (!success) if (!success)
return false; return false;
if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + i, if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + i,
data)) data))
return false; return false;
offset += addr_byte_size; offset += addr_byte_size;
} }
} }
// if registers<15> == '1' then // if registers<15> == '1' then
// LoadWritePC(MemA[address,4]); // LoadWritePC(MemA[address,4]);
if (BitIsSet(registers, 15)) { if (BitIsSet(registers, 15)) {
context.SetRegisterPlusOffset(dwarf_reg, offset); context.SetRegisterPlusOffset(*dwarf_reg, offset);
uint32_t data = uint32_t data =
MemARead(context, address + offset, addr_byte_size, 0, &success); MemARead(context, address + offset, addr_byte_size, 0, &success);
if (!success) if (!success)
return false; return false;
// In ARMv5T and above, this is an interworking branch. // In ARMv5T and above, this is an interworking branch.
if (!LoadWritePC(context, data)) if (!LoadWritePC(context, data))
return false; return false;
} }
▲ Show 20 Lines • Show All 128 Lines • ▼ Show 20 Lines if (!success)
return false; return false;
if (add) if (add)
offset_addr = base + imm32; offset_addr = base + imm32;
else else
offset_addr = base - imm32; offset_addr = base - imm32;
address = (index ? offset_addr : base); address = (index ? offset_addr : base);
RegisterInfo base_reg; llvm::Optional<RegisterInfo> base_reg =
GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + Rn, base_reg); GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + Rn);
if (wback) { if (wback) {
EmulateInstruction::Context ctx; EmulateInstruction::Context ctx;
if (Rn == 13) { if (Rn == 13) {
ctx.type = eContextAdjustStackPointer; ctx.type = eContextAdjustStackPointer;
ctx.SetImmediateSigned((int32_t)(offset_addr - base)); ctx.SetImmediateSigned((int32_t)(offset_addr - base));
} else if (Rn == GetFramePointerRegisterNumber()) { } else if (Rn == GetFramePointerRegisterNumber()) {
ctx.type = eContextSetFramePointer; ctx.type = eContextSetFramePointer;
ctx.SetRegisterPlusOffset(base_reg, (int32_t)(offset_addr - base)); ctx.SetRegisterPlusOffset(*base_reg, (int32_t)(offset_addr - base));
} else { } else {
ctx.type = EmulateInstruction::eContextAdjustBaseRegister; ctx.type = EmulateInstruction::eContextAdjustBaseRegister;
ctx.SetRegisterPlusOffset(base_reg, (int32_t)(offset_addr - base)); ctx.SetRegisterPlusOffset(*base_reg, (int32_t)(offset_addr - base));
} }
if (!WriteRegisterUnsigned(ctx, eRegisterKindDWARF, dwarf_r0 + Rn, if (!WriteRegisterUnsigned(ctx, eRegisterKindDWARF, dwarf_r0 + Rn,
offset_addr)) offset_addr))
return false; return false;
} }
// Prepare to write to the Rt register. // Prepare to write to the Rt register.
EmulateInstruction::Context context; EmulateInstruction::Context context;
context.type = EmulateInstruction::eContextRegisterLoad; context.type = EmulateInstruction::eContextRegisterLoad;
context.SetRegisterPlusOffset(base_reg, (int32_t)(offset_addr - base)); context.SetRegisterPlusOffset(*base_reg, (int32_t)(offset_addr - base));
// Read memory from the address. // Read memory from the address.
data = MemURead(context, address, 4, 0, &success); data = MemURead(context, address, 4, 0, &success);
if (!success) if (!success)
return false; return false;
if (Rt == 15) { if (Rt == 15) {
if (Bits32(address, 1, 0) == 0) { if (Bits32(address, 1, 0) == 0) {
▲ Show 20 Lines • Show All 96 Lines • ▼ Show 20 Lines if (ConditionPassed(opcode)) {
int32_t offset = 0; int32_t offset = 0;
const addr_t address = const addr_t address =
ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + n, 0, &success); ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
if (!success) if (!success)
return false; return false;
EmulateInstruction::Context context; EmulateInstruction::Context context;
context.type = EmulateInstruction::eContextRegisterStore; context.type = EmulateInstruction::eContextRegisterStore;
RegisterInfo base_reg; llvm::Optional<RegisterInfo> base_reg =
GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n, base_reg); GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n);
// for i = 0 to 14 // for i = 0 to 14
uint32_t lowest_set_bit = 14; uint32_t lowest_set_bit = 14;
for (uint32_t i = 0; i < 14; ++i) { for (uint32_t i = 0; i < 14; ++i) {
// if registers<i> == '1' then // if registers<i> == '1' then
if (BitIsSet(registers, i)) { if (BitIsSet(registers, i)) {
if (i < lowest_set_bit) if (i < lowest_set_bit)
lowest_set_bit = i; lowest_set_bit = i;
// if i == n && wback && i != LowestSetBit(registers) then // if i == n && wback && i != LowestSetBit(registers) then
if ((i == n) && wback && (i != lowest_set_bit)) if ((i == n) && wback && (i != lowest_set_bit))
// MemA[address,4] = bits(32) UNKNOWN; // Only possible for encodings // MemA[address,4] = bits(32) UNKNOWN; // Only possible for encodings
// T1 and A1 // T1 and A1
WriteBits32UnknownToMemory(address + offset); WriteBits32UnknownToMemory(address + offset);
else { else {
// MemA[address,4] = R[i]; // MemA[address,4] = R[i];
uint32_t data = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + i, uint32_t data = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + i,
0, &success); 0, &success);
if (!success) if (!success)
return false; return false;
RegisterInfo data_reg; llvm::Optional<RegisterInfo> data_reg =
GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + i, data_reg); GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + i);
context.SetRegisterToRegisterPlusOffset(data_reg, base_reg, offset); context.SetRegisterToRegisterPlusOffset(*data_reg, *base_reg, offset);
if (!MemAWrite(context, address + offset, data, addr_byte_size)) if (!MemAWrite(context, address + offset, data, addr_byte_size))
return false; return false;
} }
// address = address + 4; // address = address + 4;
offset += addr_byte_size; offset += addr_byte_size;
} }
} }
// if registers<15> == '1' then // Only possible for encoding A1 // if registers<15> == '1' then // Only possible for encoding A1
// MemA[address,4] = PCStoreValue(); // MemA[address,4] = PCStoreValue();
if (BitIsSet(registers, 15)) { if (BitIsSet(registers, 15)) {
RegisterInfo pc_reg; llvm::Optional<RegisterInfo> pc_reg =
GetRegisterInfo(eRegisterKindDWARF, dwarf_pc, pc_reg); GetRegisterInfo(eRegisterKindDWARF, dwarf_pc);
context.SetRegisterPlusOffset(pc_reg, 8); context.SetRegisterPlusOffset(*pc_reg, 8);
const uint32_t pc = ReadCoreReg(PC_REG, &success); const uint32_t pc = ReadCoreReg(PC_REG, &success);
if (!success) if (!success)
return false; return false;
if (!MemAWrite(context, address + offset, pc, addr_byte_size)) if (!MemAWrite(context, address + offset, pc, addr_byte_size))
return false; return false;
} }
▲ Show 20 Lines • Show All 66 Lines • ▼ Show 20 Lines if (ConditionPassed(opcode)) {
addr_t Rn = ReadCoreReg(n, &success); addr_t Rn = ReadCoreReg(n, &success);
if (!success) if (!success)
return false; return false;
addr_t address = Rn - (addr_byte_size * BitCount(registers)) + 4; addr_t address = Rn - (addr_byte_size * BitCount(registers)) + 4;
EmulateInstruction::Context context; EmulateInstruction::Context context;
context.type = EmulateInstruction::eContextRegisterStore; context.type = EmulateInstruction::eContextRegisterStore;
RegisterInfo base_reg; llvm::Optional<RegisterInfo> base_reg =
GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n, base_reg); GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n);
// for i = 0 to 14 // for i = 0 to 14
uint32_t lowest_bit_set = 14; uint32_t lowest_bit_set = 14;
for (uint32_t i = 0; i < 14; ++i) { for (uint32_t i = 0; i < 14; ++i) {
// if registers<i> == '1' then // if registers<i> == '1' then
if (BitIsSet(registers, i)) { if (BitIsSet(registers, i)) {
if (i < lowest_bit_set) if (i < lowest_bit_set)
lowest_bit_set = i; lowest_bit_set = i;
// if i == n && wback && i != LowestSetBit(registers) then // if i == n && wback && i != LowestSetBit(registers) then
if ((i == n) && wback && (i != lowest_bit_set)) if ((i == n) && wback && (i != lowest_bit_set))
// MemA[address,4] = bits(32) UNKNOWN; // MemA[address,4] = bits(32) UNKNOWN;
WriteBits32UnknownToMemory(address + offset); WriteBits32UnknownToMemory(address + offset);
else { else {
// MemA[address,4] = R[i]; // MemA[address,4] = R[i];
uint32_t data = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + i, uint32_t data = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + i,
0, &success); 0, &success);
if (!success) if (!success)
return false; return false;
RegisterInfo data_reg; llvm::Optional<RegisterInfo> data_reg =
GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + i, data_reg); GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + i);
context.SetRegisterToRegisterPlusOffset(data_reg, base_reg, context.SetRegisterToRegisterPlusOffset(*data_reg, *base_reg,
Rn - (address + offset)); Rn - (address + offset));
if (!MemAWrite(context, address + offset, data, addr_byte_size)) if (!MemAWrite(context, address + offset, data, addr_byte_size))
return false; return false;
} }
// address = address + 4; // address = address + 4;
offset += addr_byte_size; offset += addr_byte_size;
} }
} }
// if registers<15> == '1' then // if registers<15> == '1' then
// MemA[address,4] = PCStoreValue(); // MemA[address,4] = PCStoreValue();
if (BitIsSet(registers, 15)) { if (BitIsSet(registers, 15)) {
RegisterInfo pc_reg; llvm::Optional<RegisterInfo> pc_reg =
GetRegisterInfo(eRegisterKindDWARF, dwarf_pc, pc_reg); GetRegisterInfo(eRegisterKindDWARF, dwarf_pc);
context.SetRegisterPlusOffset(pc_reg, 8); context.SetRegisterPlusOffset(*pc_reg, 8);
const uint32_t pc = ReadCoreReg(PC_REG, &success); const uint32_t pc = ReadCoreReg(PC_REG, &success);
if (!success) if (!success)
return false; return false;
if (!MemAWrite(context, address + offset, pc, addr_byte_size)) if (!MemAWrite(context, address + offset, pc, addr_byte_size))
return false; return false;
} }
▲ Show 20 Lines • Show All 92 Lines • ▼ Show 20 Lines addr_t Rn =
ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + n, 0, &success); ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
if (!success) if (!success)
return false; return false;
addr_t address = Rn - (addr_byte_size * BitCount(registers)); addr_t address = Rn - (addr_byte_size * BitCount(registers));
EmulateInstruction::Context context; EmulateInstruction::Context context;
context.type = EmulateInstruction::eContextRegisterStore; context.type = EmulateInstruction::eContextRegisterStore;
RegisterInfo base_reg; llvm::Optional<RegisterInfo> base_reg =
GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n, base_reg); GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n);
// for i = 0 to 14 // for i = 0 to 14
uint32_t lowest_set_bit = 14; uint32_t lowest_set_bit = 14;
for (uint32_t i = 0; i < 14; ++i) { for (uint32_t i = 0; i < 14; ++i) {
// if registers<i> == '1' then // if registers<i> == '1' then
if (BitIsSet(registers, i)) { if (BitIsSet(registers, i)) {
if (i < lowest_set_bit) if (i < lowest_set_bit)
lowest_set_bit = i; lowest_set_bit = i;
// if i == n && wback && i != LowestSetBit(registers) then // if i == n && wback && i != LowestSetBit(registers) then
if ((i == n) && wback && (i != lowest_set_bit)) if ((i == n) && wback && (i != lowest_set_bit))
// MemA[address,4] = bits(32) UNKNOWN; // Only possible for encoding // MemA[address,4] = bits(32) UNKNOWN; // Only possible for encoding
// A1 // A1
WriteBits32UnknownToMemory(address + offset); WriteBits32UnknownToMemory(address + offset);
else { else {
// MemA[address,4] = R[i]; // MemA[address,4] = R[i];
uint32_t data = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + i, uint32_t data = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + i,
0, &success); 0, &success);
if (!success) if (!success)
return false; return false;
RegisterInfo data_reg; llvm::Optional<RegisterInfo> data_reg =
GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + i, data_reg); GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + i);
context.SetRegisterToRegisterPlusOffset(data_reg, base_reg, context.SetRegisterToRegisterPlusOffset(*data_reg, *base_reg,
Rn - (address + offset)); Rn - (address + offset));
if (!MemAWrite(context, address + offset, data, addr_byte_size)) if (!MemAWrite(context, address + offset, data, addr_byte_size))
return false; return false;
} }
// address = address + 4; // address = address + 4;
offset += addr_byte_size; offset += addr_byte_size;
} }
} }
// if registers<15> == '1' then // Only possible for encoding A1 // if registers<15> == '1' then // Only possible for encoding A1
// MemA[address,4] = PCStoreValue(); // MemA[address,4] = PCStoreValue();
if (BitIsSet(registers, 15)) { if (BitIsSet(registers, 15)) {
RegisterInfo pc_reg; llvm::Optional<RegisterInfo> pc_reg =
GetRegisterInfo(eRegisterKindDWARF, dwarf_pc, pc_reg); GetRegisterInfo(eRegisterKindDWARF, dwarf_pc);
context.SetRegisterPlusOffset(pc_reg, 8); context.SetRegisterPlusOffset(*pc_reg, 8);
const uint32_t pc = ReadCoreReg(PC_REG, &success); const uint32_t pc = ReadCoreReg(PC_REG, &success);
if (!success) if (!success)
return false; return false;
if (!MemAWrite(context, address + offset, pc, addr_byte_size)) if (!MemAWrite(context, address + offset, pc, addr_byte_size))
return false; return false;
} }
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addr_t Rn = ReadCoreReg(n, &success); addr_t Rn = ReadCoreReg(n, &success);
if (!success) if (!success)
return false; return false;
addr_t address = Rn + addr_byte_size; addr_t address = Rn + addr_byte_size;
EmulateInstruction::Context context; EmulateInstruction::Context context;
context.type = EmulateInstruction::eContextRegisterStore; context.type = EmulateInstruction::eContextRegisterStore;
RegisterInfo base_reg; llvm::Optional<RegisterInfo> base_reg =
GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n, base_reg); GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n);
uint32_t lowest_set_bit = 14; uint32_t lowest_set_bit = 14;
// for i = 0 to 14 // for i = 0 to 14
for (uint32_t i = 0; i < 14; ++i) { for (uint32_t i = 0; i < 14; ++i) {
// if registers<i> == '1' then // if registers<i> == '1' then
if (BitIsSet(registers, i)) { if (BitIsSet(registers, i)) {
if (i < lowest_set_bit) if (i < lowest_set_bit)
lowest_set_bit = i; lowest_set_bit = i;
// if i == n && wback && i != LowestSetBit(registers) then // if i == n && wback && i != LowestSetBit(registers) then
if ((i == n) && wback && (i != lowest_set_bit)) if ((i == n) && wback && (i != lowest_set_bit))
// MemA[address,4] = bits(32) UNKNOWN; // MemA[address,4] = bits(32) UNKNOWN;
WriteBits32UnknownToMemory(address + offset); WriteBits32UnknownToMemory(address + offset);
// else // else
else { else {
// MemA[address,4] = R[i]; // MemA[address,4] = R[i];
uint32_t data = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + i, uint32_t data = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + i,
0, &success); 0, &success);
if (!success) if (!success)
return false; return false;
RegisterInfo data_reg; llvm::Optional<RegisterInfo> data_reg =
GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + i, data_reg); GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + i);
context.SetRegisterToRegisterPlusOffset(data_reg, base_reg, context.SetRegisterToRegisterPlusOffset(*data_reg, *base_reg,
offset + addr_byte_size); offset + addr_byte_size);
if (!MemAWrite(context, address + offset, data, addr_byte_size)) if (!MemAWrite(context, address + offset, data, addr_byte_size))
return false; return false;
} }
// address = address + 4; // address = address + 4;
offset += addr_byte_size; offset += addr_byte_size;
} }
} }
// if registers<15> == '1' then // if registers<15> == '1' then
// MemA[address,4] = PCStoreValue(); // MemA[address,4] = PCStoreValue();
if (BitIsSet(registers, 15)) { if (BitIsSet(registers, 15)) {
RegisterInfo pc_reg; llvm::Optional<RegisterInfo> pc_reg =
GetRegisterInfo(eRegisterKindDWARF, dwarf_pc, pc_reg); GetRegisterInfo(eRegisterKindDWARF, dwarf_pc);
context.SetRegisterPlusOffset(pc_reg, 8); context.SetRegisterPlusOffset(*pc_reg, 8);
const uint32_t pc = ReadCoreReg(PC_REG, &success); const uint32_t pc = ReadCoreReg(PC_REG, &success);
if (!success) if (!success)
return false; return false;
if (!MemAWrite(context, address + offset, pc, addr_byte_size)) if (!MemAWrite(context, address + offset, pc, addr_byte_size))
return false; return false;
} }
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address = base_address; address = base_address;
EmulateInstruction::Context context; EmulateInstruction::Context context;
if (n == 13) if (n == 13)
context.type = eContextPushRegisterOnStack; context.type = eContextPushRegisterOnStack;
else else
context.type = eContextRegisterStore; context.type = eContextRegisterStore;
RegisterInfo base_reg; llvm::Optional<RegisterInfo> base_reg =
GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n, base_reg); GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n);
// if UnalignedSupport() || address<1:0> == '00' then // if UnalignedSupport() || address<1:0> == '00' then
if (UnalignedSupport() || if (UnalignedSupport() ||
(BitIsClear(address, 1) && BitIsClear(address, 0))) { (BitIsClear(address, 1) && BitIsClear(address, 0))) {
// MemU[address,4] = R[t]; // MemU[address,4] = R[t];
uint32_t data = uint32_t data =
ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + t, 0, &success); ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + t, 0, &success);
if (!success) if (!success)
return false; return false;
RegisterInfo data_reg; llvm::Optional<RegisterInfo> data_reg =
GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + t, data_reg); GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + t);
int32_t offset = address - base_address; int32_t offset = address - base_address;
context.SetRegisterToRegisterPlusOffset(data_reg, base_reg, offset); context.SetRegisterToRegisterPlusOffset(*data_reg, *base_reg, offset);
if (!MemUWrite(context, address, data, addr_byte_size)) if (!MemUWrite(context, address, data, addr_byte_size))
return false; return false;
} else { } else {
// MemU[address,4] = bits(32) UNKNOWN; // MemU[address,4] = bits(32) UNKNOWN;
WriteBits32UnknownToMemory(address); WriteBits32UnknownToMemory(address);
} }
// if wback then R[n] = offset_addr; // if wback then R[n] = offset_addr;
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// if UnalignedSupport() || address<1:0> == '00' || CurrentInstrSet() == // if UnalignedSupport() || address<1:0> == '00' || CurrentInstrSet() ==
// InstrSet_ARM then // InstrSet_ARM then
if (UnalignedSupport() || if (UnalignedSupport() ||
(BitIsClear(address, 1) && BitIsClear(address, 0)) || (BitIsClear(address, 1) && BitIsClear(address, 0)) ||
CurrentInstrSet() == eModeARM) { CurrentInstrSet() == eModeARM) {
// MemU[address,4] = data; // MemU[address,4] = data;
RegisterInfo base_reg; llvm::Optional<RegisterInfo> base_reg =
GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n, base_reg); GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n);
llvm::Optional<RegisterInfo> data_reg =
RegisterInfo data_reg; GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + t);
GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + t, data_reg);
context.SetRegisterToRegisterPlusOffset(data_reg, base_reg, context.SetRegisterToRegisterPlusOffset(*data_reg, *base_reg,
address - base_address); address - base_address);
if (!MemUWrite(context, address, data, addr_byte_size)) if (!MemUWrite(context, address, data, addr_byte_size))
return false; return false;
} else } else
// MemU[address,4] = bits(32) UNKNOWN; // MemU[address,4] = bits(32) UNKNOWN;
WriteBits32UnknownToMemory(address); WriteBits32UnknownToMemory(address);
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// address = if index then offset_addr else R[n]; // address = if index then offset_addr else R[n];
if (index) if (index)
address = offset_addr; address = offset_addr;
else else
address = base_address; address = base_address;
// MemU[address,1] = R[t]<7:0> // MemU[address,1] = R[t]<7:0>
RegisterInfo base_reg; llvm::Optional<RegisterInfo> base_reg =
GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n, base_reg); GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n);
llvm::Optional<RegisterInfo> data_reg =
RegisterInfo data_reg; GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + t);
GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + t, data_reg);
EmulateInstruction::Context context; EmulateInstruction::Context context;
context.type = eContextRegisterStore; context.type = eContextRegisterStore;
context.SetRegisterToRegisterPlusOffset(data_reg, base_reg, context.SetRegisterToRegisterPlusOffset(*data_reg, *base_reg,
address - base_address); address - base_address);
uint32_t data = uint32_t data =
ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + t, 0, &success); ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + t, 0, &success);
if (!success) if (!success)
return false; return false;
data = Bits32(data, 7, 0); data = Bits32(data, 7, 0);
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addr_t address; addr_t address;
if (index) if (index)
address = offset_addr; address = offset_addr;
else else
address = Rn; address = Rn;
EmulateInstruction::Context context; EmulateInstruction::Context context;
context.type = eContextRegisterStore; context.type = eContextRegisterStore;
RegisterInfo base_reg;
GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n, base_reg);
RegisterInfo offset_reg;
GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + m, offset_reg);
// if UnalignedSupport() || address<0> == '0' then // if UnalignedSupport() || address<0> == '0' then
if (UnalignedSupport() || BitIsClear(address, 0)) { if (UnalignedSupport() || BitIsClear(address, 0)) {
// MemU[address,2] = R[t]<15:0>; // MemU[address,2] = R[t]<15:0>;
uint32_t Rt = ReadCoreReg(t, &success); uint32_t Rt = ReadCoreReg(t, &success);
if (!success) if (!success)
return false; return false;
EmulateInstruction::Context context; EmulateInstruction::Context context;
context.type = eContextRegisterStore; context.type = eContextRegisterStore;
RegisterInfo base_reg; llvm::Optional<RegisterInfo> base_reg =
GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n, base_reg); GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n);
RegisterInfo offset_reg; llvm::Optional<RegisterInfo> offset_reg =
GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + m, offset_reg); GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + m);
RegisterInfo data_reg; llvm::Optional<RegisterInfo> data_reg =
GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + t, data_reg); GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + t);
context.SetRegisterToRegisterPlusIndirectOffset(base_reg, offset_reg, context.SetRegisterToRegisterPlusIndirectOffset(*base_reg, *offset_reg,
data_reg); *data_reg);
if (!MemUWrite(context, address, Bits32(Rt, 15, 0), 2)) if (!MemUWrite(context, address, Bits32(Rt, 15, 0), 2))
return false; return false;
} else // Can only occur before ARMv7 } else // Can only occur before ARMv7
{ {
// MemU[address,2] = bits(16) UNKNOWN; // MemU[address,2] = bits(16) UNKNOWN;
} }
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// address = if index then offset_addr else R[n]; // address = if index then offset_addr else R[n];
if (index) if (index)
address = offset_addr; address = offset_addr;
else else
address = base_address; address = base_address;
// data = MemU[address,4]; // data = MemU[address,4];
RegisterInfo base_reg; llvm::Optional<RegisterInfo> base_reg =
GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n, base_reg); GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n);
EmulateInstruction::Context context; EmulateInstruction::Context context;
context.type = eContextRegisterLoad; context.type = eContextRegisterLoad;
context.SetRegisterPlusOffset(base_reg, address - base_address); context.SetRegisterPlusOffset(*base_reg, address - base_address);
uint64_t data = MemURead(context, address, addr_byte_size, 0, &success); uint64_t data = MemURead(context, address, addr_byte_size, 0, &success);
if (!success) if (!success)
return false; return false;
// if wback then R[n] = offset_addr; // if wback then R[n] = offset_addr;
if (wback) { if (wback) {
context.type = eContextAdjustBaseRegister; context.type = eContextAdjustBaseRegister;
context.SetAddress(offset_addr); context.SetAddress(offset_addr);
if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + n, if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + n,
offset_addr)) offset_addr))
return false; return false;
} }
// if t == 15 then // if t == 15 then
if (t == 15) { if (t == 15) {
// if address<1:0> == '00' then LoadWritePC(data); else UNPREDICTABLE; // if address<1:0> == '00' then LoadWritePC(data); else UNPREDICTABLE;
if (BitIsClear(address, 1) && BitIsClear(address, 0)) { if (BitIsClear(address, 1) && BitIsClear(address, 0)) {
// LoadWritePC (data); // LoadWritePC (data);
context.type = eContextRegisterLoad; context.type = eContextRegisterLoad;
context.SetRegisterPlusOffset(base_reg, address - base_address); context.SetRegisterPlusOffset(*base_reg, address - base_address);
LoadWritePC(context, data); LoadWritePC(context, data);
} else } else
return false; return false;
} }
// elsif UnalignedSupport() || address<1:0> = '00' then // elsif UnalignedSupport() || address<1:0> = '00' then
else if (UnalignedSupport() || else if (UnalignedSupport() ||
(BitIsClear(address, 1) && BitIsClear(address, 0))) { (BitIsClear(address, 1) && BitIsClear(address, 0))) {
// R[t] = data; // R[t] = data;
context.type = eContextRegisterLoad; context.type = eContextRegisterLoad;
context.SetRegisterPlusOffset(base_reg, address - base_address); context.SetRegisterPlusOffset(*base_reg, address - base_address);
if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + t, if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + t,
data)) data))
return false; return false;
} }
// else // Can only apply before ARMv7 // else // Can only apply before ARMv7
else { else {
// R[t] = ROR(data, 8*UInt(address<1:0>)); // R[t] = ROR(data, 8*UInt(address<1:0>));
data = ROR(data, Bits32(address, 1, 0), &success); data = ROR(data, Bits32(address, 1, 0), &success);
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// address = if index then offset_addr else R[n]; // address = if index then offset_addr else R[n];
if (index) if (index)
address = offset_addr; address = offset_addr;
else else
address = Rn; address = Rn;
// data = MemU[address,4]; // data = MemU[address,4];
RegisterInfo base_reg; llvm::Optional<RegisterInfo> base_reg =
GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n, base_reg); GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n);
EmulateInstruction::Context context; EmulateInstruction::Context context;
context.type = eContextRegisterLoad; context.type = eContextRegisterLoad;
context.SetRegisterPlusOffset(base_reg, address - Rn); context.SetRegisterPlusOffset(*base_reg, address - Rn);
uint64_t data = MemURead(context, address, addr_byte_size, 0, &success); uint64_t data = MemURead(context, address, addr_byte_size, 0, &success);
if (!success) if (!success)
return false; return false;
// if wback then R[n] = offset_addr; // if wback then R[n] = offset_addr;
if (wback) { if (wback) {
context.type = eContextAdjustBaseRegister; context.type = eContextAdjustBaseRegister;
context.SetAddress(offset_addr); context.SetAddress(offset_addr);
if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + n, if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + n,
offset_addr)) offset_addr))
return false; return false;
} }
// if t == 15 then // if t == 15 then
if (t == 15) { if (t == 15) {
// if address<1:0> == '00' then LoadWritePC(data); else UNPREDICTABLE; // if address<1:0> == '00' then LoadWritePC(data); else UNPREDICTABLE;
if (BitIsClear(address, 1) && BitIsClear(address, 0)) { if (BitIsClear(address, 1) && BitIsClear(address, 0)) {
context.type = eContextRegisterLoad; context.type = eContextRegisterLoad;
context.SetRegisterPlusOffset(base_reg, address - Rn); context.SetRegisterPlusOffset(*base_reg, address - Rn);
LoadWritePC(context, data); LoadWritePC(context, data);
} else } else
return false; return false;
} }
// elsif UnalignedSupport() || address<1:0> = '00' then // elsif UnalignedSupport() || address<1:0> = '00' then
else if (UnalignedSupport() || else if (UnalignedSupport() ||
(BitIsClear(address, 1) && BitIsClear(address, 0))) { (BitIsClear(address, 1) && BitIsClear(address, 0))) {
// R[t] = data; // R[t] = data;
context.type = eContextRegisterLoad; context.type = eContextRegisterLoad;
context.SetRegisterPlusOffset(base_reg, address - Rn); context.SetRegisterPlusOffset(*base_reg, address - Rn);
if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + t, if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + t,
data)) data))
return false; return false;
} else // Can only apply before ARMv7 } else // Can only apply before ARMv7
{ {
// if CurrentInstrSet() == InstrSet_ARM then // if CurrentInstrSet() == InstrSet_ARM then
if (CurrentInstrSet() == eModeARM) { if (CurrentInstrSet() == eModeARM) {
// R[t] = ROR(data, 8*UInt(address<1:0>)); // R[t] = ROR(data, 8*UInt(address<1:0>));
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// address = if index then offset_addr else R[n]; // address = if index then offset_addr else R[n];
if (index) if (index)
address = offset_addr; address = offset_addr;
else else
address = Rn; address = Rn;
// R[t] = ZeroExtend(MemU[address,1], 32); // R[t] = ZeroExtend(MemU[address,1], 32);
RegisterInfo base_reg; llvm::Optional<RegisterInfo> base_reg =
RegisterInfo data_reg; GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n);
GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n, base_reg); llvm::Optional<RegisterInfo> data_reg =
GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + t, data_reg); GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + t);
EmulateInstruction::Context context; EmulateInstruction::Context context;
context.type = eContextRegisterLoad; context.type = eContextRegisterLoad;
context.SetRegisterToRegisterPlusOffset(data_reg, base_reg, address - Rn); context.SetRegisterToRegisterPlusOffset(*data_reg, *base_reg, address - Rn);
uint64_t data = MemURead(context, address, 1, 0, &success); uint64_t data = MemURead(context, address, 1, 0, &success);
if (!success) if (!success)
return false; return false;
if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + t, data)) if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + t, data))
return false; return false;
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// address = if index then offset_addr else R[n]; // address = if index then offset_addr else R[n];
if (index) if (index)
address = offset_addr; address = offset_addr;
else else
address = Rn; address = Rn;
// R[t] = ZeroExtend(MemU[address,1],32); // R[t] = ZeroExtend(MemU[address,1],32);
RegisterInfo base_reg; llvm::Optional<RegisterInfo> base_reg =
GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n, base_reg); GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n);
EmulateInstruction::Context context; EmulateInstruction::Context context;
context.type = eContextRegisterLoad; context.type = eContextRegisterLoad;
context.SetRegisterPlusOffset(base_reg, address - Rn); context.SetRegisterPlusOffset(*base_reg, address - Rn);
uint64_t data = MemURead(context, address, 1, 0, &success); uint64_t data = MemURead(context, address, 1, 0, &success);
if (!success) if (!success)
return false; return false;
if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + t, data)) if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + t, data))
return false; return false;
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// address = if index then offset_addr else R[n]; // address = if index then offset_addr else R[n];
if (index) if (index)
address = offset_addr; address = offset_addr;
else else
address = Rn; address = Rn;
// data = MemU[address,2]; // data = MemU[address,2];
RegisterInfo base_reg; llvm::Optional<RegisterInfo> base_reg =
GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n, base_reg); GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n);
EmulateInstruction::Context context; EmulateInstruction::Context context;
context.type = eContextRegisterLoad; context.type = eContextRegisterLoad;
context.SetRegisterPlusOffset(base_reg, address - Rn); context.SetRegisterPlusOffset(*base_reg, address - Rn);
uint64_t data = MemURead(context, address, 2, 0, &success); uint64_t data = MemURead(context, address, 2, 0, &success);
if (!success) if (!success)
return false; return false;
// if wback then R[n] = offset_addr; // if wback then R[n] = offset_addr;
if (wback) { if (wback) {
context.type = eContextAdjustBaseRegister; context.type = eContextAdjustBaseRegister;
context.SetAddress(offset_addr); context.SetAddress(offset_addr);
if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + n, if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + n,
offset_addr)) offset_addr))
return false; return false;
} }
// if UnalignedSupport() || address<0> = '0' then // if UnalignedSupport() || address<0> = '0' then
if (UnalignedSupport() || BitIsClear(address, 0)) { if (UnalignedSupport() || BitIsClear(address, 0)) {
// R[t] = ZeroExtend(data, 32); // R[t] = ZeroExtend(data, 32);
context.type = eContextRegisterLoad; context.type = eContextRegisterLoad;
context.SetRegisterPlusOffset(base_reg, address - Rn); context.SetRegisterPlusOffset(*base_reg, address - Rn);
if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + t, if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + t,
data)) data))
return false; return false;
} else // Can only apply before ARMv7 } else // Can only apply before ARMv7
{ {
// R[t] = bits(32) UNKNOWN; // R[t] = bits(32) UNKNOWN;
WriteBits32Unknown(t); WriteBits32Unknown(t);
} }
▲ Show 20 Lines • Show All 69 Lines • ▼ Show 20 Lines if (ConditionPassed(opcode)) {
// address = if add then (base + imm32) else (base - imm32); // address = if add then (base + imm32) else (base - imm32);
if (add) if (add)
address = base + imm32; address = base + imm32;
else else
address = base - imm32; address = base - imm32;
// data = MemU[address,2]; // data = MemU[address,2];
RegisterInfo base_reg; llvm::Optional<RegisterInfo> base_reg =
GetRegisterInfo(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, base_reg); GetRegisterInfo(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC);
EmulateInstruction::Context context; EmulateInstruction::Context context;
context.type = eContextRegisterLoad; context.type = eContextRegisterLoad;
context.SetRegisterPlusOffset(base_reg, address - base); context.SetRegisterPlusOffset(*base_reg, address - base);
uint64_t data = MemURead(context, address, 2, 0, &success); uint64_t data = MemURead(context, address, 2, 0, &success);
if (!success) if (!success)
return false; return false;
// if UnalignedSupport() || address<0> = '0' then // if UnalignedSupport() || address<0> = '0' then
if (UnalignedSupport() || BitIsClear(address, 0)) { if (UnalignedSupport() || BitIsClear(address, 0)) {
// R[t] = ZeroExtend(data, 32); // R[t] = ZeroExtend(data, 32);
context.type = eContextRegisterLoad; context.type = eContextRegisterLoad;
context.SetRegisterPlusOffset(base_reg, address - base); context.SetRegisterPlusOffset(*base_reg, address - base);
if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + t, if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + t,
data)) data))
return false; return false;
} else // Can only apply before ARMv7 } else // Can only apply before ARMv7
{ {
// R[t] = bits(32) UNKNOWN; // R[t] = bits(32) UNKNOWN;
WriteBits32Unknown(t); WriteBits32Unknown(t);
▲ Show 20 Lines • Show All 136 Lines • ▼ Show 20 Lines if (ConditionPassed(opcode)) {
// address = if index then offset_addr else R[n]; // address = if index then offset_addr else R[n];
if (index) if (index)
address = offset_addr; address = offset_addr;
else else
address = Rn; address = Rn;
// data = MemU[address,2]; // data = MemU[address,2];
RegisterInfo base_reg; llvm::Optional<RegisterInfo> base_reg =
RegisterInfo offset_reg; GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n);
GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n, base_reg); llvm::Optional<RegisterInfo> offset_reg =
GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + m, offset_reg); GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + m);
EmulateInstruction::Context context; EmulateInstruction::Context context;
context.type = eContextRegisterLoad; context.type = eContextRegisterLoad;
context.SetRegisterPlusIndirectOffset(base_reg, offset_reg); context.SetRegisterPlusIndirectOffset(*base_reg, *offset_reg);
uint64_t data = MemURead(context, address, 2, 0, &success); uint64_t data = MemURead(context, address, 2, 0, &success);
if (!success) if (!success)
return false; return false;
// if wback then R[n] = offset_addr; // if wback then R[n] = offset_addr;
if (wback) { if (wback) {
context.type = eContextAdjustBaseRegister; context.type = eContextAdjustBaseRegister;
context.SetAddress(offset_addr); context.SetAddress(offset_addr);
if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + n, if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + n,
offset_addr)) offset_addr))
return false; return false;
} }
// if UnalignedSupport() || address<0> = '0' then // if UnalignedSupport() || address<0> = '0' then
if (UnalignedSupport() || BitIsClear(address, 0)) { if (UnalignedSupport() || BitIsClear(address, 0)) {
// R[t] = ZeroExtend(data, 32); // R[t] = ZeroExtend(data, 32);
context.type = eContextRegisterLoad; context.type = eContextRegisterLoad;
context.SetRegisterPlusIndirectOffset(base_reg, offset_reg); context.SetRegisterPlusIndirectOffset(*base_reg, *offset_reg);
if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + t, if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + t,
data)) data))
return false; return false;
} else // Can only apply before ARMv7 } else // Can only apply before ARMv7
{ {
// R[t] = bits(32) UNKNOWN; // R[t] = bits(32) UNKNOWN;
WriteBits32Unknown(t); WriteBits32Unknown(t);
} }
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines if (ConditionPassed(opcode)) {
// address = if index then offset_addr else R[n]; // address = if index then offset_addr else R[n];
if (index) if (index)
address = offset_addr; address = offset_addr;
else else
address = Rn; address = Rn;
// R[t] = SignExtend(MemU[address,1], 32); // R[t] = SignExtend(MemU[address,1], 32);
RegisterInfo base_reg; llvm::Optional<RegisterInfo> base_reg =
GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n, base_reg); GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n);
EmulateInstruction::Context context; EmulateInstruction::Context context;
context.type = eContextRegisterLoad; context.type = eContextRegisterLoad;
context.SetRegisterPlusOffset(base_reg, address - Rn); context.SetRegisterPlusOffset(*base_reg, address - Rn);
uint64_t unsigned_data = MemURead(context, address, 1, 0, &success); uint64_t unsigned_data = MemURead(context, address, 1, 0, &success);
if (!success) if (!success)
return false; return false;
int64_t signed_data = llvm::SignExtend64<8>(unsigned_data); int64_t signed_data = llvm::SignExtend64<8>(unsigned_data);
if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + t, if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + t,
(uint64_t)signed_data)) (uint64_t)signed_data))
▲ Show 20 Lines • Show All 75 Lines • ▼ Show 20 Lines if (ConditionPassed(opcode)) {
// address = if add then (base + imm32) else (base - imm32); // address = if add then (base + imm32) else (base - imm32);
addr_t address; addr_t address;
if (add) if (add)
address = base + imm32; address = base + imm32;
else else
address = base - imm32; address = base - imm32;
// R[t] = SignExtend(MemU[address,1], 32); // R[t] = SignExtend(MemU[address,1], 32);
RegisterInfo base_reg; llvm::Optional<RegisterInfo> base_reg =
GetRegisterInfo(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, base_reg); GetRegisterInfo(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC);
EmulateInstruction::Context context; EmulateInstruction::Context context;
context.type = eContextRegisterLoad; context.type = eContextRegisterLoad;
context.SetRegisterPlusOffset(base_reg, address - base); context.SetRegisterPlusOffset(*base_reg, address - base);
uint64_t unsigned_data = MemURead(context, address, 1, 0, &success); uint64_t unsigned_data = MemURead(context, address, 1, 0, &success);
if (!success) if (!success)
return false; return false;
int64_t signed_data = llvm::SignExtend64<8>(unsigned_data); int64_t signed_data = llvm::SignExtend64<8>(unsigned_data);
if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + t, if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + t,
(uint64_t)signed_data)) (uint64_t)signed_data))
▲ Show 20 Lines • Show All 127 Lines • ▼ Show 20 Lines if (ConditionPassed(opcode)) {
// address = if index then offset_addr else R[n]; // address = if index then offset_addr else R[n];
if (index) if (index)
address = offset_addr; address = offset_addr;
else else
address = Rn; address = Rn;
// R[t] = SignExtend(MemU[address,1], 32); // R[t] = SignExtend(MemU[address,1], 32);
RegisterInfo base_reg; llvm::Optional<RegisterInfo> base_reg =
GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n, base_reg); GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n);
RegisterInfo offset_reg; llvm::Optional<RegisterInfo> offset_reg =
GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + m, offset_reg); GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + m);
EmulateInstruction::Context context; EmulateInstruction::Context context;
context.type = eContextRegisterLoad; context.type = eContextRegisterLoad;
context.SetRegisterPlusIndirectOffset(base_reg, offset_reg); context.SetRegisterPlusIndirectOffset(*base_reg, *offset_reg);
uint64_t unsigned_data = MemURead(context, address, 1, 0, &success); uint64_t unsigned_data = MemURead(context, address, 1, 0, &success);
if (!success) if (!success)
return false; return false;
int64_t signed_data = llvm::SignExtend64<8>(unsigned_data); int64_t signed_data = llvm::SignExtend64<8>(unsigned_data);
if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + t, if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + t,
(uint64_t)signed_data)) (uint64_t)signed_data))
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// address = if index then offset_addr else R[n]; // address = if index then offset_addr else R[n];
addr_t address; addr_t address;
if (index) if (index)
address = offset_addr; address = offset_addr;
else else
address = Rn; address = Rn;
// data = MemU[address,2]; // data = MemU[address,2];
RegisterInfo base_reg; llvm::Optional<RegisterInfo> base_reg =
GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n, base_reg); GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n);
EmulateInstruction::Context context; EmulateInstruction::Context context;
context.type = eContextRegisterLoad; context.type = eContextRegisterLoad;
context.SetRegisterPlusOffset(base_reg, address - Rn); context.SetRegisterPlusOffset(*base_reg, address - Rn);
uint64_t data = MemURead(context, address, 2, 0, &success); uint64_t data = MemURead(context, address, 2, 0, &success);
if (!success) if (!success)
return false; return false;
// if wback then R[n] = offset_addr; // if wback then R[n] = offset_addr;
if (wback) { if (wback) {
context.type = eContextAdjustBaseRegister; context.type = eContextAdjustBaseRegister;
context.SetAddress(offset_addr); context.SetAddress(offset_addr);
if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + n, if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + n,
offset_addr)) offset_addr))
return false; return false;
} }
// if UnalignedSupport() || address<0> = '0' then // if UnalignedSupport() || address<0> = '0' then
if (UnalignedSupport() || BitIsClear(address, 0)) { if (UnalignedSupport() || BitIsClear(address, 0)) {
// R[t] = SignExtend(data, 32); // R[t] = SignExtend(data, 32);
int64_t signed_data = llvm::SignExtend64<16>(data); int64_t signed_data = llvm::SignExtend64<16>(data);
context.type = eContextRegisterLoad; context.type = eContextRegisterLoad;
context.SetRegisterPlusOffset(base_reg, address - Rn); context.SetRegisterPlusOffset(*base_reg, address - Rn);
if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + t, if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + t,
(uint64_t)signed_data)) (uint64_t)signed_data))
return false; return false;
} else // Can only apply before ARMv7 } else // Can only apply before ARMv7
{ {
// R[t] = bits(32) UNKNOWN; // R[t] = bits(32) UNKNOWN;
WriteBits32Unknown(t); WriteBits32Unknown(t);
} }
▲ Show 20 Lines • Show All 68 Lines • ▼ Show 20 Lines if (ConditionPassed(opcode)) {
addr_t address; addr_t address;
// address = if add then (base + imm32) else (base - imm32); // address = if add then (base + imm32) else (base - imm32);
if (add) if (add)
address = base + imm32; address = base + imm32;
else else
address = base - imm32; address = base - imm32;
// data = MemU[address,2]; // data = MemU[address,2];
RegisterInfo base_reg; llvm::Optional<RegisterInfo> base_reg =
GetRegisterInfo(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, base_reg); GetRegisterInfo(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC);
EmulateInstruction::Context context; EmulateInstruction::Context context;
context.type = eContextRegisterLoad; context.type = eContextRegisterLoad;
context.SetRegisterPlusOffset(base_reg, imm32); context.SetRegisterPlusOffset(*base_reg, imm32);
uint64_t data = MemURead(context, address, 2, 0, &success); uint64_t data = MemURead(context, address, 2, 0, &success);
if (!success) if (!success)
return false; return false;
// if UnalignedSupport() || address<0> = '0' then // if UnalignedSupport() || address<0> = '0' then
if (UnalignedSupport() || BitIsClear(address, 0)) { if (UnalignedSupport() || BitIsClear(address, 0)) {
// R[t] = SignExtend(data, 32); // R[t] = SignExtend(data, 32);
▲ Show 20 Lines • Show All 144 Lines • ▼ Show 20 Lines if (ConditionPassed(opcode)) {
// address = if index then offset_addr else R[n]; // address = if index then offset_addr else R[n];
if (index) if (index)
address = offset_addr; address = offset_addr;
else else
address = Rn; address = Rn;
// data = MemU[address,2]; // data = MemU[address,2];
RegisterInfo base_reg; llvm::Optional<RegisterInfo> base_reg =
GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n, base_reg); GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n);
llvm::Optional<RegisterInfo> offset_reg =
RegisterInfo offset_reg; GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + m);
GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + m, offset_reg);
EmulateInstruction::Context context; EmulateInstruction::Context context;
context.type = eContextRegisterLoad; context.type = eContextRegisterLoad;
context.SetRegisterPlusIndirectOffset(base_reg, offset_reg); context.SetRegisterPlusIndirectOffset(*base_reg, *offset_reg);
uint64_t data = MemURead(context, address, 2, 0, &success); uint64_t data = MemURead(context, address, 2, 0, &success);
if (!success) if (!success)
return false; return false;
// if wback then R[n] = offset_addr; // if wback then R[n] = offset_addr;
if (wback) { if (wback) {
context.type = eContextAdjustBaseRegister; context.type = eContextAdjustBaseRegister;
context.SetAddress(offset_addr); context.SetAddress(offset_addr);
if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + n, if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + n,
offset_addr)) offset_addr))
return false; return false;
} }
// if UnalignedSupport() || address<0> = '0' then // if UnalignedSupport() || address<0> = '0' then
if (UnalignedSupport() || BitIsClear(address, 0)) { if (UnalignedSupport() || BitIsClear(address, 0)) {
// R[t] = SignExtend(data, 32); // R[t] = SignExtend(data, 32);
context.type = eContextRegisterLoad; context.type = eContextRegisterLoad;
context.SetRegisterPlusIndirectOffset(base_reg, offset_reg); context.SetRegisterPlusIndirectOffset(*base_reg, *offset_reg);
int64_t signed_data = llvm::SignExtend64<16>(data); int64_t signed_data = llvm::SignExtend64<16>(data);
if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + t, if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + t,
(uint64_t)signed_data)) (uint64_t)signed_data))
return false; return false;
} else // Can only apply before ARMv7 } else // Can only apply before ARMv7
{ {
// R[t] = bits(32) UNKNOWN; // R[t] = bits(32) UNKNOWN;
▲ Show 20 Lines • Show All 69 Lines • ▼ Show 20 Lines if (ConditionPassed(opcode)) {
// rotated = ROR(R[m], rotation); // rotated = ROR(R[m], rotation);
uint64_t rotated = ROR(Rm, rotation, &success); uint64_t rotated = ROR(Rm, rotation, &success);
if (!success) if (!success)
return false; return false;
// R[d] = SignExtend(rotated<7:0>, 32); // R[d] = SignExtend(rotated<7:0>, 32);
int64_t data = llvm::SignExtend64<8>(rotated); int64_t data = llvm::SignExtend64<8>(rotated);
RegisterInfo source_reg; llvm::Optional<RegisterInfo> source_reg =
GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + m, source_reg); GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + m);
EmulateInstruction::Context context; EmulateInstruction::Context context;
context.type = eContextRegisterLoad; context.type = eContextRegisterLoad;
context.SetRegister(source_reg); context.SetRegister(*source_reg);
if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + d, if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + d,
(uint64_t)data)) (uint64_t)data))
return false; return false;
} }
return true; return true;
} }
▲ Show 20 Lines • Show All 61 Lines • ▼ Show 20 Lines if (!success)
return false; return false;
// rotated = ROR(R[m], rotation); // rotated = ROR(R[m], rotation);
uint64_t rotated = ROR(Rm, rotation, &success); uint64_t rotated = ROR(Rm, rotation, &success);
if (!success) if (!success)
return false; return false;
// R[d] = SignExtend(rotated<15:0>, 32); // R[d] = SignExtend(rotated<15:0>, 32);
RegisterInfo source_reg; llvm::Optional<RegisterInfo> source_reg =
GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + m, source_reg); GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + m);
EmulateInstruction::Context context; EmulateInstruction::Context context;
context.type = eContextRegisterLoad; context.type = eContextRegisterLoad;
context.SetRegister(source_reg); context.SetRegister(*source_reg);
int64_t data = llvm::SignExtend64<16>(rotated); int64_t data = llvm::SignExtend64<16>(rotated);
if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + d, if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + d,
(uint64_t)data)) (uint64_t)data))
return false; return false;
} }
return true; return true;
▲ Show 20 Lines • Show All 63 Lines • ▼ Show 20 Lines if (!success)
return false; return false;
// rotated = ROR(R[m], rotation); // rotated = ROR(R[m], rotation);
uint64_t rotated = ROR(Rm, rotation, &success); uint64_t rotated = ROR(Rm, rotation, &success);
if (!success) if (!success)
return false; return false;
// R[d] = ZeroExtend(rotated<7:0>, 32); // R[d] = ZeroExtend(rotated<7:0>, 32);
RegisterInfo source_reg; llvm::Optional<RegisterInfo> source_reg =
GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + m, source_reg); GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + m);
EmulateInstruction::Context context; EmulateInstruction::Context context;
context.type = eContextRegisterLoad; context.type = eContextRegisterLoad;
context.SetRegister(source_reg); context.SetRegister(*source_reg);
if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + d, if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + d,
Bits32(rotated, 7, 0))) Bits32(rotated, 7, 0)))
return false; return false;
} }
return true; return true;
} }
▲ Show 20 Lines • Show All 60 Lines • ▼ Show 20 Lines if (!success)
return false; return false;
// rotated = ROR(R[m], rotation); // rotated = ROR(R[m], rotation);
uint64_t rotated = ROR(Rm, rotation, &success); uint64_t rotated = ROR(Rm, rotation, &success);
if (!success) if (!success)
return false; return false;
// R[d] = ZeroExtend(rotated<15:0>, 32); // R[d] = ZeroExtend(rotated<15:0>, 32);
RegisterInfo source_reg; llvm::Optional<RegisterInfo> source_reg =
GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + m, source_reg); GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + m);
EmulateInstruction::Context context; EmulateInstruction::Context context;
context.type = eContextRegisterLoad; context.type = eContextRegisterLoad;
context.SetRegister(source_reg); context.SetRegister(*source_reg);
if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + d, if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + d,
Bits32(rotated, 15, 0))) Bits32(rotated, 15, 0)))
return false; return false;
} }
return true; return true;
} }
▲ Show 20 Lines • Show All 97 Lines • ▼ Show 20 Lines else {
else else
address = Rn - 8; address = Rn - 8;
// if wordhigher then address = address+4; // if wordhigher then address = address+4;
if (wordhigher) if (wordhigher)
address = address + 4; address = address + 4;
// CPSRWriteByInstr(MemA[address+4,4], '1111', TRUE); // CPSRWriteByInstr(MemA[address+4,4], '1111', TRUE);
RegisterInfo base_reg; llvm::Optional<RegisterInfo> base_reg =
GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n, base_reg); GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n);
EmulateInstruction::Context context; EmulateInstruction::Context context;
context.type = eContextReturnFromException; context.type = eContextReturnFromException;
context.SetRegisterPlusOffset(base_reg, address - Rn); context.SetRegisterPlusOffset(*base_reg, address - Rn);
uint64_t data = MemARead(context, address + 4, 4, 0, &success); uint64_t data = MemARead(context, address + 4, 4, 0, &success);
if (!success) if (!success)
return false; return false;
CPSRWriteByInstr(data, 15, true); CPSRWriteByInstr(data, 15, true);
// BranchWritePC(MemA[address,4]); // BranchWritePC(MemA[address,4]);
▲ Show 20 Lines • Show All 940 Lines • ▼ Show 20 Lines if (ConditionPassed(opcode)) {
AddWithCarryResult res = AddWithCarry(reg_val, ~imm32, 1); AddWithCarryResult res = AddWithCarry(reg_val, ~imm32, 1);
EmulateInstruction::Context context; EmulateInstruction::Context context;
if (Rd == 13) if (Rd == 13)
context.type = EmulateInstruction::eContextAdjustStackPointer; context.type = EmulateInstruction::eContextAdjustStackPointer;
else else
context.type = EmulateInstruction::eContextRegisterPlusOffset; context.type = EmulateInstruction::eContextRegisterPlusOffset;
RegisterInfo dwarf_reg; llvm::Optional<RegisterInfo> dwarf_reg =
GetRegisterInfo(eRegisterKindDWARF, Rn, dwarf_reg); GetRegisterInfo(eRegisterKindDWARF, Rn);
int64_t imm32_signed = imm32; int64_t imm32_signed = imm32;
context.SetRegisterPlusOffset(dwarf_reg, -imm32_signed); context.SetRegisterPlusOffset(*dwarf_reg, -imm32_signed);
if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags, if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags,
res.carry_out, res.overflow)) res.carry_out, res.overflow))
return false; return false;
} }
return true; return true;
} }
▲ Show 20 Lines • Show All 333 Lines • ▼ Show 20 Lines if (ConditionPassed(opcode)) {
uint32_t sp_val = ReadCoreReg(SP_REG, &success); uint32_t sp_val = ReadCoreReg(SP_REG, &success);
if (!success) if (!success)
return false; return false;
AddWithCarryResult res = AddWithCarry(sp_val, ~shifted, 1); AddWithCarryResult res = AddWithCarry(sp_val, ~shifted, 1);
EmulateInstruction::Context context; EmulateInstruction::Context context;
context.type = eContextArithmetic; context.type = eContextArithmetic;
RegisterInfo sp_reg; llvm::Optional<RegisterInfo> sp_reg =
GetRegisterInfo(eRegisterKindDWARF, dwarf_sp, sp_reg); GetRegisterInfo(eRegisterKindDWARF, dwarf_sp);
RegisterInfo dwarf_reg; llvm::Optional<RegisterInfo> dwarf_reg =
GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + m, dwarf_reg); GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + m);
context.SetRegisterRegisterOperands(sp_reg, dwarf_reg); context.SetRegisterRegisterOperands(*sp_reg, *dwarf_reg);
if (!WriteCoreRegOptionalFlags(context, res.result, dwarf_r0 + d, setflags, if (!WriteCoreRegOptionalFlags(context, res.result, dwarf_r0 + d, setflags,
res.carry_out, res.overflow)) res.carry_out, res.overflow))
return false; return false;
} }
return true; return true;
} }
▲ Show 20 Lines • Show All 66 Lines • ▼ Show 20 Lines if (ConditionPassed(opcode)) {
if (!success) if (!success)
return false; return false;
AddWithCarryResult res = AddWithCarry(Rn, shifted, 0); AddWithCarryResult res = AddWithCarry(Rn, shifted, 0);
// R[d] = result; // R[d] = result;
EmulateInstruction::Context context; EmulateInstruction::Context context;
context.type = eContextArithmetic; context.type = eContextArithmetic;
RegisterInfo reg_n; llvm::Optional<RegisterInfo> reg_n =
GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n, reg_n); GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n);
RegisterInfo reg_m; llvm::Optional<RegisterInfo> reg_m =
GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + m, reg_m); GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + m);
context.SetRegisterRegisterOperands(reg_n, reg_m); context.SetRegisterRegisterOperands(*reg_n, *reg_m);
if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + d, if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + d,
res.result)) res.result))
return false; return false;
// if setflags then // if setflags then
// APSR.N = result<31>; // APSR.N = result<31>;
// APSR.Z = IsZeroBit(result); // APSR.Z = IsZeroBit(result);
▲ Show 20 Lines • Show All 118 Lines • ▼ Show 20 Lines if (ConditionPassed(opcode)) {
// if setflags then // if setflags then
// APSR.N = result<31>; // APSR.N = result<31>;
// APSR.Z = IsZeroBit(result); // APSR.Z = IsZeroBit(result);
// APSR.C = carry; // APSR.C = carry;
// APSR.V = overflow; // APSR.V = overflow;
EmulateInstruction::Context context; EmulateInstruction::Context context;
context.type = eContextArithmetic; context.type = eContextArithmetic;
RegisterInfo reg_n; llvm::Optional<RegisterInfo> reg_n =
GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n, reg_n); GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n);
RegisterInfo reg_m; llvm::Optional<RegisterInfo> reg_m =
GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + m, reg_m); GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + m);
context.SetRegisterRegisterOperands(reg_n, reg_m); context.SetRegisterRegisterOperands(*reg_n, *reg_m);
if (!WriteCoreRegOptionalFlags(context, res.result, dwarf_r0 + d, setflags, if (!WriteCoreRegOptionalFlags(context, res.result, dwarf_r0 + d, setflags,
res.carry_out, res.overflow)) res.carry_out, res.overflow))
return false; return false;
} }
return true; return true;
} }
▲ Show 20 Lines • Show All 67 Lines • ▼ Show 20 Lines if (ConditionPassed(opcode)) {
// address = R[n] + imm32; // address = R[n] + imm32;
uint32_t Rn = ReadCoreReg(n, &success); uint32_t Rn = ReadCoreReg(n, &success);
if (!success) if (!success)
return false; return false;
addr_t address = Rn + imm32; addr_t address = Rn + imm32;
RegisterInfo base_reg; llvm::Optional<RegisterInfo> base_reg =
GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n, base_reg); GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n);
RegisterInfo data_reg; llvm::Optional<RegisterInfo> data_reg =
GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + t, data_reg); GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + t);
EmulateInstruction::Context context; EmulateInstruction::Context context;
context.type = eContextRegisterStore; context.type = eContextRegisterStore;
context.SetRegisterToRegisterPlusOffset(data_reg, base_reg, imm32); context.SetRegisterToRegisterPlusOffset(*data_reg, *base_reg, imm32);
// if ExclusiveMonitorsPass(address,4) then if (ExclusiveMonitorsPass // if ExclusiveMonitorsPass(address,4) then if (ExclusiveMonitorsPass
// (address, addr_byte_size)) -- For now, for the sake of emulation, we // (address, addr_byte_size)) -- For now, for the sake of emulation, we
// will say this // will say this
// always return // always return
// true. // true.
if (true) { if (true) {
// MemA[address,4] = R[t]; // MemA[address,4] = R[t];
▲ Show 20 Lines • Show All 88 Lines • ▼ Show 20 Lines if (ConditionPassed(opcode)) {
else else
address = Rn; address = Rn;
// MemU[address,1] = R[t]<7:0>; // MemU[address,1] = R[t]<7:0>;
uint32_t Rt = ReadCoreReg(t, &success); uint32_t Rt = ReadCoreReg(t, &success);
if (!success) if (!success)
return false; return false;
RegisterInfo base_reg; llvm::Optional<RegisterInfo> base_reg =
GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n, base_reg); GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n);
RegisterInfo data_reg; llvm::Optional<RegisterInfo> data_reg =
GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + t, data_reg); GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + t);
EmulateInstruction::Context context; EmulateInstruction::Context context;
context.type = eContextRegisterStore; context.type = eContextRegisterStore;
context.SetRegisterToRegisterPlusOffset(data_reg, base_reg, address - Rn); context.SetRegisterToRegisterPlusOffset(*data_reg, *base_reg, address - Rn);
if (!MemUWrite(context, address, Bits32(Rt, 7, 0), 1)) if (!MemUWrite(context, address, Bits32(Rt, 7, 0), 1))
return false; return false;
// if wback then R[n] = offset_addr; // if wback then R[n] = offset_addr;
if (wback) { if (wback) {
if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + n, if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + n,
offset_addr)) offset_addr))
▲ Show 20 Lines • Show All 65 Lines • ▼ Show 20 Lines if (ConditionPassed(opcode)) {
// address = if index then offset_addr else R[n]; // address = if index then offset_addr else R[n];
addr_t address; addr_t address;
if (index) if (index)
address = offset_addr; address = offset_addr;
else else
address = Rn; address = Rn;
RegisterInfo base_reg; llvm::Optional<RegisterInfo> base_reg =
GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n, base_reg); GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n);
RegisterInfo data_reg; llvm::Optional<RegisterInfo> data_reg =
GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + t, data_reg); GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + t);
EmulateInstruction::Context context; EmulateInstruction::Context context;
context.type = eContextRegisterStore; context.type = eContextRegisterStore;
context.SetRegisterToRegisterPlusOffset(data_reg, base_reg, address - Rn); context.SetRegisterToRegisterPlusOffset(*data_reg, *base_reg, address - Rn);
// MemU[address,4] = if t == 15 then PCStoreValue() else R[t]; // MemU[address,4] = if t == 15 then PCStoreValue() else R[t];
uint32_t Rt = ReadCoreReg(t, &success); uint32_t Rt = ReadCoreReg(t, &success);
if (!success) if (!success)
return false; return false;
if (t == 15) { if (t == 15) {
uint32_t pc_value = ReadCoreReg(PC_REG, &success); uint32_t pc_value = ReadCoreReg(PC_REG, &success);
▲ Show 20 Lines • Show All 123 Lines • ▼ Show 20 Lines if (ConditionPassed(opcode)) {
// address = if index then offset_addr else R[n]; // address = if index then offset_addr else R[n];
addr_t address; addr_t address;
if (index) if (index)
address = offset_addr; address = offset_addr;
else else
address = Rn; address = Rn;
// R[t] = MemA[address,4]; // R[t] = MemA[address,4];
RegisterInfo base_reg;
GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n, base_reg);
EmulateInstruction::Context context; EmulateInstruction::Context context;
if (n == 13) if (n == 13)
context.type = eContextPopRegisterOffStack; context.type = eContextPopRegisterOffStack;
else else
context.type = eContextRegisterLoad; context.type = eContextRegisterLoad;
context.SetAddress(address); context.SetAddress(address);
▲ Show 20 Lines • Show All 90 Lines • ▼ Show 20 Lines if (ConditionPassed(opcode)) {
default: default:
return false; return false;
} }
uint32_t Rn = ReadCoreReg(n, &success); uint32_t Rn = ReadCoreReg(n, &success);
if (!success) if (!success)
return false; return false;
RegisterInfo base_reg;
GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n, base_reg);
uint32_t Rm = ReadCoreReg(m, &success); uint32_t Rm = ReadCoreReg(m, &success);
if (!success) if (!success)
return false; return false;
RegisterInfo offset_reg;
GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + m, offset_reg);
// offset_addr = if add then (R[n] + R[m]) else (R[n] - R[m]); // offset_addr = if add then (R[n] + R[m]) else (R[n] - R[m]);
addr_t offset_addr; addr_t offset_addr;
if (add) if (add)
offset_addr = Rn + Rm; offset_addr = Rn + Rm;
else else
offset_addr = Rn - Rm; offset_addr = Rn - Rm;
▲ Show 20 Lines • Show All 125 Lines • ▼ Show 20 Lines case eEncodingA1:
return false; return false;
break; break;
default: default:
return false; return false;
} }
RegisterInfo base_reg; llvm::Optional<RegisterInfo> base_reg =
GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n, base_reg); GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n);
uint32_t Rn = ReadCoreReg(n, &success); uint32_t Rn = ReadCoreReg(n, &success);
if (!success) if (!success)
return false; return false;
// offset_addr = if add then (R[n] + imm32) else (R[n] - imm32); // offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
addr_t offset_addr; addr_t offset_addr;
if (add) if (add)
offset_addr = Rn + imm32; offset_addr = Rn + imm32;
else else
offset_addr = Rn - imm32; offset_addr = Rn - imm32;
// address = if index then offset_addr else R[n]; // address = if index then offset_addr else R[n];
addr_t address; addr_t address;
if (index) if (index)
address = offset_addr; address = offset_addr;
else else
address = Rn; address = Rn;
// MemA[address,4] = R[t]; // MemA[address,4] = R[t];
RegisterInfo data_reg; llvm::Optional<RegisterInfo> data_reg =
GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + t, data_reg); GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + t);
uint32_t data = ReadCoreReg(t, &success); uint32_t data = ReadCoreReg(t, &success);
if (!success) if (!success)
return false; return false;
EmulateInstruction::Context context; EmulateInstruction::Context context;
if (n == 13) if (n == 13)
context.type = eContextPushRegisterOnStack; context.type = eContextPushRegisterOnStack;
else else
context.type = eContextRegisterStore; context.type = eContextRegisterStore;
context.SetRegisterToRegisterPlusOffset(data_reg, base_reg, address - Rn); context.SetRegisterToRegisterPlusOffset(*data_reg, *base_reg, address - Rn);
const uint32_t addr_byte_size = GetAddressByteSize(); const uint32_t addr_byte_size = GetAddressByteSize();
if (!MemAWrite(context, address, data, addr_byte_size)) if (!MemAWrite(context, address, data, addr_byte_size))
return false; return false;
// MemA[address+4,4] = R[t2]; // MemA[address+4,4] = R[t2];
GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + t2, data_reg); data_reg = GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + t2);
context.SetRegisterToRegisterPlusOffset(data_reg, base_reg, context.SetRegisterToRegisterPlusOffset(*data_reg, *base_reg,
(address + 4) - Rn); (address + 4) - Rn);
data = ReadCoreReg(t2, &success); data = ReadCoreReg(t2, &success);
if (!success) if (!success)
return false; return false;
if (!MemAWrite(context, address + 4, data, addr_byte_size)) if (!MemAWrite(context, address + 4, data, addr_byte_size))
return false; return false;
▲ Show 20 Lines • Show All 72 Lines • ▼ Show 20 Lines case eEncodingA1:
return false; return false;
break; break;
default: default:
return false; return false;
} }
RegisterInfo base_reg;
GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n, base_reg);
RegisterInfo offset_reg;
GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + m, offset_reg);
RegisterInfo data_reg;
uint32_t Rn = ReadCoreReg(n, &success); uint32_t Rn = ReadCoreReg(n, &success);
if (!success) if (!success)
return false; return false;
uint32_t Rm = ReadCoreReg(m, &success); uint32_t Rm = ReadCoreReg(m, &success);
if (!success) if (!success)
return false; return false;
Show All 16 Lines if (!success)
return false; return false;
EmulateInstruction::Context context; EmulateInstruction::Context context;
if (t == 13) if (t == 13)
context.type = eContextPushRegisterOnStack; context.type = eContextPushRegisterOnStack;
else else
context.type = eContextRegisterStore; context.type = eContextRegisterStore;
GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + t, data_reg); llvm::Optional<RegisterInfo> base_reg =
context.SetRegisterToRegisterPlusIndirectOffset(base_reg, offset_reg, GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n);
data_reg); llvm::Optional<RegisterInfo> offset_reg =
GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + m);
llvm::Optional<RegisterInfo> data_reg =
GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + t);
context.SetRegisterToRegisterPlusIndirectOffset(*base_reg, *offset_reg,
*data_reg);
const uint32_t addr_byte_size = GetAddressByteSize(); const uint32_t addr_byte_size = GetAddressByteSize();
if (!MemAWrite(context, address, Rt, addr_byte_size)) if (!MemAWrite(context, address, Rt, addr_byte_size))
return false; return false;
// MemA[address+4,4] = R[t2]; // MemA[address+4,4] = R[t2];
uint32_t Rt2 = ReadCoreReg(t2, &success); uint32_t Rt2 = ReadCoreReg(t2, &success);
if (!success) if (!success)
return false; return false;
GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + t2, data_reg); data_reg = GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + t2);
context.SetRegisterToRegisterPlusIndirectOffset(base_reg, offset_reg, context.SetRegisterToRegisterPlusIndirectOffset(*base_reg, *offset_reg,
data_reg); *data_reg);
if (!MemAWrite(context, address + 4, Rt2, addr_byte_size)) if (!MemAWrite(context, address + 4, Rt2, addr_byte_size))
return false; return false;
// if wback then R[n] = offset_addr; // if wback then R[n] = offset_addr;
if (wback) { if (wback) {
context.type = eContextAdjustBaseRegister; context.type = eContextAdjustBaseRegister;
context.SetAddress(offset_addr); context.SetAddress(offset_addr);
▲ Show 20 Lines • Show All 105 Lines • ▼ Show 20 Lines case eEncodingA2:
if ((regs == 0) || ((d + regs) > 32)) if ((regs == 0) || ((d + regs) > 32))
return false; return false;
break; break;
default: default:
return false; return false;
} }
RegisterInfo base_reg;
GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n, base_reg);
uint32_t Rn = ReadCoreReg(n, &success); uint32_t Rn = ReadCoreReg(n, &success);
if (!success) if (!success)
return false; return false;
// address = if add then R[n] else R[n]-imm32; // address = if add then R[n] else R[n]-imm32;
addr_t address; addr_t address;
if (add) if (add)
address = Rn; address = Rn;
Show All 17 Lines if (wback) {
return false; return false;
} }
const uint32_t addr_byte_size = GetAddressByteSize(); const uint32_t addr_byte_size = GetAddressByteSize();
uint32_t start_reg = single_regs ? dwarf_s0 : dwarf_d0; uint32_t start_reg = single_regs ? dwarf_s0 : dwarf_d0;
context.type = eContextRegisterLoad; context.type = eContextRegisterLoad;
llvm::Optional<RegisterInfo> base_reg =
GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n);
// for r = 0 to regs-1 // for r = 0 to regs-1
for (uint32_t r = 0; r < regs; ++r) { for (uint32_t r = 0; r < regs; ++r) {
if (single_regs) { if (single_regs) {
// S[d+r] = MemA[address,4]; address = address+4; // S[d+r] = MemA[address,4]; address = address+4;
context.SetRegisterPlusOffset(base_reg, address - Rn); context.SetRegisterPlusOffset(*base_reg, address - Rn);
uint32_t data = MemARead(context, address, addr_byte_size, 0, &success); uint32_t data = MemARead(context, address, addr_byte_size, 0, &success);
if (!success) if (!success)
return false; return false;
if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, if (!WriteRegisterUnsigned(context, eRegisterKindDWARF,
start_reg + d + r, data)) start_reg + d + r, data))
return false; return false;
address = address + 4; address = address + 4;
} else { } else {
// word1 = MemA[address,4]; word2 = MemA[address+4,4]; address = // word1 = MemA[address,4]; word2 = MemA[address+4,4]; address =
// address+8; // address+8;
context.SetRegisterPlusOffset(base_reg, address - Rn); context.SetRegisterPlusOffset(*base_reg, address - Rn);
uint32_t word1 = uint32_t word1 =
MemARead(context, address, addr_byte_size, 0, &success); MemARead(context, address, addr_byte_size, 0, &success);
if (!success) if (!success)
return false; return false;
context.SetRegisterPlusOffset(base_reg, (address + 4) - Rn); context.SetRegisterPlusOffset(*base_reg, (address + 4) - Rn);
uint32_t word2 = uint32_t word2 =
MemARead(context, address + 4, addr_byte_size, 0, &success); MemARead(context, address + 4, addr_byte_size, 0, &success);
if (!success) if (!success)
return false; return false;
address = address + 8; address = address + 8;
// // Combine the word-aligned words in the correct order for current // // Combine the word-aligned words in the correct order for current
// endianness. // endianness.
▲ Show 20 Lines • Show All 118 Lines • ▼ Show 20 Lines case eEncodingA2:
return false; return false;
break; break;
default: default:
return false; return false;
} }
RegisterInfo base_reg; llvm::Optional<RegisterInfo> base_reg =
GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n, base_reg); GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n);
uint32_t Rn = ReadCoreReg(n, &success); uint32_t Rn = ReadCoreReg(n, &success);
if (!success) if (!success)
return false; return false;
// address = if add then R[n] else R[n]-imm32; // address = if add then R[n] else R[n]-imm32;
addr_t address; addr_t address;
if (add) if (add)
address = Rn; address = Rn;
else else
address = Rn - imm32; address = Rn - imm32;
EmulateInstruction::Context context; EmulateInstruction::Context context;
// if wback then R[n] = if add then R[n]+imm32 else R[n]-imm32; // if wback then R[n] = if add then R[n]+imm32 else R[n]-imm32;
if (wback) { if (wback) {
uint32_t value; uint32_t value;
if (add) if (add)
value = Rn + imm32; value = Rn + imm32;
else else
value = Rn - imm32; value = Rn - imm32;
context.type = eContextAdjustBaseRegister; context.type = eContextAdjustBaseRegister;
context.SetRegisterPlusOffset(base_reg, value - Rn); context.SetRegisterPlusOffset(*base_reg, value - Rn);
if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + n, if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + n,
value)) value))
return false; return false;
} }
const uint32_t addr_byte_size = GetAddressByteSize(); const uint32_t addr_byte_size = GetAddressByteSize();
uint32_t start_reg = single_regs ? dwarf_s0 : dwarf_d0; uint32_t start_reg = single_regs ? dwarf_s0 : dwarf_d0;
context.type = eContextRegisterStore; context.type = eContextRegisterStore;
// for r = 0 to regs-1 // for r = 0 to regs-1
for (uint32_t r = 0; r < regs; ++r) { for (uint32_t r = 0; r < regs; ++r) {
if (single_regs) { if (single_regs) {
// MemA[address,4] = S[d+r]; address = address+4; // MemA[address,4] = S[d+r]; address = address+4;
uint32_t data = ReadRegisterUnsigned(eRegisterKindDWARF, uint32_t data = ReadRegisterUnsigned(eRegisterKindDWARF,
start_reg + d + r, 0, &success); start_reg + d + r, 0, &success);
if (!success) if (!success)
return false; return false;
RegisterInfo data_reg; llvm::Optional<RegisterInfo> data_reg =
GetRegisterInfo(eRegisterKindDWARF, start_reg + d + r, data_reg); GetRegisterInfo(eRegisterKindDWARF, start_reg + d + r);
context.SetRegisterToRegisterPlusOffset(data_reg, base_reg, context.SetRegisterToRegisterPlusOffset(*data_reg, *base_reg,
address - Rn); address - Rn);
if (!MemAWrite(context, address, data, addr_byte_size)) if (!MemAWrite(context, address, data, addr_byte_size))
return false; return false;
address = address + 4; address = address + 4;
} else { } else {
// // Store as two word-aligned words in the correct order for current // // Store as two word-aligned words in the correct order for current
// endianness. MemA[address,4] = if BigEndian() then D[d+r]<63:32> else // endianness. MemA[address,4] = if BigEndian() then D[d+r]<63:32> else
// D[d+r]<31:0>; // D[d+r]<31:0>;
// MemA[address+4,4] = if BigEndian() then D[d+r]<31:0> else // MemA[address+4,4] = if BigEndian() then D[d+r]<31:0> else
// D[d+r]<63:32>; // D[d+r]<63:32>;
uint64_t data = ReadRegisterUnsigned(eRegisterKindDWARF, uint64_t data = ReadRegisterUnsigned(eRegisterKindDWARF,
start_reg + d + r, 0, &success); start_reg + d + r, 0, &success);
if (!success) if (!success)
return false; return false;
RegisterInfo data_reg; llvm::Optional<RegisterInfo> data_reg =
GetRegisterInfo(eRegisterKindDWARF, start_reg + d + r, data_reg); GetRegisterInfo(eRegisterKindDWARF, start_reg + d + r);
if (GetByteOrder() == eByteOrderBig) { if (GetByteOrder() == eByteOrderBig) {
context.SetRegisterToRegisterPlusOffset(data_reg, base_reg, context.SetRegisterToRegisterPlusOffset(*data_reg, *base_reg,
address - Rn); address - Rn);
if (!MemAWrite(context, address, Bits64(data, 63, 32), if (!MemAWrite(context, address, Bits64(data, 63, 32),
addr_byte_size)) addr_byte_size))
return false; return false;
context.SetRegisterToRegisterPlusOffset(data_reg, base_reg, context.SetRegisterToRegisterPlusOffset(*data_reg, *base_reg,
(address + 4) - Rn); (address + 4) - Rn);
if (!MemAWrite(context, address + 4, Bits64(data, 31, 0), if (!MemAWrite(context, address + 4, Bits64(data, 31, 0),
addr_byte_size)) addr_byte_size))
return false; return false;
} else { } else {
context.SetRegisterToRegisterPlusOffset(data_reg, base_reg, context.SetRegisterToRegisterPlusOffset(*data_reg, *base_reg,
address - Rn); address - Rn);
if (!MemAWrite(context, address, Bits64(data, 31, 0), addr_byte_size)) if (!MemAWrite(context, address, Bits64(data, 31, 0), addr_byte_size))
return false; return false;
context.SetRegisterToRegisterPlusOffset(data_reg, base_reg, context.SetRegisterToRegisterPlusOffset(*data_reg, *base_reg,
(address + 4) - Rn); (address + 4) - Rn);
if (!MemAWrite(context, address + 4, Bits64(data, 63, 32), if (!MemAWrite(context, address + 4, Bits64(data, 63, 32),
addr_byte_size)) addr_byte_size))
return false; return false;
} }
// address = address+8; // address = address+8;
address = address + 8; address = address + 8;
} }
▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Lines case eEncodingA2:
d = (Bits32(opcode, 15, 12) << 1) | Bit32(opcode, 22); d = (Bits32(opcode, 15, 12) << 1) | Bit32(opcode, 22);
n = Bits32(opcode, 19, 16); n = Bits32(opcode, 19, 16);
break; break;
default: default:
return false; return false;
} }
RegisterInfo base_reg; llvm::Optional<RegisterInfo> base_reg =
GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n, base_reg); GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n);
uint32_t Rn = ReadCoreReg(n, &success); uint32_t Rn = ReadCoreReg(n, &success);
if (!success) if (!success)
return false; return false;
// base = if n == 15 then Align(PC,4) else R[n]; // base = if n == 15 then Align(PC,4) else R[n];
uint32_t base; uint32_t base;
if (n == 15) if (n == 15)
base = AlignPC(Rn); base = AlignPC(Rn);
else else
base = Rn; base = Rn;
// address = if add then (base + imm32) else (base - imm32); // address = if add then (base + imm32) else (base - imm32);
addr_t address; addr_t address;
if (add) if (add)
address = base + imm32; address = base + imm32;
else else
address = base - imm32; address = base - imm32;
const uint32_t addr_byte_size = GetAddressByteSize(); const uint32_t addr_byte_size = GetAddressByteSize();
uint32_t start_reg = single_reg ? dwarf_s0 : dwarf_d0; uint32_t start_reg = single_reg ? dwarf_s0 : dwarf_d0;
EmulateInstruction::Context context; EmulateInstruction::Context context;
context.type = eContextRegisterLoad; context.type = eContextRegisterLoad;
context.SetRegisterPlusOffset(base_reg, address - base); context.SetRegisterPlusOffset(*base_reg, address - base);
if (single_reg) { if (single_reg) {
// S[d] = MemA[address,4]; // S[d] = MemA[address,4];
uint32_t data = MemARead(context, address, addr_byte_size, 0, &success); uint32_t data = MemARead(context, address, addr_byte_size, 0, &success);
if (!success) if (!success)
return false; return false;
if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, start_reg + d, if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, start_reg + d,
data)) data))
return false; return false;
} else { } else {
// word1 = MemA[address,4]; word2 = MemA[address+4,4]; // word1 = MemA[address,4]; word2 = MemA[address+4,4];
uint32_t word1 = MemARead(context, address, addr_byte_size, 0, &success); uint32_t word1 = MemARead(context, address, addr_byte_size, 0, &success);
if (!success) if (!success)
return false; return false;
context.SetRegisterPlusOffset(base_reg, (address + 4) - base); context.SetRegisterPlusOffset(*base_reg, (address + 4) - base);
uint32_t word2 = uint32_t word2 =
MemARead(context, address + 4, addr_byte_size, 0, &success); MemARead(context, address + 4, addr_byte_size, 0, &success);
if (!success) if (!success)
return false; return false;
// // Combine the word-aligned words in the correct order for current // // Combine the word-aligned words in the correct order for current
// endianness. // endianness.
// D[d] = if BigEndian() then word1:word2 else word2:word1; // D[d] = if BigEndian() then word1:word2 else word2:word1;
uint64_t data64; uint64_t data64;
▲ Show 20 Lines • Show All 75 Lines • ▼ Show 20 Lines case eEncodingA2:
return false; return false;
break; break;
default: default:
return false; return false;
} }
RegisterInfo base_reg;
GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n, base_reg);
uint32_t Rn = ReadCoreReg(n, &success); uint32_t Rn = ReadCoreReg(n, &success);
if (!success) if (!success)
return false; return false;
// address = if add then (R[n] + imm32) else (R[n] - imm32); // address = if add then (R[n] + imm32) else (R[n] - imm32);
addr_t address; addr_t address;
if (add) if (add)
address = Rn + imm32; address = Rn + imm32;
else else
address = Rn - imm32; address = Rn - imm32;
const uint32_t addr_byte_size = GetAddressByteSize(); const uint32_t addr_byte_size = GetAddressByteSize();
uint32_t start_reg = single_reg ? dwarf_s0 : dwarf_d0; uint32_t start_reg = single_reg ? dwarf_s0 : dwarf_d0;
RegisterInfo data_reg; llvm::Optional<RegisterInfo> base_reg =
GetRegisterInfo(eRegisterKindDWARF, start_reg + d, data_reg); GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n);
llvm::Optional<RegisterInfo> data_reg =
GetRegisterInfo(eRegisterKindDWARF, start_reg + d);
EmulateInstruction::Context context; EmulateInstruction::Context context;
context.type = eContextRegisterStore; context.type = eContextRegisterStore;
context.SetRegisterToRegisterPlusOffset(data_reg, base_reg, address - Rn); context.SetRegisterToRegisterPlusOffset(*data_reg, *base_reg, address - Rn);
if (single_reg) { if (single_reg) {
// MemA[address,4] = S[d]; // MemA[address,4] = S[d];
uint32_t data = uint32_t data =
ReadRegisterUnsigned(eRegisterKindDWARF, start_reg + d, 0, &success); ReadRegisterUnsigned(eRegisterKindDWARF, start_reg + d, 0, &success);
if (!success) if (!success)
return false; return false;
if (!MemAWrite(context, address, data, addr_byte_size)) if (!MemAWrite(context, address, data, addr_byte_size))
return false; return false;
} else { } else {
// // Store as two word-aligned words in the correct order for current // // Store as two word-aligned words in the correct order for current
// endianness. // endianness.
// MemA[address,4] = if BigEndian() then D[d]<63:32> else D[d]<31:0>; // MemA[address,4] = if BigEndian() then D[d]<63:32> else D[d]<31:0>;
// MemA[address+4,4] = if BigEndian() then D[d]<31:0> else D[d]<63:32>; // MemA[address+4,4] = if BigEndian() then D[d]<31:0> else D[d]<63:32>;
uint64_t data = uint64_t data =
ReadRegisterUnsigned(eRegisterKindDWARF, start_reg + d, 0, &success); ReadRegisterUnsigned(eRegisterKindDWARF, start_reg + d, 0, &success);
if (!success) if (!success)
return false; return false;
if (GetByteOrder() == eByteOrderBig) { if (GetByteOrder() == eByteOrderBig) {
if (!MemAWrite(context, address, Bits64(data, 63, 32), addr_byte_size)) if (!MemAWrite(context, address, Bits64(data, 63, 32), addr_byte_size))
return false; return false;
context.SetRegisterToRegisterPlusOffset(data_reg, base_reg, context.SetRegisterToRegisterPlusOffset(*data_reg, *base_reg,
(address + 4) - Rn); (address + 4) - Rn);
if (!MemAWrite(context, address + 4, Bits64(data, 31, 0), if (!MemAWrite(context, address + 4, Bits64(data, 31, 0),
addr_byte_size)) addr_byte_size))
return false; return false;
} else { } else {
if (!MemAWrite(context, address, Bits64(data, 31, 0), addr_byte_size)) if (!MemAWrite(context, address, Bits64(data, 31, 0), addr_byte_size))
return false; return false;
context.SetRegisterToRegisterPlusOffset(data_reg, base_reg, context.SetRegisterToRegisterPlusOffset(*data_reg, *base_reg,
(address + 4) - Rn); (address + 4) - Rn);
if (!MemAWrite(context, address + 4, Bits64(data, 63, 32), if (!MemAWrite(context, address + 4, Bits64(data, 63, 32),
addr_byte_size)) addr_byte_size))
return false; return false;
} }
} }
} }
return true; return true;
▲ Show 20 Lines • Show All 91 Lines • ▼ Show 20 Lines case eEncodingA1: {
if ((d + regs) > 32) if ((d + regs) > 32)
return false; return false;
} break; } break;
default: default:
return false; return false;
} }
RegisterInfo base_reg; llvm::Optional<RegisterInfo> base_reg =
GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n, base_reg); GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n);
uint32_t Rn = ReadCoreReg(n, &success); uint32_t Rn = ReadCoreReg(n, &success);
if (!success) if (!success)
return false; return false;
// address = R[n]; if (address MOD alignment) != 0 then // address = R[n]; if (address MOD alignment) != 0 then
// GenerateAlignmentException(); // GenerateAlignmentException();
addr_t address = Rn; addr_t address = Rn;
Show All 10 Lines if (wback) {
uint32_t offset; uint32_t offset;
if (register_index) if (register_index)
offset = Rm; offset = Rm;
else else
offset = 8 * regs; offset = 8 * regs;
uint32_t value = Rn + offset; uint32_t value = Rn + offset;
context.type = eContextAdjustBaseRegister; context.type = eContextAdjustBaseRegister;
context.SetRegisterPlusOffset(base_reg, offset); context.SetRegisterPlusOffset(*base_reg, offset);
if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + n, if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + n,
value)) value))
return false; return false;
} }
// for r = 0 to regs-1 // for r = 0 to regs-1
for (uint32_t r = 0; r < regs; ++r) { for (uint32_t r = 0; r < regs; ++r) {
// for e = 0 to elements-1 // for e = 0 to elements-1
uint64_t assembled_data = 0; uint64_t assembled_data = 0;
for (uint32_t e = 0; e < elements; ++e) { for (uint32_t e = 0; e < elements; ++e) {
// Elem[D[d+r],e,esize] = MemU[address,ebytes]; // Elem[D[d+r],e,esize] = MemU[address,ebytes];
context.type = eContextRegisterLoad; context.type = eContextRegisterLoad;
context.SetRegisterPlusOffset(base_reg, address - Rn); context.SetRegisterPlusOffset(*base_reg, address - Rn);
uint64_t data = MemURead(context, address, ebytes, 0, &success); uint64_t data = MemURead(context, address, ebytes, 0, &success);
if (!success) if (!success)
return false; return false;
assembled_data = assembled_data =
(data << (e * esize)) | (data << (e * esize)) |
assembled_data; // New data goes to the left of existing data assembled_data; // New data goes to the left of existing data
▲ Show 20 Lines • Show All 108 Lines • ▼ Show 20 Lines case eEncodingA1: {
return false; return false;
} break; } break;
default: default:
return false; return false;
} }
RegisterInfo base_reg;
GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n, base_reg);
uint32_t Rn = ReadCoreReg(n, &success); uint32_t Rn = ReadCoreReg(n, &success);
if (!success) if (!success)
return false; return false;
// address = R[n]; if (address MOD alignment) != 0 then // address = R[n]; if (address MOD alignment) != 0 then
// GenerateAlignmentException(); // GenerateAlignmentException();
addr_t address = Rn; addr_t address = Rn;
if ((address % alignment) != 0) if ((address % alignment) != 0)
Show All 10 Lines if (wback) {
if (register_index) if (register_index)
offset = Rm; offset = Rm;
else else
offset = ebytes; offset = ebytes;
uint32_t value = Rn + offset; uint32_t value = Rn + offset;
context.type = eContextAdjustBaseRegister; context.type = eContextAdjustBaseRegister;
context.SetRegisterPlusOffset(base_reg, offset); llvm::Optional<RegisterInfo> base_reg =
GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n);
context.SetRegisterPlusOffset(*base_reg, offset);
if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + n, if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + n,
value)) value))
return false; return false;
} }
// Elem[D[d],index,esize] = MemU[address,ebytes]; // Elem[D[d],index,esize] = MemU[address,ebytes];
uint32_t element = MemURead(context, address, esize, 0, &success); uint32_t element = MemURead(context, address, esize, 0, &success);
▲ Show 20 Lines • Show All 120 Lines • ▼ Show 20 Lines case eEncodingA1: {
return false; return false;
} break; } break;
default: default:
return false; return false;
} }
RegisterInfo base_reg; llvm::Optional<RegisterInfo> base_reg =
GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n, base_reg); GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n);
uint32_t Rn = ReadCoreReg(n, &success); uint32_t Rn = ReadCoreReg(n, &success);
if (!success) if (!success)
return false; return false;
// address = R[n]; if (address MOD alignment) != 0 then // address = R[n]; if (address MOD alignment) != 0 then
// GenerateAlignmentException(); // GenerateAlignmentException();
addr_t address = Rn; addr_t address = Rn;
Show All 9 Lines if (wback) {
uint32_t offset; uint32_t offset;
if (register_index) if (register_index)
offset = Rm; offset = Rm;
else else
offset = 8 * regs; offset = 8 * regs;
context.type = eContextAdjustBaseRegister; context.type = eContextAdjustBaseRegister;
context.SetRegisterPlusOffset(base_reg, offset); context.SetRegisterPlusOffset(*base_reg, offset);
if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + n, if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + n,
Rn + offset)) Rn + offset))
return false; return false;
} }
RegisterInfo data_reg;
context.type = eContextRegisterStore; context.type = eContextRegisterStore;
// for r = 0 to regs-1 // for r = 0 to regs-1
for (uint32_t r = 0; r < regs; ++r) { for (uint32_t r = 0; r < regs; ++r) {
GetRegisterInfo(eRegisterKindDWARF, dwarf_d0 + d + r, data_reg); llvm::Optional<RegisterInfo> data_reg =
GetRegisterInfo(eRegisterKindDWARF, dwarf_d0 + d + r);
uint64_t register_data = ReadRegisterUnsigned( uint64_t register_data = ReadRegisterUnsigned(
eRegisterKindDWARF, dwarf_d0 + d + r, 0, &success); eRegisterKindDWARF, dwarf_d0 + d + r, 0, &success);
if (!success) if (!success)
return false; return false;
// for e = 0 to elements-1 // for e = 0 to elements-1
for (uint32_t e = 0; e < elements; ++e) { for (uint32_t e = 0; e < elements; ++e) {
// MemU[address,ebytes] = Elem[D[d+r],e,esize]; // MemU[address,ebytes] = Elem[D[d+r],e,esize];
uint64_t word = Bits64(register_data, ((e + 1) * esize) - 1, e * esize); uint64_t word = Bits64(register_data, ((e + 1) * esize) - 1, e * esize);
context.SetRegisterToRegisterPlusOffset(data_reg, base_reg, context.SetRegisterToRegisterPlusOffset(*data_reg, *base_reg,
address - Rn); address - Rn);
if (!MemUWrite(context, address, word, ebytes)) if (!MemUWrite(context, address, word, ebytes))
return false; return false;
// address = address + ebytes; // address = address + ebytes;
address = address + ebytes; address = address + ebytes;
} }
} }
▲ Show 20 Lines • Show All 101 Lines • ▼ Show 20 Lines case eEncodingA1: {
if (n == 15) if (n == 15)
return false; return false;
} break; } break;
default: default:
return false; return false;
} }
RegisterInfo base_reg; llvm::Optional<RegisterInfo> base_reg =
GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n, base_reg); GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n);
uint32_t Rn = ReadCoreReg(n, &success); uint32_t Rn = ReadCoreReg(n, &success);
if (!success) if (!success)
return false; return false;
// address = R[n]; if (address MOD alignment) != 0 then // address = R[n]; if (address MOD alignment) != 0 then
// GenerateAlignmentException(); // GenerateAlignmentException();
addr_t address = Rn; addr_t address = Rn;
Show All 9 Lines if (wback) {
uint32_t offset; uint32_t offset;
if (register_index) if (register_index)
offset = Rm; offset = Rm;
else else
offset = ebytes; offset = ebytes;
context.type = eContextAdjustBaseRegister; context.type = eContextAdjustBaseRegister;
context.SetRegisterPlusOffset(base_reg, offset); context.SetRegisterPlusOffset(*base_reg, offset);
if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + n, if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + n,
Rn + offset)) Rn + offset))
return false; return false;
} }
// MemU[address,ebytes] = Elem[D[d],index,esize]; // MemU[address,ebytes] = Elem[D[d],index,esize];
uint64_t register_data = uint64_t register_data =
ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_d0 + d, 0, &success); ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_d0 + d, 0, &success);
if (!success) if (!success)
return false; return false;
uint64_t word = uint64_t word =
Bits64(register_data, ((index + 1) * esize) - 1, index * esize); Bits64(register_data, ((index + 1) * esize) - 1, index * esize);
RegisterInfo data_reg; llvm::Optional<RegisterInfo> data_reg =
GetRegisterInfo(eRegisterKindDWARF, dwarf_d0 + d, data_reg); GetRegisterInfo(eRegisterKindDWARF, dwarf_d0 + d);
context.type = eContextRegisterStore; context.type = eContextRegisterStore;
context.SetRegisterToRegisterPlusOffset(data_reg, base_reg, address - Rn); context.SetRegisterToRegisterPlusOffset(*data_reg, *base_reg, address - Rn);
if (!MemUWrite(context, address, word, ebytes)) if (!MemUWrite(context, address, word, ebytes))
return false; return false;
} }
return true; return true;
} }
// A8.6.309 VLD1 (single element to all lanes) This instruction loads one // A8.6.309 VLD1 (single element to all lanes) This instruction loads one
▲ Show 20 Lines • Show All 62 Lines • ▼ Show 20 Lines case eEncodingA1: {
if (n == 15) if (n == 15)
return false; return false;
} break; } break;
default: default:
return false; return false;
} }
RegisterInfo base_reg;
GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n, base_reg);
uint32_t Rn = ReadCoreReg(n, &success); uint32_t Rn = ReadCoreReg(n, &success);
if (!success) if (!success)
return false; return false;
// address = R[n]; if (address MOD alignment) != 0 then // address = R[n]; if (address MOD alignment) != 0 then
// GenerateAlignmentException(); // GenerateAlignmentException();
addr_t address = Rn; addr_t address = Rn;
if ((address % alignment) != 0) if ((address % alignment) != 0)
return false; return false;
EmulateInstruction::Context context; EmulateInstruction::Context context;
// if wback then R[n] = R[n] + (if register_index then R[m] else ebytes); // if wback then R[n] = R[n] + (if register_index then R[m] else ebytes);
if (wback) { if (wback) {
uint32_t Rm = ReadCoreReg(m, &success); uint32_t Rm = ReadCoreReg(m, &success);
if (!success) if (!success)
return false; return false;
uint32_t offset; uint32_t offset;
if (register_index) if (register_index)
offset = Rm; offset = Rm;
else else
offset = ebytes; offset = ebytes;
context.type = eContextAdjustBaseRegister; context.type = eContextAdjustBaseRegister;
context.SetRegisterPlusOffset(base_reg, offset); llvm::Optional<RegisterInfo> base_reg =
GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n);
context.SetRegisterPlusOffset(*base_reg, offset);
if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + n, if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + n,
Rn + offset)) Rn + offset))
return false; return false;
} }
// replicated_element = Replicate(MemU[address,ebytes], elements); // replicated_element = Replicate(MemU[address,ebytes], elements);
▲ Show 20 Lines • Show All 1,874 Lines • Show Last 20 Lines