[LoongArch] Support 'generic' as a valid CPU name

[xen0n]

Summary

As the LoongArch port is largely modeled after RISCV it has the same
behavior of not accepting generic as a CPU name. For better
compatibility with consumers of LLVM (e.g. mesa) follow D121149's suit
and treat generic the same as an empty CPU name.

[SixWeining]

LGTM. Thanks.

EDIT: Should we add some tests for this change?

[xen0n]

add testcase

[SixWeining]

LGTM. Thanks.

llvm/lib/Target/LoongArch/LoongArch.td

 
 //===----------------------------------------------------------------------===//
 // LoongArch processors supported.
 //===----------------------------------------------------------------------===//
 
 def : ProcessorModel<"generic-la32", NoSchedModel, []>;
 def : ProcessorModel<"generic-la64", NoSchedModel, [Feature64Bit]>;
 
+// Support generic for compatibility with other targets. The triple will be used
+// to change to the appropriate la32/la64 version.
+def : ProcessorModel<"generic", NoSchedModel, []>;
+
 def : ProcessorModel<"la464", NoSchedModel, [Feature64Bit,
                                              FeatureExtLASX,
                                              FeatureExtLVZ,
                                              FeatureExtLBT]>;
 
 //===----------------------------------------------------------------------===//
 // Define the LoongArch target.
 //===----------------------------------------------------------------------===//

llvm/lib/Target/LoongArch/LoongArchSubtarget.cpp

 #include "LoongArchGenSubtargetInfo.inc"
 
 void LoongArchSubtarget::anchor() {}
 
 LoongArchSubtarget &LoongArchSubtarget::initializeSubtargetDependencies(
     const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS,
     StringRef ABIName) {
   bool Is64Bit = TT.isArch64Bit();
-  if (CPU.empty())
+  if (CPU.empty() || CPU == "generic")
     CPU = Is64Bit ? "generic-la64" : "generic-la32";
 
   if (TuneCPU.empty())
     TuneCPU = CPU;
 
   ParseSubtargetFeatures(CPU, TuneCPU, FS);
   if (Is64Bit) {
     GRLenVT = MVT::i64;

llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCTargetDesc.cpp

 static MCInstrInfo *createLoongArchMCInstrInfo() {
   MCInstrInfo *X = new MCInstrInfo();
   InitLoongArchMCInstrInfo(X);
   return X;
 }
 
 static MCSubtargetInfo *
 createLoongArchMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
-  if (CPU.empty())
+  if (CPU.empty() || CPU == "generic")
     CPU = TT.isArch64Bit() ? "la464" : "generic-la32";
   return createLoongArchMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
 }
 
 static MCAsmInfo *createLoongArchMCAsmInfo(const MCRegisterInfo &MRI,
                                            const Triple &TT,
                                            const MCTargetOptions &Options) {
   MCAsmInfo *MAI = new LoongArchMCAsmInfo(TT);

llvm/test/CodeGen/LoongArch/cpu-name-generic.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mcpu=generic < %s \
+; RUN:   | FileCheck %s --check-prefix=LA32
+; RUN: llc --mtriple=loongarch32 --mcpu=generic-la32 < %s \
+; RUN:   | FileCheck %s --check-prefix=LA32
+; RUN: llc --mtriple=loongarch64 --mcpu=generic < %s \
+; RUN:   | FileCheck %s --check-prefix=LA64
+; RUN: llc --mtriple=loongarch64 --mcpu=generic-la64 < %s \
+; RUN:   | FileCheck %s --check-prefix=LA64
+
+;; The CPU name "generic" should map to the corresponding concrete names
+;; according to the target triple's bitness.
+define i64 @f(i64 signext %a, i64 signext %b) {
+; LA32-LABEL: f:
+; LA32:       # %bb.0:
+; LA32-NEXT:    add.w $a1, $a1, $a3
+; LA32-NEXT:    add.w $a2, $a0, $a2
+; LA32-NEXT:    sltu $a0, $a2, $a0
+; LA32-NEXT:    add.w $a1, $a1, $a0
+; LA32-NEXT:    move $a0, $a2
+; LA32-NEXT:    ret
+;
+; LA64-LABEL: f:
+; LA64:       # %bb.0:
+; LA64-NEXT:    add.d $a0, $a0, $a1
+; LA64-NEXT:    ret
+  %1 = add nsw i64 %a, %b
+  ret i64 %1
+}