[LoongArch] Add support for llvm.trap and llvm.debugtrap

[xen0n]

Summary

Similar to D69390 for RISCV, use a guaranteed non-existing insn for
llvm.trap and the break insn for llvm.debugtrap.

[xry111]

I have some doubt here: on x86_64 a trap leads to SIGILL, but a debugtrap leads to SIGTRAP. Not sure if they have a good reason or this is just for satisfying some "habit" of x86 programmers.

If we want a SIGILL we can amswap.w $r0, $r0, $r0.

[xry111]

In D134365#3806143, @xry111 wrote:

I have some doubt here: on x86_64 a trap leads to SIGILL, but a debugtrap leads to SIGTRAP. Not sure if they have a good reason or this is just for satisfying some "habit" of x86 programmers.

If we want a SIGILL we can amswap.w $r0, $r0, $r0.

I used amswap.w $r0, $r0, $r1 in my early work. But again I'm not sure if we want a SIGTRAP of SIGILL (or something else) here.

[SixWeining]

In D134365#3806160, @xry111 wrote:

In D134365#3806143, @xry111 wrote:

I have some doubt here: on x86_64 a trap leads to SIGILL, but a debugtrap leads to SIGTRAP. Not sure if they have a good reason or this is just for satisfying some "habit" of x86 programmers.

If we want a SIGILL we can amswap.w $r0, $r0, $r0.

I used amswap.w $r0, $r0, $r1 in my early work. But again I'm not sure if we want a SIGTRAP of SIGILL (or something else) here.

Do you mean when rd == rj (but not rd == rk)?

[xen0n]

In D134365#3806160, @xry111 wrote:

In D134365#3806143, @xry111 wrote:

I have some doubt here: on x86_64 a trap leads to SIGILL, but a debugtrap leads to SIGTRAP. Not sure if they have a good reason or this is just for satisfying some "habit" of x86 programmers.

If we want a SIGILL we can amswap.w $r0, $r0, $r0.

I used amswap.w $r0, $r0, $r1 in my early work.

It's a shame the ISA manual didn't give us a bit pattern guaranteed to cause INE (hence SIGILL). In theory all-zeros would work but I got told (I believe at least by FlyGoat) that apparently some engineering sample batches of 3A5000 treated the all-zeros insn word as valid, so it's probably better to be extra safe and just avoid it.

But again I'm not sure if we want a SIGTRAP of SIGILL (or something else) here.

I'd really like to differentiate but according to glibc the break 0 is used as the ultimate fallback for abort. Still a shame the two things have to be conflated if strictly implementing the specs...

[xry111]

In D134365#3811041, @SixWeining wrote:

In D134365#3806160, @xry111 wrote:

In D134365#3806143, @xry111 wrote:

I have some doubt here: on x86_64 a trap leads to SIGILL, but a debugtrap leads to SIGTRAP. Not sure if they have a good reason or this is just for satisfying some "habit" of x86 programmers.

If we want a SIGILL we can amswap.w $r0, $r0, $r0.

I used amswap.w $r0, $r0, $r1 in my early work. But again I'm not sure if we want a SIGTRAP of SIGILL (or something else) here.

Do you mean when rd == rj (but not rd == rk)?

It's the only way mentioned by the ISA manual to reliably trigger an INE. IIRC on a 3A5000LL amswap.w $r0, $r0, $r0 also works but the manual is some sort of cryptic about the behavior when rd == rj and rd == rk, so I avoided rd == rk.

[xry111]

In D134365#3811102, @xen0n wrote:

But again I'm not sure if we want a SIGTRAP of SIGILL (or something else) here.

I'd really like to differentiate but according to glibc the break 0 is used as the ultimate fallback for abort. Still a shame the two things have to be conflated if strictly implementing the specs...

And GCC is generating break 0 for __builtin_trap(), while LLVM translates it to llvm.trap (not debugtrap).

Perhaps using break 0 for both is OK, but I just wonder if there is a better way.

[xry111]

RISC-V uses an undefined instruction for llvm.trap. AArch64 uses different break codes for trap and debugtrap.

I think we need to either request an instruction "must be undefined", or request a documentation of break codes. Note that break 7 is already used for a SIGFPE (when -mcheck-zero-division) and the number 7 is not documented anywhere AFAIK...

[xen0n]

In D134365#3814862, @xry111 wrote:

RISC-V uses an undefined instruction for llvm.trap. AArch64 uses different break codes for trap and debugtrap.

I think we need to either request an instruction "must be undefined", or request a documentation of break codes. Note that break 7 is already used for a SIGFPE (when -mcheck-zero-division) and the number 7 is not documented anywhere AFAIK...

Look at /usr/include/asm/break.h in your LoongArch sysroot for the definitions... inherited from MIPS, of course. Unfortunately there's no reservation about an "abort" kind... maybe I should ask and try to stuff one into Linux before amending the patch to make use of that.

[xen0n]

Adopt @xry111's approach to llvm.trap with guaranteed INE-ing insn.

[SixWeining]

LGTM. But let's wait @xry111.

[xry111]

Trap part LGTM. But for other parts I have to admit I don't have enough knowledge to review...

llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp

LoongArchTargetLowering::LoongArchTargetLowering(const TargetMachine &TM,
 
   // TODO: add necessary setOperationAction calls later.
   setOperationAction(ISD::SHL_PARTS, GRLenVT, Custom);
   setOperationAction(ISD::SRA_PARTS, GRLenVT, Custom);
   setOperationAction(ISD::SRL_PARTS, GRLenVT, Custom);
   setOperationAction(ISD::FP_TO_SINT, GRLenVT, Custom);
   setOperationAction(ISD::ROTL, GRLenVT, Expand);
   setOperationAction(ISD::CTPOP, GRLenVT, Expand);
+  setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
+  setOperationAction(ISD::TRAP, MVT::Other, Legal);
 
   setOperationAction({ISD::GlobalAddress, ISD::BlockAddress, ISD::ConstantPool,
                       ISD::JumpTable},
                      GRLenVT, Custom);
 
   setOperationAction(ISD::GlobalTLSAddress, GRLenVT, Custom);
 
   setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);

llvm/lib/Target/LoongArch/LoongArchInstrInfo.td

 def : PatGprImm<or, ORI, uimm12>;
 def : PatGprGpr<xor, XOR>;
 def : PatGprImm<xor, XORI, uimm12>;
 def : Pat<(not GPR:$rj), (NOR GPR:$rj, R0)>;
 def : Pat<(not (or GPR:$rj, GPR:$rk)), (NOR GPR:$rj, GPR:$rk)>;
 def : Pat<(or GPR:$rj, (not GPR:$rk)), (ORN GPR:$rj, GPR:$rk)>;
 def : Pat<(and GPR:$rj, (not GPR:$rk)), (ANDN GPR:$rj, GPR:$rk)>;
 
+/// Traps
+
+// We lower `trap` to `amswap.w rd:$r0, rk:$r1, rj:$r0`, as this is guaranteed
+// to trap with an INE (non-existent on LA32, explicitly documented to INE on
+// LA64). And the resulting signal is different from `debugtrap` like on some
+// other existing ports so programs/porters might have an easier time.
+def PseudoUNIMP : Pseudo<(outs), (ins), [(trap)]>,
+                  PseudoInstExpansion<(AMSWAP_W R0, R1, R0)>;
+
+// We lower `debugtrap` to `break 0`, as this is guaranteed to exist and work,
+// even for LA32 Primary. Also, because so far the ISA does not provide a
+// specific trap instruction/kind exclusively for alerting the debugger,
+// every other project uses the generic immediate of 0 for this.
+def : Pat<(debugtrap), (BREAK 0)>;
+
 /// Bit counting operations
 
 let Predicates = [IsLA64] in {
 def : PatGpr<ctlz, CLZ_D>;
 def : PatGpr<cttz, CTZ_D>;
 def : Pat<(ctlz (not GPR:$rj)), (CLO_D GPR:$rj)>;
 def : Pat<(cttz (not GPR:$rj)), (CTO_D GPR:$rj)>;
 def : PatGpr<loongarch_clzw, CLZ_W>;

llvm/test/CodeGen/LoongArch/trap.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --verify-machineinstrs < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch64 --verify-machineinstrs < %s | FileCheck %s
+
+;; Verify that we lower @llvm.trap() and @llvm.debugtrap() correctly.
+
+declare void @llvm.trap()
+declare void @llvm.debugtrap()
+
+define void @test_trap() nounwind {
+; CHECK-LABEL: test_trap:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    amswap.w $zero, $ra, $zero
+; CHECK-NEXT:    ret
+  tail call void @llvm.trap()
+  ret void
+}
+
+define void @test_debugtrap() nounwind {
+; CHECK-LABEL: test_debugtrap:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    break 0
+; CHECK-NEXT:    ret
+  tail call void @llvm.debugtrap()
+  ret void
+}