[Sparc] Fix useDeprecatedPositionallyEncodedOperands errors.

[jyknight]

Summary

This is a follow-on to https://reviews.llvm.org/D134073.

It renames a few fields to have consistent names, as well as renaming
operands to match the field names.

Behavior is unchanged by this cleanup. (The only generated code change
is for the disassembler for LDSTUB/LDSTUBA, but in both old and new
versions, it fails to add enough operands, and thus triggers a runtime
abort. I will address that bug in a future commit.)

[MaskRay]

In the build directory, I use rsync -aR -f '+ */' -f '+ *.inc' -f '- *' ./lib/Target/Sparc /tmp/new/ (and /tmp/old) to compare *.inc files before and after the change.

LDSTUBrr/LDSTUBri have differences as mentioned. Is the case 74: difference expected?

% diff -ur /tmp/{old,new}
diff -ur /tmp/old/lib/Target/Sparc/SparcGenDisassemblerTables.inc /tmp/new/lib/Target/Sparc/SparcGenDisassemblerTables.inc
--- /tmp/old/lib/Target/Sparc/SparcGenDisassemblerTables.inc    2022-10-25 15:43:12.603059757 -0700
+++ /tmp/new/lib/Target/Sparc/SparcGenDisassemblerTables.inc    2022-10-25 15:44:15.299347605 -0700
@@ -1511,9 +1511,9 @@
 /* 6918 */    MCD::OPC_ExtractField, 13, 1,  // Inst{13} ...
 /* 6921 */    MCD::OPC_FilterValue, 0, 11, 0, 0, // Skip to: 6937
 /* 6926 */    MCD::OPC_CheckField, 5, 8, 0, 99, 4, 0, // Skip to: 8056
-/* 6933 */    MCD::OPC_Decode, 174, 4, 4, // Opcode: LDSTUBrr
+/* 6933 */    MCD::OPC_Decode, 174, 4, 17, // Opcode: LDSTUBrr
 /* 6937 */    MCD::OPC_FilterValue, 1, 90, 4, 0, // Skip to: 8056
-/* 6942 */    MCD::OPC_Decode, 173, 4, 4, // Opcode: LDSTUBri
+/* 6942 */    MCD::OPC_Decode, 173, 4, 17, // Opcode: LDSTUBri
 /* 6946 */    MCD::OPC_FilterValue, 14, 28, 0, 0, // Skip to: 6979
 /* 6951 */    MCD::OPC_ExtractField, 13, 1,  // Inst{13} ...
 /* 6954 */    MCD::OPC_FilterValue, 0, 11, 0, 0, // Skip to: 6970
@@ -2312,6 +2312,8 @@
     if (DecodeSWAP(MI, insn, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
     return S;
   case 74:
+    tmp = fieldFromInstruction(insn, 25, 5);
+    if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
     tmp = fieldFromInstruction(insn, 5, 8);
     MI.addOperand(MCOperand::createImm(tmp));
     return S;

[jyknight]

In D134201#3883934, @MaskRay wrote:

LDSTUBrr/LDSTUBri have differences as mentioned. Is the case 74: difference expected?

Yep, that's expected (the decoder currently just silently ignores non-matching operands, and "dst" didn't match anything, but "rd" does -- so now it emits (correctly) an additional operand in decoding). It's still broken, as mentioned, though, since the sub-operands aren't supported in decoding yet. Patch coming soon will address that and make other improvements here.

llvm/lib/Target/Sparc/Sparc.td

 // Register File, Calling Conv, Instruction Descriptions
 //===----------------------------------------------------------------------===//
 
 include "SparcRegisterInfo.td"
 include "SparcCallingConv.td"
 include "SparcSchedule.td"
 include "SparcInstrInfo.td"
 
-def SparcInstrInfo : InstrInfo {
-  let useDeprecatedPositionallyEncodedOperands = 1;
-}
+def SparcInstrInfo : InstrInfo;
 
 def SparcAsmParser : AsmParser {
   bit ShouldEmitMatchRegisterName = 0;
 }
 
 //===----------------------------------------------------------------------===//
 // SPARC processors supported.
 //===----------------------------------------------------------------------===//

llvm/lib/Target/Sparc/SparcInstr64Bit.td

 
 // Register-register instructions.
 let isCodeGenOnly = 1 in {
 defm ANDX    : F3_12<"and", 0b000001, and, I64Regs, i64, i64imm>;
 defm ORX     : F3_12<"or",  0b000010, or,  I64Regs, i64, i64imm>;
 defm XORX    : F3_12<"xor", 0b000011, xor, I64Regs, i64, i64imm>;
 
 def ANDXNrr  : F3_1<2, 0b000101,
-                 (outs I64Regs:$dst), (ins I64Regs:$b, I64Regs:$c),
-                 "andn $b, $c, $dst",
-                 [(set i64:$dst, (and i64:$b, (not i64:$c)))]>;
+                 (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2),
+                 "andn $rs1, $rs2, $rd",
+                 [(set i64:$rd, (and i64:$rs1, (not i64:$rs2)))]>;
 def ORXNrr   : F3_1<2, 0b000110,
-                 (outs I64Regs:$dst), (ins I64Regs:$b, I64Regs:$c),
-                 "orn $b, $c, $dst",
-                 [(set i64:$dst, (or i64:$b, (not i64:$c)))]>;
+                 (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2),
+                 "orn $rs1, $rs2, $rd",
+                 [(set i64:$rd, (or i64:$rs1, (not i64:$rs2)))]>;
 def XNORXrr  : F3_1<2, 0b000111,
-                   (outs I64Regs:$dst), (ins I64Regs:$b, I64Regs:$c),
-                   "xnor $b, $c, $dst",
-                   [(set i64:$dst, (not (xor i64:$b, i64:$c)))]>;
+                   (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2),
+                   "xnor $rs1, $rs2, $rd",
+                   [(set i64:$rd, (not (xor i64:$rs1, i64:$rs2)))]>;
 
 defm ADDX    : F3_12<"add", 0b000000, add, I64Regs, i64, i64imm>;
 defm SUBX    : F3_12<"sub", 0b000100, sub, I64Regs, i64, i64imm>;
 
 def TLS_ADDXrr : F3_1<2, 0b000000, (outs I64Regs:$rd),
                    (ins I64Regs:$rs1, I64Regs:$rs2, TailRelocSymTLSAdd:$sym),
                    "add $rs1, $rs2, $rd, $sym",
                    [(set i64:$rd,
                        (tlsadd i64:$rs1, i64:$rs2, tglobaltlsaddr:$sym))]>;
 
 // "LEA" form of add
 def LEAX_ADDri : F3_2<2, 0b000000,
-                     (outs I64Regs:$dst), (ins MEMri:$addr),
-                     "add ${addr:arith}, $dst",
-                     [(set iPTR:$dst, ADDRri:$addr)]>;
+                     (outs I64Regs:$rd), (ins (MEMri $rs1, $simm13):$addr),
+                     "add ${addr:arith}, $rd",
+                     [(set iPTR:$rd, ADDRri:$addr)]>;
 }
 
 def : Pat<(SPcmpicc i64:$a, i64:$b), (CMPrr $a, $b)>;
 def : Pat<(SPcmpicc i64:$a, (i64 simm13:$b)), (CMPri $a, (as_i32imm $b))>;
 def : Pat<(i64 (ctpop i64:$src)), (POPCrr $src)>;
 
 } // Predicates = [Is64Bit]
 

 let Predicates = [Is64Bit] in {
 
 // 64-bit loads.
 let DecoderMethod = "DecodeLoadInt" in
   defm LDX   : Load<"ldx", 0b001011, load, I64Regs, i64>;
 
 let mayLoad = 1, isAsmParserOnly = 1 in {
   def TLS_LDXrr : F3_1<3, 0b001011,
-                       (outs IntRegs:$dst),
-                       (ins MEMrr:$addr, TailRelocSymTLSLoad:$sym),
-                       "ldx [$addr], $dst, $sym",
-                       [(set i64:$dst,
+                       (outs IntRegs:$rd),
+                       (ins (MEMrr $rs1, $rs2):$addr, TailRelocSymTLSLoad:$sym),
+                       "ldx [$addr], $rd, $sym",
+                       [(set i64:$rd,
                            (tlsld ADDRrr:$addr, tglobaltlsaddr:$sym))]>;
   def GDOP_LDXrr : F3_1<3, 0b001011,
-                       (outs I64Regs:$dst),
-                       (ins MEMrr:$addr, TailRelocSymGOTLoad:$sym),
-                       "ldx [$addr], $dst, $sym",
-                       [(set i64:$dst,
+                       (outs I64Regs:$rd),
+                       (ins (MEMrr $rs1, $rs2):$addr, TailRelocSymGOTLoad:$sym),
+                       "ldx [$addr], $rd, $sym",
+                       [(set i64:$rd,
                            (load_gdop ADDRrr:$addr, tglobaladdr:$sym))]>;
 }
 
 // Extending loads to i64.
 def : Pat<(i64 (zextloadi1 ADDRrr:$addr)), (LDUBrr ADDRrr:$addr)>;
 def : Pat<(i64 (zextloadi1 ADDRri:$addr)), (LDUBri ADDRri:$addr)>;
 def : Pat<(i64 (extloadi1 ADDRrr:$addr)), (LDUBrr ADDRrr:$addr)>;
 def : Pat<(i64 (extloadi1 ADDRri:$addr)), (LDUBri ADDRri:$addr)>;

llvm/lib/Target/Sparc/SparcInstrInfo.td

 
 def SparcMEMriAsmOperand : AsmOperandClass {
   let Name = "MEMri";
   let ParserMethod = "parseMEMOperand";
 }
 
 def MEMrr : Operand<iPTR> {
   let PrintMethod = "printMemOperand";
-  let MIOperandInfo = (ops ptr_rc, ptr_rc);
+  let MIOperandInfo = (ops ptr_rc:$rs1, ptr_rc:$rs2);
   let ParserMatchClass = SparcMEMrrAsmOperand;
 }
 def MEMri : Operand<iPTR> {
   let PrintMethod = "printMemOperand";
-  let MIOperandInfo = (ops ptr_rc, i32imm);
+  let MIOperandInfo = (ops ptr_rc:$rs1, i32imm:$simm13);
   let ParserMatchClass = SparcMEMriAsmOperand;
 }
 
 // Represents a tail relocation operand for instructions such as add, ld, call.
 class SparcTailRelocSymAsmOperand<string Kind> : AsmOperandClass {
   let Name = "TailRelocSym" # Kind;
   let RenderMethod = "addTailRelocSymOperands";
   let PredicateMethod = "isTailRelocSym";
def ri  : F3_2<2, Op3Val,
                  !strconcat(OpcStr, " $rs1, $simm13, $rd"), [],
                  itin>;
 }
 
 // Load multiclass - Define both Reg+Reg/Reg+Imm patterns in one shot.
 multiclass Load<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode,
            RegisterClass RC, ValueType Ty, InstrItinClass itin = IIC_iu_instr> {
   def rr  : F3_1<3, Op3Val,
-                 (outs RC:$dst), (ins MEMrr:$addr),
-                 !strconcat(OpcStr, " [$addr], $dst"),
-                 [(set Ty:$dst, (OpNode ADDRrr:$addr))],
+                 (outs RC:$rd), (ins (MEMrr $rs1, $rs2):$addr),
+                 !strconcat(OpcStr, " [$addr], $rd"),
+                 [(set Ty:$rd, (OpNode ADDRrr:$addr))],
                  itin>;
   def ri  : F3_2<3, Op3Val,
-                 (outs RC:$dst), (ins MEMri:$addr),
-                 !strconcat(OpcStr, " [$addr], $dst"),
-                 [(set Ty:$dst, (OpNode ADDRri:$addr))],
+                 (outs RC:$rd), (ins (MEMri $rs1, $simm13):$addr),
+                 !strconcat(OpcStr, " [$addr], $rd"),
+                 [(set Ty:$rd, (OpNode ADDRri:$addr))],
                  itin>;
 }
 
 // TODO: Instructions of the LoadASI class are currently asm only; hooking up
 // CodeGen's address spaces to use these is a future task.
 class LoadASI<string OpcStr, bits<6> Op3Val, RegisterClass RC> :
-  F3_1_asi<3, Op3Val, (outs RC:$dst), (ins MEMrr:$addr, i8imm:$asi),
-                !strconcat(OpcStr, "a [$addr] $asi, $dst"),
+  F3_1_asi<3, Op3Val, (outs RC:$rd), (ins (MEMrr $rs1, $rs2):$addr, i8imm:$asi),
+                !strconcat(OpcStr, "a [$addr] $asi, $rd"),
                 []>;
 
 // LoadA multiclass - As above, but also define alternate address space variant
 multiclass LoadA<string OpcStr, bits<6> Op3Val, bits<6> LoadAOp3Val,
                  SDPatternOperator OpNode, RegisterClass RC, ValueType Ty,
                  InstrItinClass itin = NoItinerary> :
              Load<OpcStr, Op3Val, OpNode, RC, Ty, itin> {
   def Arr  : LoadASI<OpcStr, LoadAOp3Val, RC>;
 }
 
 // The LDSTUB instruction is supported for asm only.
 // It is unlikely that general-purpose code could make use of it.
 // CAS is preferred for sparc v9.
-def LDSTUBrr : F3_1<3, 0b001101, (outs IntRegs:$dst), (ins MEMrr:$addr),
-                    "ldstub [$addr], $dst", []>;
-def LDSTUBri : F3_2<3, 0b001101, (outs IntRegs:$dst), (ins MEMri:$addr),
-                    "ldstub [$addr], $dst", []>;
-def LDSTUBArr : F3_1_asi<3, 0b011101, (outs IntRegs:$dst),
-                         (ins MEMrr:$addr, i8imm:$asi),
-                         "ldstuba [$addr] $asi, $dst", []>;
+def LDSTUBrr : F3_1<3, 0b001101, (outs IntRegs:$rd), (ins (MEMrr $rs1, $rs2):$addr),
+                    "ldstub [$addr], $rd", []>;
+def LDSTUBri : F3_2<3, 0b001101, (outs IntRegs:$rd), (ins (MEMri $rs1, $simm13):$addr),
+                    "ldstub [$addr], $rd", []>;
+def LDSTUBArr : F3_1_asi<3, 0b011101, (outs IntRegs:$rd),
+                         (ins (MEMrr $rs1, $rs2):$addr, i8imm:$asi),
+                         "ldstuba [$addr] $asi, $rd", []>;
 
 // Store multiclass - Define both Reg+Reg/Reg+Imm patterns in one shot.
 multiclass Store<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode,
            RegisterClass RC, ValueType Ty, InstrItinClass itin = IIC_st> {
   def rr  : F3_1<3, Op3Val,
-                 (outs), (ins MEMrr:$addr, RC:$rd),
+                 (outs), (ins (MEMrr $rs1, $rs2):$addr, RC:$rd),
                  !strconcat(OpcStr, " $rd, [$addr]"),
                  [(OpNode Ty:$rd, ADDRrr:$addr)],
                  itin>;
   def ri  : F3_2<3, Op3Val,
-                 (outs), (ins MEMri:$addr, RC:$rd),
+                 (outs), (ins (MEMri $rs1, $simm13):$addr, RC:$rd),
                  !strconcat(OpcStr, " $rd, [$addr]"),
                  [(OpNode Ty:$rd, ADDRri:$addr)],
                  itin>;
 }
 
 // TODO: Instructions of the StoreASI class are currently asm only; hooking up
 // CodeGen's address spaces to use these is a future task.
 class StoreASI<string OpcStr, bits<6> Op3Val, RegisterClass RC,
                InstrItinClass itin = IIC_st> :
-  F3_1_asi<3, Op3Val, (outs), (ins MEMrr:$addr, RC:$rd, i8imm:$asi),
+  F3_1_asi<3, Op3Val, (outs), (ins (MEMrr $rs1, $rs2):$addr, RC:$rd, i8imm:$asi),
            !strconcat(OpcStr, "a $rd, [$addr] $asi"),
            [],
            itin>;
 
 multiclass StoreA<string OpcStr, bits<6> Op3Val, bits<6> StoreAOp3Val,
                   SDPatternOperator OpNode, RegisterClass RC, ValueType Ty> :
              Store<OpcStr, Op3Val, OpNode, RC, Ty> {
   def Arr : StoreASI<OpcStr, StoreAOp3Val, RC>;

 
 let DecoderMethod = "DecodeLoadCP" in
   defm LDC   : Load<"ld", 0b110000, load, CoprocRegs, i32>;
 let DecoderMethod = "DecodeLoadCPPair" in
   defm LDDC   : Load<"ldd", 0b110011, load, CoprocPair, v2i32, IIC_ldd>;
 
 let DecoderMethod = "DecodeLoadCP", Defs = [CPSR] in {
   let rd = 0 in {
-    def LDCSRrr : F3_1<3, 0b110001, (outs), (ins MEMrr:$addr),
+    def LDCSRrr : F3_1<3, 0b110001, (outs), (ins (MEMrr $rs1, $rs2):$addr),
                        "ld [$addr], %csr", []>;
-    def LDCSRri : F3_2<3, 0b110001, (outs), (ins MEMri:$addr),
+    def LDCSRri : F3_2<3, 0b110001, (outs), (ins (MEMri $rs1, $simm13):$addr),
                        "ld [$addr], %csr", []>;
   }
 }
 
 let DecoderMethod = "DecodeLoadFP" in
   let Defs = [FSR] in {
     let rd = 0 in {
-      def LDFSRrr : F3_1<3, 0b100001, (outs), (ins MEMrr:$addr),
+      def LDFSRrr : F3_1<3, 0b100001, (outs), (ins (MEMrr $rs1, $rs2):$addr),
                      "ld [$addr], %fsr", [], IIC_iu_or_fpu_instr>;
-      def LDFSRri : F3_2<3, 0b100001, (outs), (ins MEMri:$addr),
+      def LDFSRri : F3_2<3, 0b100001, (outs), (ins (MEMri $rs1, $simm13):$addr),
                      "ld [$addr], %fsr", [], IIC_iu_or_fpu_instr>;
     }
     let rd = 1 in {
-      def LDXFSRrr : F3_1<3, 0b100001, (outs), (ins MEMrr:$addr),
+      def LDXFSRrr : F3_1<3, 0b100001, (outs), (ins (MEMrr $rs1, $rs2):$addr),
                      "ldx [$addr], %fsr", []>, Requires<[HasV9]>;
-      def LDXFSRri : F3_2<3, 0b100001, (outs), (ins MEMri:$addr),
+      def LDXFSRri : F3_2<3, 0b100001, (outs), (ins (MEMri $rs1, $simm13):$addr),
                      "ldx [$addr], %fsr", []>, Requires<[HasV9]>;
     }
   }
 
 let mayLoad = 1, isAsmParserOnly = 1 in {
   def GDOP_LDrr : F3_1<3, 0b000000,
-                      (outs IntRegs:$dst),
-                      (ins MEMrr:$addr, TailRelocSymGOTLoad:$sym),
-                      "ld [$addr], $dst, $sym",
-                      [(set i32:$dst,
+                      (outs IntRegs:$rd),
+                      (ins (MEMrr $rs1, $rs2):$addr, TailRelocSymGOTLoad:$sym),
+                      "ld [$addr], $rd, $sym",
+                      [(set i32:$rd,
                           (load_gdop ADDRrr:$addr, tglobaladdr:$sym))]>;
 }
 
 // Section B.4 - Store Integer Instructions, p. 95
 let DecoderMethod = "DecodeStoreInt" in {
   defm STB   : StoreA<"stb", 0b000101, 0b010101, truncstorei8,  IntRegs, i32>;
   defm STH   : StoreA<"sth", 0b000110, 0b010110, truncstorei16, IntRegs, i32>;
   defm ST    : StoreA<"st",  0b000100, 0b010100, store,         IntRegs, i32>;

 let DecoderMethod = "DecodeStoreCP" in
   defm STC   : Store<"st", 0b110100, store, CoprocRegs, i32>;
 
 let DecoderMethod = "DecodeStoreCPPair" in
   defm STDC   : Store<"std", 0b110111, store, CoprocPair, v2i32, IIC_std>;
 
 let DecoderMethod = "DecodeStoreCP", rd = 0 in {
   let Defs = [CPSR] in {
-    def STCSRrr : F3_1<3, 0b110101, (outs MEMrr:$addr), (ins),
+    def STCSRrr : F3_1<3, 0b110101, (outs (MEMrr $rs1, $rs2):$addr), (ins),
                        "st %csr, [$addr]", [], IIC_st>;
-    def STCSRri : F3_2<3, 0b110101, (outs MEMri:$addr), (ins),
+    def STCSRri : F3_2<3, 0b110101, (outs (MEMri $rs1, $simm13):$addr), (ins),
                        "st %csr, [$addr]", [], IIC_st>;
   }
   let Defs = [CPQ] in {
-    def STDCQrr : F3_1<3, 0b110110, (outs MEMrr:$addr), (ins),
+    def STDCQrr : F3_1<3, 0b110110, (outs (MEMrr $rs1, $rs2):$addr), (ins),
                        "std %cq, [$addr]", [], IIC_std>;
-    def STDCQri : F3_2<3, 0b110110, (outs MEMri:$addr), (ins),
+    def STDCQri : F3_2<3, 0b110110, (outs (MEMri $rs1, $simm13):$addr), (ins),
                        "std %cq, [$addr]", [], IIC_std>;
   }
 }
 
 let DecoderMethod = "DecodeStoreFP" in {
   let rd = 0 in {
     let Defs = [FSR] in {
-      def STFSRrr : F3_1<3, 0b100101, (outs MEMrr:$addr), (ins),
+      def STFSRrr : F3_1<3, 0b100101, (outs (MEMrr $rs1, $rs2):$addr), (ins),
                      "st %fsr, [$addr]", [], IIC_st>;
-      def STFSRri : F3_2<3, 0b100101, (outs MEMri:$addr), (ins),
+      def STFSRri : F3_2<3, 0b100101, (outs (MEMri $rs1, $simm13):$addr), (ins),
                      "st %fsr, [$addr]", [], IIC_st>;
     }
     let Defs = [FQ] in {
-      def STDFQrr : F3_1<3, 0b100110, (outs MEMrr:$addr), (ins),
+      def STDFQrr : F3_1<3, 0b100110, (outs (MEMrr $rs1, $rs2):$addr), (ins),
                      "std %fq, [$addr]", [], IIC_std>;
-      def STDFQri : F3_2<3, 0b100110, (outs MEMri:$addr), (ins),
+      def STDFQri : F3_2<3, 0b100110, (outs (MEMri $rs1, $simm13):$addr), (ins),
                      "std %fq, [$addr]", [], IIC_std>;
     }
   }
   let rd = 1, Defs = [FSR] in {
-    def STXFSRrr : F3_1<3, 0b100101, (outs MEMrr:$addr), (ins),
+    def STXFSRrr : F3_1<3, 0b100101, (outs (MEMrr $rs1, $rs2):$addr), (ins),
                    "stx %fsr, [$addr]", []>, Requires<[HasV9]>;
-    def STXFSRri : F3_2<3, 0b100101, (outs MEMri:$addr), (ins),
+    def STXFSRri : F3_2<3, 0b100101, (outs (MEMri $rs1, $simm13):$addr), (ins),
                    "stx %fsr, [$addr]", []>, Requires<[HasV9]>;
   }
 }
 
 // Section B.8 - SWAP Register with Memory Instruction
 // (Atomic swap)
-let Constraints = "$val = $dst", DecoderMethod = "DecodeSWAP" in {
+let Constraints = "$val = $rd", DecoderMethod = "DecodeSWAP" in {
   def SWAPrr : F3_1<3, 0b001111,
-                 (outs IntRegs:$dst), (ins MEMrr:$addr, IntRegs:$val),
-                 "swap [$addr], $dst",
-                 [(set i32:$dst, (atomic_swap_32 ADDRrr:$addr, i32:$val))]>;
+                 (outs IntRegs:$rd), (ins (MEMrr $rs1, $rs2):$addr, IntRegs:$val),
+                 "swap [$addr], $rd",
+                 [(set i32:$rd, (atomic_swap_32 ADDRrr:$addr, i32:$val))]>;
   def SWAPri : F3_2<3, 0b001111,
-                 (outs IntRegs:$dst), (ins MEMri:$addr, IntRegs:$val),
-                 "swap [$addr], $dst",
-                 [(set i32:$dst, (atomic_swap_32 ADDRri:$addr, i32:$val))]>;
+                 (outs IntRegs:$rd), (ins (MEMri $rs1, $simm13):$addr, IntRegs:$val),
+                 "swap [$addr], $rd",
+                 [(set i32:$rd, (atomic_swap_32 ADDRri:$addr, i32:$val))]>;
   def SWAPArr : F3_1_asi<3, 0b011111,
-                 (outs IntRegs:$dst), (ins MEMrr:$addr, i8imm:$asi, IntRegs:$val),
-                 "swapa [$addr] $asi, $dst",
+                 (outs IntRegs:$rd), (ins (MEMrr $rs1, $rs2):$addr, i8imm:$asi, IntRegs:$val),
+                 "swapa [$addr] $asi, $rd",
                  [/*FIXME: pattern?*/]>;
 }
 
 
 // Section B.9 - SETHI Instruction, p. 104
 def SETHIi: F2_1<0b100,
                  (outs IntRegs:$rd), (ins i32imm:$imm22),
                  "sethi $imm22, $rd",

 defm SRA : F3_S<"sra", 0b100111, 0, sra, i32, shift_imm5, IntRegs>;
 
 // Section B.13 - Add Instructions, p. 108
 defm ADD   : F3_12<"add", 0b000000, add, IntRegs, i32, simm13Op>;
 
 // "LEA" forms of add (patterns to make tblgen happy)
 let Predicates = [Is32Bit], isCodeGenOnly = 1 in
   def LEA_ADDri   : F3_2<2, 0b000000,
-                     (outs IntRegs:$dst), (ins MEMri:$addr),
-                     "add ${addr:arith}, $dst",
-                     [(set iPTR:$dst, ADDRri:$addr)]>;
+                     (outs IntRegs:$rd), (ins (MEMri $rs1, $simm13):$addr),
+                     "add ${addr:arith}, $rd",
+                     [(set iPTR:$rd, ADDRri:$addr)]>;
 
 let Defs = [ICC] in
   defm ADDCC  : F3_12<"addcc", 0b010000, addc, IntRegs, i32, simm13Op>;
 
 let Uses = [ICC] in
   defm ADDC   : F3_12np<"addx", 0b001000>;
 
 let Uses = [ICC], Defs = [ICC] in

 
 } // let isBranch = 1, isTerminator = 1, hasDelaySlot = 1
 
 
 // Indirect branch instructions.
 let isTerminator = 1, isBarrier = 1,  hasDelaySlot = 1, isBranch =1,
      isIndirectBranch = 1, rd = 0, isCodeGenOnly = 1 in {
   def BINDrr  : F3_1<2, 0b111000,
-                   (outs), (ins MEMrr:$ptr),
-                   "jmp $ptr",
-                   [(brind ADDRrr:$ptr)]>;
+                   (outs), (ins (MEMrr $rs1, $rs2):$addr),
+                   "jmp $addr",
+                   [(brind ADDRrr:$addr)]>;
   def BINDri  : F3_2<2, 0b111000,
-                   (outs), (ins MEMri:$ptr),
-                   "jmp $ptr",
-                   [(brind ADDRri:$ptr)]>;
+                   (outs), (ins (MEMri $rs1, $simm13):$addr),
+                   "jmp $addr",
+                   [(brind ADDRri:$addr)]>;
 }
 
 let Uses = [ICC] in {
   def BCOND : BranchSP<(ins brtarget:$imm22, CCOp:$cond),
                          "b$cond $imm22",
                         [(SPbricc bb:$imm22, imm:$cond)]>;
   def BCONDA : BranchSPA<(ins brtarget:$imm22, CCOp:$cond),
                          "b$cond,a $imm22", []>;
def CALL : InstSP<(outs), (ins calltarget:$disp, variable_ops),
     bits<30> disp;
     let op = 1;
     let Inst{29-0} = disp;
   }
 
   // indirect calls: special cases of JMPL.
   let isCodeGenOnly = 1, rd = 15 in {
     def CALLrr : F3_1<2, 0b111000,
-                      (outs), (ins MEMrr:$ptr, variable_ops),
-                      "call $ptr",
-                      [(call ADDRrr:$ptr)],
+                      (outs), (ins (MEMrr $rs1, $rs2):$addr, variable_ops),
+                      "call $addr",
+                      [(call ADDRrr:$addr)],
                       IIC_jmp_or_call>;
     def CALLri : F3_2<2, 0b111000,
-                      (outs), (ins MEMri:$ptr, variable_ops),
-                      "call $ptr",
-                      [(call ADDRri:$ptr)],
+                      (outs), (ins (MEMri $rs1, $simm13):$addr, variable_ops),
+                      "call $addr",
+                      [(call ADDRri:$addr)],
                       IIC_jmp_or_call>;
   }
 }
 
 // Section B.25 - Jump and Link Instruction
 
 // JMPL Instruction.
 let isTerminator = 1, hasDelaySlot = 1, isBarrier = 1,
     DecoderMethod = "DecodeJMPL" in {
   def JMPLrr: F3_1<2, 0b111000,
-                   (outs IntRegs:$dst), (ins MEMrr:$addr),
-                   "jmpl $addr, $dst",
+                   (outs IntRegs:$rd), (ins (MEMrr $rs1, $rs2):$addr),
+                   "jmpl $addr, $rd",
                    [],
                    IIC_jmp_or_call>;
   def JMPLri: F3_2<2, 0b111000,
-                   (outs IntRegs:$dst), (ins MEMri:$addr),
-                   "jmpl $addr, $dst",
+                   (outs IntRegs:$rd), (ins (MEMri $rs1, $simm13):$addr),
+                   "jmpl $addr, $rd",
                    [],
                    IIC_jmp_or_call>;
 }
 
 // Section A.3 - Synthetic Instructions, p. 85
 // special cases of JMPL:
 let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, isBarrier = 1,
     isCodeGenOnly = 1 in {
   let rd = 0, rs1 = 15 in
     def RETL: F3_2<2, 0b111000,
-                   (outs), (ins i32imm:$val),
-                   "jmp %o7+$val",
-                   [(retflag simm13:$val)],
+                   (outs), (ins i32imm:$simm13),
+                   "jmp %o7+$simm13",
+                   [(retflag simm13:$simm13)],
                    IIC_jmp_or_call>;
 
   let rd = 0, rs1 = 31 in
     def RET: F3_2<2, 0b111000,
-                  (outs), (ins i32imm:$val),
-                  "jmp %i7+$val",
+                  (outs), (ins i32imm:$simm13),
+                  "jmp %i7+$simm13",
                   [],
                   IIC_jmp_or_call>;
 }
 
 // Section B.26 - Return from Trap Instruction
 let isReturn = 1, isTerminator = 1, hasDelaySlot = 1,
      isBarrier = 1, rd = 0, DecoderMethod = "DecodeReturn" in {
   def RETTrr : F3_1<2, 0b111001,
-                   (outs), (ins MEMrr:$addr),
+                   (outs), (ins (MEMrr $rs1, $rs2):$addr),
                    "rett $addr",
                    [],
                    IIC_jmp_or_call>;
   def RETTri : F3_2<2, 0b111001,
-                    (outs), (ins MEMri:$addr),
+                    (outs), (ins (MEMri $rs1, $simm13):$addr),
                     "rett $addr",
                     [],
                     IIC_jmp_or_call>;
 }
 
 
 // Section B.27 - Trap on Integer Condition Codes Instruction
 // conditional branch class:

 
 // Section B.31 - Unimplemented Instruction
 let rd = 0 in
   def UNIMP : F2_1<0b000, (outs), (ins i32imm:$imm22),
                   "unimp $imm22", []>;
 
 // Section B.32 - Flush Instruction Memory
 let rd = 0 in {
-  def FLUSHrr : F3_1<2, 0b111011, (outs), (ins MEMrr:$addr),
+  def FLUSHrr : F3_1<2, 0b111011, (outs), (ins (MEMrr $rs1, $rs2):$addr),
                        "flush $addr", []>;
-  def FLUSHri : F3_2<2, 0b111011, (outs), (ins MEMri:$addr),
+  def FLUSHri : F3_2<2, 0b111011, (outs), (ins (MEMri $rs1, $simm13):$addr),
                        "flush $addr", []>;
 
   // The no-arg FLUSH is only here for the benefit of the InstAlias
   // "flush", which cannot seem to use FLUSHrr, due to the inability
   // to construct a MEMrr with fixed G0 registers.
   let rs1 = 0, rs2 = 0 in
     def FLUSH   : F3_1<2, 0b111011, (outs), (ins), "flush %g0", []>;
 }
def TLS_ADDrr : F3_1<2, 0b000000,
                     (outs IntRegs:$rd),
                     (ins IntRegs:$rs1, IntRegs:$rs2, TailRelocSymTLSAdd:$sym),
                     "add $rs1, $rs2, $rd, $sym",
                     [(set i32:$rd,
                         (tlsadd i32:$rs1, i32:$rs2, tglobaltlsaddr:$sym))]>;
 
 let mayLoad = 1 in {
   def TLS_LDrr : F3_1<3, 0b000000,
-                      (outs IntRegs:$dst),
-                      (ins MEMrr:$addr, TailRelocSymTLSLoad:$sym),
-                      "ld [$addr], $dst, $sym",
-                      [(set i32:$dst,
+                      (outs IntRegs:$rd),
+                      (ins (MEMrr $rs1, $rs2):$addr, TailRelocSymTLSLoad:$sym),
+                      "ld [$addr], $rd, $sym",
+                      [(set i32:$rd,
                           (tlsld ADDRrr:$addr, tglobaltlsaddr:$sym))]>;
 }
 
 let Uses = [O6], isCall = 1, hasDelaySlot = 1 in
   def TLS_CALL : InstSP<(outs),
                         (ins calltarget:$disp, TailRelocSymTLSCall:$sym,
                          variable_ops),
                         "call $disp, $sym",

 }
 
 def : Pat<(tailcall (iPTR texternalsym:$dst)),
           (TAIL_CALL texternalsym:$dst)>;
 
 let isCodeGenOnly = 1, isReturn = 1,  hasDelaySlot = 1,  isTerminator = 1,
     isBarrier = 1, rd = 0 in {
   def TAIL_CALLri : F3_2<2, 0b111000,
-                         (outs), (ins MEMri:$ptr, variable_ops),
-                         "jmp $ptr",
-                         [(tailcall ADDRri:$ptr)]>;
+                         (outs), (ins (MEMri $rs1, $simm13):$addr, variable_ops),
+                         "jmp $addr",
+                         [(tailcall ADDRri:$addr)]>;
 }
 
 //===----------------------------------------------------------------------===//
 // V9 Instructions
 //===----------------------------------------------------------------------===//
 
 // V9 Conditional Moves.
 let Predicates = [HasV9], Constraints = "$f = $rd" in {
let hasSideEffects = 1 in {
   defm TADDCCTV : F3_12np<"taddcctv", 0b100010>;
   defm TSUBCCTV : F3_12np<"tsubcctv", 0b100011>;
 }
 }
 
 // Section A.42 - Prefetch Data
 let Predicates = [HasV9] in {
   def PREFETCHr : F3_1<3, 0b101101,
-                   (outs), (ins MEMrr:$addr, shift_imm5:$rd),
+                   (outs), (ins (MEMrr $rs1, $rs2):$addr, shift_imm5:$rd),
                    "prefetch [$addr], $rd", []>;
   def PREFETCHi : F3_2<3, 0b101101,
-                   (outs), (ins MEMri:$addr, shift_imm5:$rd),
+                   (outs), (ins (MEMri $rs1, $simm13):$addr, shift_imm5:$rd),
                    "prefetch [$addr], $rd", []>;
 }
 
 
 
 // Section A.43 - Read Privileged Register Instructions
 let Predicates = [HasV9] in {
 let rs2 = 0 in