[M68k] Fix the crash of fast register allocator

[0x59616e]

Summary

MOVEM is used to spill the register, which will cause problem with 1 byte data, since it only supports word (2 bytes) and long (4 bytes) size.

We change to use the normal move instruction to spill 1 byte data.

Fixes #57660

[RKSimon]

llvm/test/CodeGen/M68k/fast-regalloc.ll

5

Please can you reference PR57660 in a comment or test name to speed up any triage when people look at this test file in the future.

[0x59616e]

Add comment to refer to the issue.

[RKSimon]

llvm/lib/Target/M68k/M68kRegisterInfo.td

95

does i16 need fixing as well?

[myhsu]

Thank you for fixing this bug!
As I mentioned in #57660, I feel like we should fix the assertion instead

[0x59616e]

Fix the assertion in M68kInstrInfo::storeRegToStackSlot and M68kInstrInfo::loadRegFromStackSlot

[myhsu]

llvm/lib/Target/M68k/M68kInstrInfo.cpp

705 ↗

(On Diff #459395)

Oh I didn't notice this, thanks for spotting

748 ↗

(On Diff #459395)

Instead of remove these assertions completely, can we check if the object size matches the spill size of the given register class (like what X86 is doing). Ditto for loadRegFromStackSlot.

[0x59616e]

Add assertion to check the size of the stack slot matches the size of register class

[myhsu]

LGTM, thanks

[0x59616e]

Thanks ;)

llvm/lib/Target/M68k/M68kRegisterInfo.td

 
 def PC  : MxPseudoReg<"pc">;
 
 //===----------------------------------------------------------------------===//
 // Register Classes
 //===----------------------------------------------------------------------===//
 
 class MxRegClass<list<ValueType> regTypes, int alignment, dag regList>
-    : RegisterClass<"M68k", regTypes, alignment, regList>;
+    : RegisterClass<"M68k", regTypes, alignment, regList> {
+  let RegInfos = RegInfoByHwMode<[DefaultMode], [RegInfo<alignment, 32, alignment>]>;
+}
 
 // Data Registers
-def DR8  : MxRegClass<[i8],  16, (sequence "BD%u", 0, 7)>;
+def DR8  : MxRegClass<[i8],  16, (sequence "BD%u", 0, 7)> {
+  let RegInfos = RegInfoByHwMode<[DefaultMode], [RegInfo<8, 32, 16>]>;
+}
+
 def DR16 : MxRegClass<[i16], 16, (sequence "WD%u", 0, 7)>;
 def DR32 : MxRegClass<[i32], 32, (sequence "D%u",  0, 7)>;
 
 // Address Registers
 def AR16 : MxRegClass<[i16], 16, (add (sequence "WA%u", 0, 6), WSP)>;
 def AR32 : MxRegClass<[i32], 32, (add (sequence "A%u", 0, 6), SP)>;
 
 def AR32_NOSP : MxRegClass<[i32], 32, (sequence "A%u", 0, 6)>;
 

llvm/test/CodeGen/M68k/fast-regalloc.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=m68k-linux-gnu --regalloc=fast -o - %s | FileCheck %s
+
+; This is the regression test of PR57660
+; (https://github.com/llvm/llvm-project/issues/57660)
+
+define dso_local void @foo1() {
+; CHECK-LABEL: foo1:
+; CHECK:         .cfi_startproc
+; CHECK-NEXT:  ; %bb.0: ; %entry
+; CHECK-NEXT:    suba.l #4, %sp
+; CHECK-NEXT:    .cfi_def_cfa_offset -8
+; CHECK-NEXT:    move.b #0, %d0
+; CHECK-NEXT:    movem.l %d0, (0,%sp)
+; CHECK-NEXT:  .LBB0_1: ; %do.body
+; CHECK-NEXT:    ; =>This Inner Loop Header: Depth=1
+; CHECK-NEXT:    movem.l (0,%sp), %d0
+; CHECK-NEXT:    cmpi.b #0, %d0
+; CHECK-NEXT:    bne .LBB0_1
+; CHECK-NEXT:  ; %bb.2: ; %do.end
+; CHECK-NEXT:    adda.l #4, %sp
+; CHECK-NEXT:    rts
+entry:
+  br label %do.body
+
+do.body:                                          ; preds = %land.end, %entry
+  %cmp5 = icmp eq i32 0, 4
+  br label %land.end
+
+land.end:                                         ; preds = %do.body
+  br i1 %cmp5, label %do.body, label %do.end
+
+do.end:                                           ; preds = %land.end
+  ret void
+}
+
+define dso_local i32 @foo2(ptr noundef %0) {
+; CHECK-LABEL: foo2:
+; CHECK:         .cfi_startproc
+; CHECK-NEXT:  ; %bb.0: ; %entry
+; CHECK-NEXT:    suba.l #8, %sp
+; CHECK-NEXT:    .cfi_def_cfa_offset -12
+; CHECK-NEXT:    move.l (12,%sp), %a0
+; CHECK-NEXT:    move.b (%a0), %d0
+; CHECK-NEXT:    movem.l %d0, (0,%sp)
+; CHECK-NEXT:    and.b #1, %d0
+; CHECK-NEXT:    movem.l %d0, (4,%sp)
+; CHECK-NEXT:    sub.b #1, %d0
+; CHECK-NEXT:    bgt .LBB1_2
+; CHECK-NEXT:  ; %bb.1: ; %if
+; CHECK-NEXT:    movem.l (4,%sp), %d0
+; CHECK-NEXT:    movem.l (0,%sp), %d1
+; CHECK-NEXT:    add.b %d1, %d0
+; CHECK-NEXT:    bra .LBB1_3
+; CHECK-NEXT:  .LBB1_2: ; %else
+; CHECK-NEXT:    movem.l (0,%sp), %d0-%d1
+; CHECK-NEXT:    sub.b %d1, %d0
+; CHECK-NEXT:    movem.l %d0, (0,%sp)
+; CHECK-NEXT:  .LBB1_3: ; %cont
+; CHECK-NEXT:    movem.l %d0, (4,%sp)
+; CHECK-NEXT:    movem.l (4,%sp), %d0
+; CHECK-NEXT:    ext.w %d0
+; CHECK-NEXT:    ext.l %d0
+; CHECK-NEXT:    adda.l #8, %sp
+; CHECK-NEXT:    rts
+entry:
+  %1 = getelementptr i8, ptr %0, i32 0
+  %2 = load i8, ptr %1
+  %3 = and i8 %2, 1
+  %4 = icmp sle i8 %3, 1
+  br i1 %4, label %if, label %else
+
+if:
+  %5 = add i8 %3, %2
+  br label %cont
+
+else:
+  %6 = sub i8 %2, %3
+  br label %cont
+
+cont:
+  %7 = phi i8 [%5, %if], [%6, %else]
+  %8 = sext i8 %7 to i32
+  ret i32 %8
+}