[M68k] Fix the crash of fast register allocator

[0x59616e]

Summary

MOVEM is used to spill the register, which will cause problem with 1 byte data, since it only supports word (2 bytes) and long (4 bytes) size.

We change to use the normal move instruction to spill 1 byte data.

Fixes #57660

[RKSimon]

llvm/test/CodeGen/M68k/fast-regalloc.ll

4 ↗

(On Diff #459266)

Please can you reference PR57660 in a comment or test name to speed up any triage when people look at this test file in the future.

[0x59616e]

Add comment to refer to the issue.

[RKSimon]

llvm/lib/Target/M68k/M68kRegisterInfo.td

95 ↗

(On Diff #459278)

does i16 need fixing as well?

[myhsu]

Thank you for fixing this bug!
As I mentioned in #57660, I feel like we should fix the assertion instead

[0x59616e]

Fix the assertion in M68kInstrInfo::storeRegToStackSlot and M68kInstrInfo::loadRegFromStackSlot

[myhsu]

llvm/lib/Target/M68k/M68kInstrInfo.cpp

705

Oh I didn't notice this, thanks for spotting

748

Instead of remove these assertions completely, can we check if the object size matches the spill size of the given register class (like what X86 is doing). Ditto for loadRegFromStackSlot.

[0x59616e]

Add assertion to check the size of the stack slot matches the size of register class

[myhsu]

LGTM, thanks

[0x59616e]

Thanks ;)

llvm/lib/Target/M68k/M68kInstrInfo.cpp

 unsigned getLoadStoreRegOpcode(unsigned Reg, const TargetRegisterClass *RC,
                                const TargetRegisterInfo *TRI,
                                const M68kSubtarget &STI, bool load) {
   switch (TRI->getRegSizeInBits(*RC)) {
   default:
     llvm_unreachable("Unknown spill size");
   case 8:
     if (M68k::DR8RegClass.hasSubClassEq(RC))
-      return load ? M68k::MOVM8mp_P : M68k::MOVM8pm_P;
+      return load ? M68k::MOV8dp : M68k::MOV8pd;
     if (M68k::CCRCRegClass.hasSubClassEq(RC))
       return load ? M68k::MOV16cp : M68k::MOV16pc;
 
     llvm_unreachable("Unknown 1-byte regclass");
   case 16:
     assert(M68k::XR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass");
     return load ? M68k::MOVM16mp_P : M68k::MOVM16pm_P;
   case 32:

 }
 
 void M68kInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
                                         MachineBasicBlock::iterator MI,
                                         Register SrcReg, bool IsKill,
                                         int FrameIndex,
                                         const TargetRegisterClass *RC,
                                         const TargetRegisterInfo *TRI) const {
-  const MachineFunction &MF = *MBB.getParent();
-  assert(MF.getFrameInfo().getObjectSize(FrameIndex) == 4 &&
-         "Stack slot too small for store");
+  const MachineFrameInfo &MFI = MBB.getParent()->getFrameInfo();
+  assert(MFI.getObjectSize(FrameIndex) >= TRI->getSpillSize(*RC) &&
+         "Stack slot is too small to store");
+
   unsigned Opc = getStoreRegOpcode(SrcReg, RC, TRI, Subtarget);
   DebugLoc DL = MBB.findDebugLoc(MI);
   // (0,FrameIndex) <- $reg
   M68k::addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIndex)
       .addReg(SrcReg, getKillRegState(IsKill));
 }
 
 void M68kInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
                                          MachineBasicBlock::iterator MI,
                                          Register DstReg, int FrameIndex,
                                          const TargetRegisterClass *RC,
                                          const TargetRegisterInfo *TRI) const {
-  const MachineFunction &MF = *MBB.getParent();
-  assert(MF.getFrameInfo().getObjectSize(FrameIndex) == 4 &&
-         "Stack slot too small for load");
+  const MachineFrameInfo &MFI = MBB.getParent()->getFrameInfo();
+  assert(MFI.getObjectSize(FrameIndex) >= TRI->getSpillSize(*RC) &&
+         "Stack slot is too small to load");
+
   unsigned Opc = getLoadRegOpcode(DstReg, RC, TRI, Subtarget);
   DebugLoc DL = MBB.findDebugLoc(MI);
   M68k::addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DstReg), FrameIndex);
 }
 
 /// Return a virtual register initialized with the the global base register
 /// value. Output instructions required to initialize the register in the
 /// function entry block, if necessary.

llvm/test/CodeGen/M68k/PR57660.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=m68k-linux-gnu --regalloc=fast %s -o - | FileCheck %s
+
+define dso_local void @foo1() {
+; CHECK-LABEL: foo1:
+; CHECK:         .cfi_startproc
+; CHECK-NEXT:  ; %bb.0: ; %entry
+; CHECK-NEXT:    suba.l #2, %sp
+; CHECK-NEXT:    .cfi_def_cfa_offset -6
+; CHECK-NEXT:    move.b #0, %d0
+; CHECK-NEXT:    move.b %d0, (0,%sp) ; 1-byte Folded Spill
+; CHECK-NEXT:  .LBB0_1: ; %do.body
+; CHECK-NEXT:    ; =>This Inner Loop Header: Depth=1
+; CHECK-NEXT:    move.b (0,%sp), %d0 ; 1-byte Folded Reload
+; CHECK-NEXT:    cmpi.b #0, %d0
+; CHECK-NEXT:    bne .LBB0_1
+; CHECK-NEXT:  ; %bb.2: ; %do.end
+; CHECK-NEXT:    adda.l #2, %sp
+; CHECK-NEXT:    rts
+entry:
+  br label %do.body
+
+do.body:                                          ; preds = %land.end, %entry
+  %cmp5 = icmp eq i32 0, 4
+  br label %land.end
+
+land.end:                                         ; preds = %do.body
+  br i1 %cmp5, label %do.body, label %do.end
+
+do.end:                                           ; preds = %land.end
+  ret void
+}
+
+define i32 @foo2(ptr noundef %0) {
+; CHECK-LABEL: foo2:
+; CHECK:         .cfi_startproc
+; CHECK-NEXT:  ; %bb.0: ; %entry
+; CHECK-NEXT:    suba.l #4, %sp
+; CHECK-NEXT:    .cfi_def_cfa_offset -8
+; CHECK-NEXT:    move.l (8,%sp), %a0
+; CHECK-NEXT:    move.b (%a0), %d0
+; CHECK-NEXT:    move.b %d0, (0,%sp) ; 1-byte Folded Spill
+; CHECK-NEXT:    and.b #1, %d0
+; CHECK-NEXT:    move.b %d0, (2,%sp) ; 1-byte Folded Spill
+; CHECK-NEXT:    sub.b #1, %d0
+; CHECK-NEXT:    bgt .LBB1_2
+; CHECK-NEXT:  ; %bb.1: ; %if
+; CHECK-NEXT:    move.b (2,%sp), %d0 ; 1-byte Folded Reload
+; CHECK-NEXT:    move.b (0,%sp), %d1 ; 1-byte Folded Reload
+; CHECK-NEXT:    add.b %d1, %d0
+; CHECK-NEXT:    bra .LBB1_3
+; CHECK-NEXT:  .LBB1_2: ; %else
+; CHECK-NEXT:    move.b (2,%sp), %d1 ; 1-byte Folded Reload
+; CHECK-NEXT:    move.b (0,%sp), %d0 ; 1-byte Folded Reload
+; CHECK-NEXT:    sub.b %d1, %d0
+; CHECK-NEXT:    move.b %d0, (0,%sp) ; 1-byte Folded Spill
+; CHECK-NEXT:  .LBB1_3: ; %cont
+; CHECK-NEXT:    move.b %d0, (2,%sp) ; 1-byte Folded Spill
+; CHECK-NEXT:    move.b (2,%sp), %d0 ; 1-byte Folded Reload
+; CHECK-NEXT:    ext.w %d0
+; CHECK-NEXT:    ext.l %d0
+; CHECK-NEXT:    adda.l #4, %sp
+; CHECK-NEXT:    rts
+entry:
+  %1 = getelementptr i8, ptr %0, i32 0
+  %2 = load i8, ptr %1
+  %3 = and i8 %2, 1
+  %4 = icmp sle i8 %3, 1
+  br i1 %4, label %if, label %else
+
+if:
+  %5 = add i8 %3, %2
+  br label %cont
+
+else:
+  %6 = sub i8 %2, %3
+  br label %cont
+
+cont:
+  %7 = phi i8 [%5, %if], [%6, %else]
+  %8 = sext i8 %7 to i32
+  ret i32 %8
+}