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Differential D133543

[PowerPC][NFC] Add base test case to show redundant spill of vector registers
ClosedPublic

Authored by tingwang on Sep 8 2022, 5:25 PM.

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Reviewers
lkail
Group Reviewers
Restricted Project
Commits
rG12e78d96f2fb: [PowerPC][NFC] Add base test case to show redundant spill of vector registers
Summary

Add base test case for https://reviews.llvm.org/D133466.

Diff Detail

Unit TestsFailed

TimeTest
60,050 msx64 debian > libFuzzer.libFuzzer::fuzzer-leak.test

Event Timeline

tingwang created this revision.Sep 8 2022, 5:25 PM
Herald added a project: Restricted Project. · View Herald TranscriptSep 8 2022, 5:25 PM
Herald added subscribers: shchenz, nemanjai, qcolombet. · View Herald Transcript
tingwang requested review of this revision.Sep 8 2022, 5:25 PM
Herald added a subscriber: llvm-commits. · View Herald TranscriptSep 8 2022, 5:25 PM
tingwang updated this revision to Diff 458929.Sep 8 2022, 5:35 PM

Remove redundant NOT check.

Harbormaster completed remote builds in B185751: Diff 458929.Sep 8 2022, 6:56 PM
tingwang added a child revision: D133466: [PowerPC] Remove redundant spill/reload of callee saved vector registers.Sep 8 2022, 7:08 PM
tingwang updated this revision to Diff 459603.Sep 12 2022, 5:39 PM

Drop @llvm.experimental.patchpoint.void test case as not supported on AIX.

lkail added inline comments.Sep 12 2022, 6:28 PM
llvm/test/CodeGen/PowerPC/aix32-vector-pair-cc-spills.ll
7

You can use CHECK-LABEL here.

22

ditto.

42

ditto.

57

ditto.

llvm/test/CodeGen/PowerPC/aix64-vector-pair-cc-spills.ll
8

ditto.

34

ditto.

55

ditto.

81

ditto.

Harbormaster completed remote builds in B186264: Diff 459603.Sep 12 2022, 6:41 PM
tingwang updated this revision to Diff 459631.Sep 12 2022, 7:36 PM

Address comments:
Use CHECK-LABEL to match function name.

lkail accepted this revision as: lkail.Sep 12 2022, 8:35 PM

LGTM, thanks for your patience.

This revision is now accepted and ready to land.Sep 12 2022, 8:35 PM
Harbormaster completed remote builds in B186288: Diff 459631.Sep 12 2022, 8:47 PM
tingwang added a comment.Sep 12 2022, 8:58 PM
In D133543#3785484, @lkail wrote:

LGTM, thanks for your patience.

Thank you for your guidance!

Closed by commit rG12e78d96f2fb: [PowerPC][NFC] Add base test case to show redundant spill of vector registers (authored by tingwang). · Explain WhySep 12 2022, 9:48 PM
This revision was automatically updated to reflect the committed changes.
tingwang added a commit: rG12e78d96f2fb: [PowerPC][NFC] Add base test case to show redundant spill of vector registers.

Revision Contents

PathSize
llvm/
test/
CodeGen/
PowerPC/
88 lines
172 lines

Diff 458929

llvm/test/CodeGen/PowerPC/aix32-vector-pair-cc-spills.ll

  • This file was added.
; RUN: llc -O0 -mtriple=powerpc-ibm-aix-xcoff -mcpu=pwr10 -stop-after=prologepilog -verify-machineinstrs < %s | \
; RUN: FileCheck --check-prefix=CHECK %s
; RUN: llc -O0 -mtriple=powerpc-ibm-aix-xcoff -mcpu=pwr10 -vec-extabi -stop-after=prologepilog -verify-machineinstrs < %s | \
; RUN: FileCheck --check-prefix=CHECK-VEXT %s
; CHECK: name: foo
; CHECK-NOT: spill-slot
lkailUnsubmitted
Not Done
ReplyInline Actions

You can use CHECK-LABEL here.

lkail: You can use `CHECK-LABEL` here.
; CHECK-NOT: callee-saved-register: '$v31'
; CHECK-NOT: callee-saved-register: '$v30'
; CHECK-NOT: callee-saved-register: '$v29'
; CHECK-NOT: callee-saved-register: '$v28'
; CHECK-NOT: callee-saved-register: '$v27'
; CHECK-NOT: callee-saved-register: '$v26'
; CHECK-NOT: callee-saved-register: '$v25'
; CHECK-NOT: callee-saved-register: '$v24'
; CHECK-NOT: callee-saved-register: '$v23'
; CHECK-NOT: callee-saved-register: '$v22'
; CHECK-NOT: callee-saved-register: '$v21'
; CHECK-NOT: callee-saved-register: '$v20'
; CHECK-VEXT: name: foo
; CHECK-VEXT-NOT: spill-slot
lkailUnsubmitted
Not Done
ReplyInline Actions

ditto.

lkail: ditto.
; CHECK-VEXT-NOT: callee-saved-register: '$v31'
; CHECK-VEXT-NOT: callee-saved-register: '$v30'
; CHECK-VEXT-NOT: callee-saved-register: '$v29'
; CHECK-VEXT-NOT: callee-saved-register: '$v28'
; CHECK-VEXT-NOT: callee-saved-register: '$v27'
; CHECK-VEXT-NOT: callee-saved-register: '$v26'
; CHECK-VEXT-NOT: callee-saved-register: '$v25'
; CHECK-VEXT-NOT: callee-saved-register: '$v24'
; CHECK-VEXT-NOT: callee-saved-register: '$v23'
; CHECK-VEXT-NOT: callee-saved-register: '$v22'
; CHECK-VEXT-NOT: callee-saved-register: '$v21'
; CHECK-VEXT-NOT: callee-saved-register: '$v20'
define void @foo() {
entry:
call void @bar(i32 0)
ret void
}
; CHECK: name: spill
; CHECK-NOT: spill-slot
lkailUnsubmitted
Not Done
ReplyInline Actions

ditto.

lkail: ditto.
; CHECK-NOT: callee-saved-register: '$v31'
; CHECK-NOT: callee-saved-register: '$v30'
; CHECK-NOT: callee-saved-register: '$v29'
; CHECK-NOT: callee-saved-register: '$v28'
; CHECK-NOT: callee-saved-register: '$v27'
; CHECK-NOT: callee-saved-register: '$v26'
; CHECK-NOT: callee-saved-register: '$v25'
; CHECK-NOT: callee-saved-register: '$v24'
; CHECK-NOT: callee-saved-register: '$v23'
; CHECK-NOT: callee-saved-register: '$v22'
; CHECK-NOT: callee-saved-register: '$v21'
; CHECK-NOT: callee-saved-register: '$v20'
; CHECK-VEXT: name: spill
; CHECK-VEXT: spill-slot
lkailUnsubmitted
Not Done
ReplyInline Actions

ditto.

lkail: ditto.
; CHECK-VEXT-NEXT: callee-saved-register: '$v31'
; CHECK-VEXT: spill-slot
; CHECK-VEXT-NEXT: callee-saved-register: '$v30'
; CHECK-VEXT: spill-slot
; CHECK-VEXT-NEXT: callee-saved-register: '$v29'
; CHECK-VEXT: spill-slot
; CHECK-VEXT-NEXT: callee-saved-register: '$v28'
; CHECK-VEXT: spill-slot
; CHECK-VEXT-NEXT: callee-saved-register: '$v27'
; CHECK-VEXT: spill-slot
; CHECK-VEXT-NEXT: callee-saved-register: '$v26'
; CHECK-VEXT: spill-slot
; CHECK-VEXT-NEXT: callee-saved-register: '$v25'
; CHECK-VEXT: spill-slot
; CHECK-VEXT-NEXT: callee-saved-register: '$v24'
; CHECK-VEXT: spill-slot
; CHECK-VEXT-NEXT: callee-saved-register: '$v23'
; CHECK-VEXT: spill-slot
; CHECK-VEXT-NEXT: callee-saved-register: '$v22'
; CHECK-VEXT: spill-slot
; CHECK-VEXT-NEXT: callee-saved-register: '$v21'
; CHECK-VEXT: spill-slot
; CHECK-VEXT-NEXT: callee-saved-register: '$v20'
define void @spill() {
entry:
call void asm sideeffect "nop", "~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()
call void @bar(i32 0)
ret void
}
declare void @bar(i32)

llvm/test/CodeGen/PowerPC/aix64-vector-pair-cc-spills.ll

  • This file was added.
; RUN: llc -O0 -mtriple=powerpc64-ibm-aix-xcoff -mcpu=pwr10 -stop-after=prologepilog -verify-machineinstrs < %s | \
; RUN: FileCheck --check-prefix=CHECK %s
; RUN: llc -O0 -mtriple=powerpc64-ibm-aix-xcoff -mcpu=pwr10 -vec-extabi -stop-after=prologepilog -verify-machineinstrs < %s | \
; RUN: FileCheck --check-prefix=CHECK-VEXT %s
; Error pattern will be fixed in https://reviews.llvm.org/D133466
; CHECK: name: foo
; CHECK: spill-slot
lkailUnsubmitted
Not Done
ReplyInline Actions

ditto.

lkail: ditto.
; CHECK-NEXT: callee-saved-register: '$v31'
; CHECK: spill-slot
; CHECK-NEXT: callee-saved-register: '$v30'
; CHECK: spill-slot
; CHECK-NEXT: callee-saved-register: '$v29'
; CHECK: spill-slot
; CHECK-NEXT: callee-saved-register: '$v28'
; CHECK: spill-slot
; CHECK-NEXT: callee-saved-register: '$v27'
; CHECK: spill-slot
; CHECK-NEXT: callee-saved-register: '$v26'
; CHECK: spill-slot
; CHECK-NEXT: callee-saved-register: '$v25'
; CHECK: spill-slot
; CHECK-NEXT: callee-saved-register: '$v24'
; CHECK: spill-slot
; CHECK-NEXT: callee-saved-register: '$v23'
; CHECK: spill-slot
; CHECK-NEXT: callee-saved-register: '$v22'
; CHECK: spill-slot
; CHECK-NEXT: callee-saved-register: '$v21'
; CHECK: spill-slot
; CHECK-NEXT: callee-saved-register: '$v20'
; CHECK-VEXT: name: foo
; CHECK-VEXT-NOT: spill-slot
lkailUnsubmitted
Not Done
ReplyInline Actions

ditto.

lkail: ditto.
; CHECK-VEXT-NOT: callee-saved-register: '$v31'
; CHECK-VEXT-NOT: callee-saved-register: '$v30'
; CHECK-VEXT-NOT: callee-saved-register: '$v29'
; CHECK-VEXT-NOT: callee-saved-register: '$v28'
; CHECK-VEXT-NOT: callee-saved-register: '$v27'
; CHECK-VEXT-NOT: callee-saved-register: '$v26'
; CHECK-VEXT-NOT: callee-saved-register: '$v25'
; CHECK-VEXT-NOT: callee-saved-register: '$v24'
; CHECK-VEXT-NOT: callee-saved-register: '$v23'
; CHECK-VEXT-NOT: callee-saved-register: '$v22'
; CHECK-VEXT-NOT: callee-saved-register: '$v21'
; CHECK-VEXT-NOT: callee-saved-register: '$v20'
define void @foo() {
entry:
call void @bar(i32 0)
ret void
}
; Error pattern will be fixed in https://reviews.llvm.org/D133466
; CHECK: name: spill
; CHECK: spill-slot
lkailUnsubmitted
Not Done
ReplyInline Actions

ditto.

lkail: ditto.
; CHECK-NEXT: callee-saved-register: '$v31'
; CHECK: spill-slot
; CHECK-NEXT: callee-saved-register: '$v30'
; CHECK: spill-slot
; CHECK-NEXT: callee-saved-register: '$v29'
; CHECK: spill-slot
; CHECK-NEXT: callee-saved-register: '$v28'
; CHECK: spill-slot
; CHECK-NEXT: callee-saved-register: '$v27'
; CHECK: spill-slot
; CHECK-NEXT: callee-saved-register: '$v26'
; CHECK: spill-slot
; CHECK-NEXT: callee-saved-register: '$v25'
; CHECK: spill-slot
; CHECK-NEXT: callee-saved-register: '$v24'
; CHECK: spill-slot
; CHECK-NEXT: callee-saved-register: '$v23'
; CHECK: spill-slot
; CHECK-NEXT: callee-saved-register: '$v22'
; CHECK: spill-slot
; CHECK-NEXT: callee-saved-register: '$v21'
; CHECK: spill-slot
; CHECK-NEXT: callee-saved-register: '$v20'
; CHECK-VEXT: name: spill
; CHECK-VEXT: spill-slot
lkailUnsubmitted
Not Done
ReplyInline Actions

ditto.

lkail: ditto.
; CHECK-VEXT-NEXT: callee-saved-register: '$v31'
; CHECK-VEXT: spill-slot
; CHECK-VEXT-NEXT: callee-saved-register: '$v30'
; CHECK-VEXT: spill-slot
; CHECK-VEXT-NEXT: callee-saved-register: '$v29'
; CHECK-VEXT: spill-slot
; CHECK-VEXT-NEXT: callee-saved-register: '$v28'
; CHECK-VEXT: spill-slot
; CHECK-VEXT-NEXT: callee-saved-register: '$v27'
; CHECK-VEXT: spill-slot
; CHECK-VEXT-NEXT: callee-saved-register: '$v26'
; CHECK-VEXT: spill-slot
; CHECK-VEXT-NEXT: callee-saved-register: '$v25'
; CHECK-VEXT: spill-slot
; CHECK-VEXT-NEXT: callee-saved-register: '$v24'
; CHECK-VEXT: spill-slot
; CHECK-VEXT-NEXT: callee-saved-register: '$v23'
; CHECK-VEXT: spill-slot
; CHECK-VEXT-NEXT: callee-saved-register: '$v22'
; CHECK-VEXT: spill-slot
; CHECK-VEXT-NEXT: callee-saved-register: '$v21'
; CHECK-VEXT: spill-slot
; CHECK-VEXT-NEXT: callee-saved-register: '$v20'
define void @spill() {
entry:
call void asm sideeffect "nop", "~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()
call void @bar(i32 0)
ret void
}
; Error pattern will be fixed in https://reviews.llvm.org/D133466
; CHECK: name: spill2
; CHECK: spill-slot
; CHECK-NEXT: callee-saved-register: '$v31'
; CHECK: spill-slot
; CHECK-NEXT: callee-saved-register: '$v30'
; CHECK: spill-slot
; CHECK-NEXT: callee-saved-register: '$v29'
; CHECK: spill-slot
; CHECK-NEXT: callee-saved-register: '$v28'
; CHECK: spill-slot
; CHECK-NEXT: callee-saved-register: '$v27'
; CHECK: spill-slot
; CHECK-NEXT: callee-saved-register: '$v26'
; CHECK: spill-slot
; CHECK-NEXT: callee-saved-register: '$v25'
; CHECK: spill-slot
; CHECK-NEXT: callee-saved-register: '$v24'
; CHECK: spill-slot
; CHECK-NEXT: callee-saved-register: '$v23'
; CHECK: spill-slot
; CHECK-NEXT: callee-saved-register: '$v22'
; CHECK: spill-slot
; CHECK-NEXT: callee-saved-register: '$v21'
; CHECK: spill-slot
; CHECK-NEXT: callee-saved-register: '$v20'
; CHECK-VEXT: name: spill2
; CHECK-VEXT: spill-slot
; CHECK-VEXT-NEXT: callee-saved-register: '$v31'
; CHECK-VEXT: spill-slot
; CHECK-VEXT-NEXT: callee-saved-register: '$v30'
; CHECK-VEXT: spill-slot
; CHECK-VEXT-NEXT: callee-saved-register: '$v29'
; CHECK-VEXT: spill-slot
; CHECK-VEXT-NEXT: callee-saved-register: '$v28'
; CHECK-VEXT: spill-slot
; CHECK-VEXT-NEXT: callee-saved-register: '$v27'
; CHECK-VEXT: spill-slot
; CHECK-VEXT-NEXT: callee-saved-register: '$v26'
; CHECK-VEXT: spill-slot
; CHECK-VEXT-NEXT: callee-saved-register: '$v25'
; CHECK-VEXT: spill-slot
; CHECK-VEXT-NEXT: callee-saved-register: '$v24'
; CHECK-VEXT: spill-slot
; CHECK-VEXT-NEXT: callee-saved-register: '$v23'
; CHECK-VEXT: spill-slot
; CHECK-VEXT-NEXT: callee-saved-register: '$v22'
; CHECK-VEXT: spill-slot
; CHECK-VEXT-NEXT: callee-saved-register: '$v21'
; CHECK-VEXT: spill-slot
; CHECK-VEXT-NEXT: callee-saved-register: '$v20'
define void @spill2(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
entry:
call void asm sideeffect "nop", "~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()
call anyregcc void (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.void(i64 13, i32 40, ptr inttoptr (i64 0 to ptr), i32 2, i64 %p1, i64 %p2, i64 %p3, i64 %p4)
ret void
}
declare void @bar(i32)
declare void @llvm.experimental.patchpoint.void(i64, i32, ptr, i32, ...)