AMDGPU: Factor out hasDivergentBranch(). NFC

[ruiling]

Summary

This is helpful for detecting whether a block ends with divergent branch
in passes before lowering the pseudo control flow instructions.

[foad]

LGTM.

llvm/lib/Target/AMDGPU/SIInstrInfo.h

public:
   bool findCommutedOpIndices(MCInstrDesc Desc, unsigned & SrcOpIdx0,
    unsigned & SrcOpIdx1) const;
 
   bool isBranchOffsetInRange(unsigned BranchOpc,
                              int64_t BrOffset) const override;
 
   MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;
 
+  /// Return whether the block terminate with divergent branch.
+  /// Note this only work before lowering the pseudo control flow instructions.
+  bool hasDivergentBranch(const MachineBasicBlock *MBB) const;
+
   void insertIndirectBranch(MachineBasicBlock &MBB,
                             MachineBasicBlock &NewDestBB,
                             MachineBasicBlock &RestoreBB, const DebugLoc &DL,
                             int64_t BrOffset, RegScavenger *RS) const override;
 
   bool analyzeBranchImpl(MachineBasicBlock &MBB,
                          MachineBasicBlock::iterator I,
                          MachineBasicBlock *&TBB,

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

if (MI.getOpcode() == AMDGPU::S_SETPC_B64) {
     // This would be a difficult analysis to perform, but can always be legal so
     // there's no need to analyze it.
     return nullptr;
   }
 
   return MI.getOperand(0).getMBB();
 }
 
+bool SIInstrInfo::hasDivergentBranch(const MachineBasicBlock *MBB) const {
+  for (const MachineInstr &MI : MBB->terminators()) {
+    if (MI.getOpcode() == AMDGPU::SI_NON_UNIFORM_BRCOND_PSEUDO ||
+        MI.getOpcode() == AMDGPU::SI_IF || MI.getOpcode() == AMDGPU::SI_ELSE ||
+        MI.getOpcode() == AMDGPU::SI_LOOP)
+      return true;
+  }
+  return false;
+}
+
 void SIInstrInfo::insertIndirectBranch(MachineBasicBlock &MBB,
                                        MachineBasicBlock &DestBB,
                                        MachineBasicBlock &RestoreBB,
                                        const DebugLoc &DL, int64_t BrOffset,
                                        RegScavenger *RS) const {
   assert(RS && "RegScavenger required for long branching");
   assert(MBB.empty() &&
          "new block should be inserted for expanding unconditional branch");

llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp

 ///    we need to invent an available value for the SSAUpdater. Choices are
 ///    0 and undef, with differing consequences for how to merge values etc.
 ///
 /// TODO: We could use region analysis to quickly skip over SESE regions during
 ///       the traversal.
 ///
 class PhiIncomingAnalysis {
   MachinePostDominatorTree &PDT;
+  const SIInstrInfo *TII;
 
   // For each reachable basic block, whether it is a source in the induced
   // subgraph of the CFG.
   DenseMap<MachineBasicBlock *, bool> ReachableMap;
   SmallVector<MachineBasicBlock *, 4> ReachableOrdered;
   SmallVector<MachineBasicBlock *, 4> Stack;
   SmallVector<MachineBasicBlock *, 4> Predecessors;
 
 public:
-  PhiIncomingAnalysis(MachinePostDominatorTree &PDT) : PDT(PDT) {}
+  PhiIncomingAnalysis(MachinePostDominatorTree &PDT, const SIInstrInfo *TII)
+      : PDT(PDT), TII(TII) {}
 
   /// Returns whether \p MBB is a source in the induced subgraph of reachable
   /// blocks.
   bool isSource(MachineBasicBlock &MBB) const {
     return ReachableMap.find(&MBB)->second;
   }
 
   ArrayRef<MachineBasicBlock *> predecessors() const { return Predecessors; }
for (MachineBasicBlock *MBB : IncomingBlocks) {
         continue;
       }
 
       ReachableMap.try_emplace(MBB, false);
       ReachableOrdered.push_back(MBB);
 
       // If this block has a divergent terminator and the def block is its
       // post-dominator, the wave may first visit the other successors.
-      bool Divergent = false;
-      for (MachineInstr &MI : MBB->terminators()) {
-        if (MI.getOpcode() == AMDGPU::SI_NON_UNIFORM_BRCOND_PSEUDO ||
-            MI.getOpcode() == AMDGPU::SI_IF ||
-            MI.getOpcode() == AMDGPU::SI_ELSE ||
-            MI.getOpcode() == AMDGPU::SI_LOOP) {
-          Divergent = true;
-          break;
-        }
-      }
-
-      if (Divergent && PDT.dominates(&DefBlock, MBB))
+      if (TII->hasDivergentBranch(MBB) && PDT.dominates(&DefBlock, MBB))
         append_range(Stack, MBB->successors());
     }
 
     while (!Stack.empty()) {
       MachineBasicBlock *MBB = Stack.pop_back_val();
       if (!ReachableMap.try_emplace(MBB, false).second)
         continue;
       ReachableOrdered.push_back(MBB);
for (MachineBasicBlock &MBB : *MF) {
     DeadCopies.clear();
   }
   return Changed;
 }
 
 bool SILowerI1Copies::lowerPhis() {
   MachineSSAUpdater SSAUpdater(*MF);
   LoopFinder LF(*DT, *PDT);
-  PhiIncomingAnalysis PIA(*PDT);
+  PhiIncomingAnalysis PIA(*PDT, TII);
   SmallVector<MachineInstr *, 4> Vreg1Phis;
   SmallVector<MachineBasicBlock *, 4> IncomingBlocks;
   SmallVector<unsigned, 4> IncomingRegs;
   SmallVector<unsigned, 4> IncomingUpdated;
 #ifndef NDEBUG
   DenseSet<unsigned> PhiRegisters;
 #endif