[MachineCSE] Use TargetInstrInfo::isAsCheapAsAMove in isPRECandidate.

[craig.topper]

Summary

Some targets like RISC-V require operands to be inspected to
determine if an instruction is similar to a move.

Spotted while investigating code differences between using an ADDI
vs an ADDIW. RISC-V has the isAsCheapAsAMove flag for ADDI, but
the TII hook checks the immediate is 0 or the register is X0. ADDIW
is never generated with X0 or with an immediate of 0 so it doesn't
have the isAsCheapAsAMove flag.

I don't know enough about the PRE code to write a test for this yet.

[craig.topper]

Looks like this was previously submitted as D113885

llvm/lib/CodeGen/MachineCSE.cpp

 //===- MachineCSE.cpp - Machine Common Subexpression Elimination Pass -----===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //

 
 // We use stronger checks for PRE candidate rather than for CSE ones to embrace
 // checks inside ProcessBlockCSE(), not only inside isCSECandidate(). This helps
 // to exclude instrs created by PRE that won't be CSEed later.
 bool MachineCSE::isPRECandidate(MachineInstr *MI) {
   if (!isCSECandidate(MI) ||
       MI->isNotDuplicable() ||
       MI->mayLoad() ||
-      MI->isAsCheapAsAMove() ||
+      TII->isAsCheapAsAMove(*MI) ||
       MI->getNumDefs() != 1 ||
       MI->getNumExplicitDefs() != 1)
     return false;
 
   for (const auto &def : MI->defs())
     if (!Register::isVirtualRegister(def.getReg()))
       return false;